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Special Issue "FPGA Applications and Future Trends"

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A special issue of Micromachines (ISSN 2072-666X). This special issue belongs to the section "E：Engineering and Technology".

Deadline for manuscript submissions: 15 August 2023 | Viewed by 2385

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Special Issue Editor

Dr. José de Jesús Rangel Magdaleno

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Guest Editor

Digital Systems Group, Electronics Department, Instituto Nacional de Astrofísica, Óptica y Electrónica, Luis Enrique Erro #1, Tonantzintla, Puebla, México C.P. 72840, Mexico
Interests: FPGA; instrumentation; mechatronics; digital systems; fault detection
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Special Issue Information

Dear Colleagues,

Currently, the use of FPGAs (field-programmable gate arrays) has been extended to several areas of engineering, such as security, biomedical, control, power systems, instrumentation, automotive, astronomy, and particle physics, to name a few.

The flexibility and reconfigurability of FPGAs allow them to be a tool used for rapid prototyping, in addition to offering parallel processing enabling the control of several systems within the same FPGA. Furthermore, technological advances have allowed the integration of microprocessor architectures, facilitating the handling of sequential tasks without neglecting the advantages of the FPGA architecture.

This Special Issue provides a forum for the presentation of new and improved FPGA-based applications, including (but not limited to):

Cryptography;
Control;
Embedded systems;
Power systems;
Monitoring;
Signal processing;
Intelligent systems;
Image processing;
Biomedical application;
Robotics;
Industrial applications;
Reconfigurable computing;
Particle physics;
Deep neural networks.

Dr. José de Jesús Rangel Magdaleno
Guest Editor

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Micromachines is an international peer-reviewed open access monthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2000 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

FPGAs
high-level synthesis
Verilog
VHDL
embedded systems
reconfigurable computing

Published Papers (4 papers)

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Research

Open AccessArticle

High-Speed Hardware Architecture Based on Error Detection for KECCAK

Hassen Mestiri

and

Imen Barraj

Micromachines 2023, 14(6), 1129; https://doi.org/10.3390/mi14061129 - 27 May 2023

Viewed by 327

Abstract

The hash function KECCAK integrity algorithm is implemented in cryptographic systems to provide high security for any circuit requiring integrity and protect the transmitted data. Fault attacks, which can extricate confidential data, are one of the most effective physical attacks against KECCAK hardware. Several KECCAK fault detection systems have been proposed to counteract fault attacks. The present research proposes a modified KECCAK architecture and scrambling algorithm to protect against fault injection attacks. Thus, the KECCAK round is modified so that it consists of two parts with input and pipeline registers. The scheme is independent of the KECCAK design. Iterative and pipeline designs are both protected by it. To test the resilience of the suggested detection system approach fault attacks, we conduct permanent as well as transient fault attacks, and we evaluate the fault detection capabilities (99.9999% for transient faults and 99.999905% for permanent faults). The KECCAK fault detection scheme is modeled using VHDL language and implemented on an FPGA hardware board. The experimental results show that our technique effectively secures the KECCAK design. It can be carried out with little difficulty. In addition, the experimental FPGA results demonstrate the proposed KECCAK detection scheme’s low area burden, high efficiency and working frequency. Full article

(This article belongs to the Special Issue FPGA Applications and Future Trends)

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Open AccessArticle

An Improved Blind Zone Channelization Structure and Rapid Implementation Method

Ziliang Jia

and

Hongxia Liu

Micromachines 2023, 14(5), 1091; https://doi.org/10.3390/mi14051091 - 22 May 2023

Viewed by 286

Abstract

The paper proposes an enhanced design for broadband digital receivers that aims to improve signal capture probability, real-time performance, and the hardware development cycle. To overcome the issue of false signals in the blind zone channelization structure, this paper introduces an improved joint-decision channelization structure that reduces channel ambiguity during signal reception. Xilinx’s high-level synthesis (HLS) tools are used for accelerated algorithm implementation, and techniques such as pipelining and loop parallelization are employed to reduce system latency. The entire system is implemented on FPGA. The simulation results demonstrate that the proposed solution effectively eliminates channel ambiguity, improves algorithm implementation speed, and meets the design requirements. Full article

(This article belongs to the Special Issue FPGA Applications and Future Trends)

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Open AccessArticle

FPGA Implementation for Elliptic Curve Cryptography Algorithm and Circuit with High Efficiency and Low Delay for IoT Applications

and

Micromachines 2023, 14(5), 1037; https://doi.org/10.3390/mi14051037 - 12 May 2023

Viewed by 476

Abstract

The Internet of Things requires greater attention to the security and privacy of the network. Compared to other public-key cryptosystems, elliptic curve cryptography can provide better security and lower latency with shorter keys, rendering it more suitable for IoT security. This paper presents [...] Read more.

p_{256}

prime field for IoT security applications. A modular square unit utilizes a fast partial Montgomery reduction algorithm, demanding just a mere four clock cycles to complete a modular square operation. The modular square unit can be computed simultaneously with the modular multiplication unit, consequently improving the speed of point multiplication operations. Synthesized on the Xilinx Virtex-7 FPGA platform, the proposed architecture completes one PM operation in 0.08 ms using 23.1 k LUTs at 105.3 MHz. These results show significantly better performance compared to that in previous works. Full article

(This article belongs to the Special Issue FPGA Applications and Future Trends)

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Open AccessArticle

A Real-Time FPGA-Based Metaheuristic Processor to Efficiently Simulate a New Variant of the PSO Algorithm

and

Micromachines 2023, 14(4), 809; https://doi.org/10.3390/mi14040809 - 31 Mar 2023

Viewed by 662

Abstract

Nowadays, high-performance audio communication devices demand superior audio quality. To improve the audio quality, several authors have developed acoustic echo cancellers based on particle swarm optimization algorithms (PSO). However, its performance is reduced significantly since the PSO algorithm suffers from premature convergence. To overcome this issue, we propose a new variant of the PSO algorithm based on the Markovian switching technique. Furthermore, the proposed algorithm has a mechanism to dynamically adjust the population size over the filtering process. In this way, the proposed algorithm exhibits great performance by reducing its computational cost significantly. To adequately implement the proposed algorithm in a Stratix IV GX EP4SGX530 FPGA, we present for the first time, the development of a parallel metaheuristic processor, in which each processing core simulates the different number of particles by using the time-multiplexing technique. In this way, the variation of the size of the population can be effective. Therefore, the properties of the proposed algorithm along with the proposed parallel hardware architecture potentially allow the development of high-performance acoustic echo canceller (AEC) systems. Full article

(This article belongs to the Special Issue FPGA Applications and Future Trends)

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