Journal of Low Power Electronics and Applications

17 pages, 7606 KiB

Open AccessArticle

An Ultra Low Power Integer-N PLL with a High-Gain Sampling Phase Detector for IOT Applications in 65 nm CMOS

by Javad Tavakoli, Hossein Miri Lavasani and Samad Sheikhaei

J. Low Power Electron. Appl. 2023, 13(4), 65; https://doi.org/10.3390/jlpea13040065 - 17 Dec 2023

Viewed by 1792

A low-power and low-jitter 1.2 GHz Integer-N PLL (INPLL) is designed in a 65 nm standard CMOS process. A novel high-gain sampling phase detector (PD), which takes advantage of a transconductance (Gm) cell to boost the gain, is developed to increase the phase [...] Read more.

A low-power and low-jitter 1.2 GHz Integer-N PLL (INPLL) is designed in a 65 nm standard CMOS process. A novel high-gain sampling phase detector (PD), which takes advantage of a transconductance (Gm) cell to boost the gain, is developed to increase the phase detection gain by ~100× compared to the Phase-Frequency Detectors (PFDs) used in conventional PLLs. Using this high detection gain, the noise contribution of the PFD and Charge Pump (CP), reference clock, and dividers on the PLL output is minimized, enabling low output jitter at low power, even when using low-frequency reference clocks. To provide a sufficient frequency locking range, an auxiliary frequency-locked loop (AFLL) is embedded within the INPLL. An integrated Lock Detector (LD) helps detect the INPLL locked state and disables the AFLL to save on power consumption and minimize its impact on the INPLL jitter. The proposed INPLL layout measures 700 µm × 350 µm, consumes 350 µW, and exhibits an integrated phase noise (IPN) of −37 dBc (from 10 kHz to 10 MHz), equivalent to 2.9 ps rms jitter, while keeping the spur level 64 dBc lower, resulting in jitter figure of Merit (

F o M_{j i t t e r}

) ~−236 dB. Full article

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9 pages, 3852 KiB

Open AccessCommunication

Design of a Low-Power Delay-Locked Loop-Based 8× Frequency Multiplier in 22 nm FDSOI

by Naveed and Jeff Dix

J. Low Power Electron. Appl. 2023, 13(4), 64; https://doi.org/10.3390/jlpea13040064 - 12 Dec 2023

Viewed by 1612

Abstract

A low-power delay-locked loop (DLL)-based frequency multiplier is presented. The multiplier is designed in 22 nm FDSOI and achieves 8× multiplication. The proposed DLL uses a new simple duty cycle correction circuit and is XOR logic-based for frequency multiplication. Current starved delay cells [...] Read more.

A low-power delay-locked loop (DLL)-based frequency multiplier is presented. The multiplier is designed in 22 nm FDSOI and achieves 8× multiplication. The proposed DLL uses a new simple duty cycle correction circuit and is XOR logic-based for frequency multiplication. Current starved delay cells are used to make the circuit power efficient. The circuit uses three 2× stages instead of an edge combiner to achieve 8× multiplication, thus requiring far less power and chip area as compared to conventional phase-locked loop (PLL) circuits. The proposed 8× multiplier occupies an active area of 0.09 mm². The measurement result shows ultra-low power consumption of 130 µW at 0.8 V supply. The post-layout simulation shows a timing jitter of 24 ps (pk-pk) at 2.44 GHz. Full article

(This article belongs to the Special Issue Ultra-Low-Power ICs for the Internet of Things Vol. 2)

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15 pages, 1799 KiB

Open AccessArticle

Signal Filtering Using Neuromorphic Measurements

by Dorian Florescu and Daniel Coca

J. Low Power Electron. Appl. 2023, 13(4), 63; https://doi.org/10.3390/jlpea13040063 - 06 Dec 2023

Viewed by 1493

Abstract

Digital filtering is a fundamental technique in digital signal processing, which operates on a digital sequence without any information on how the sequence was generated. This paper proposes a methodology for designing the equivalent of digital filtering for neuromorphic samples, which are a [...] Read more.

Digital filtering is a fundamental technique in digital signal processing, which operates on a digital sequence without any information on how the sequence was generated. This paper proposes a methodology for designing the equivalent of digital filtering for neuromorphic samples, which are a low-power alternative to conventional digital samples. In the literature, filtering using neuromorphic samples is performed by filtering the reconstructed analog signal, which is required to belong to a predefined input space. We show that this requirement is not necessary, and introduce a new method for computing the neuromorphic samples of the filter output directly from the input samples, backed by theoretical guarantees. We show numerically that we can achieve a similar accuracy compared to that of the conventional method. However, given that we bypass the analog signal reconstruction step, our results show significantly reduced computation time for the proposed method and good performance even when signal recovery is not possible. Full article

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30 pages, 6794 KiB

Open AccessReview

Applications of Sustainable Hybrid Energy Harvesting: A Review

by Hamna Shaukat, Ahsan Ali, Shaukat Ali, Wael A. Altabey, Mohammad Noori and Sallam A. Kouritem

J. Low Power Electron. Appl. 2023, 13(4), 62; https://doi.org/10.3390/jlpea13040062 - 26 Nov 2023

Cited by 4 | Viewed by 2984

Abstract

This paper provides a short review of sustainable hybrid energy harvesting and its applications. The potential usage of self-powered wireless sensor (WSN) systems has recently drawn a lot of attention to sustainable energy harvesting. The objective of this research is to determine the [...] Read more.

This paper provides a short review of sustainable hybrid energy harvesting and its applications. The potential usage of self-powered wireless sensor (WSN) systems has recently drawn a lot of attention to sustainable energy harvesting. The objective of this research is to determine the potential of hybrid energy harvesters to help single energy harvesters overcome their energy deficiency problems. The major findings of the study demonstrate how hybrid energy harvesting, which integrates various energy conversion technologies, may increase power outputs, and improve space utilization efficiency. Hybrid energy harvesting involves collecting energy from multiple sources and converting it into electrical energy using various transduction mechanisms. By properly integrating different energy conversion technologies, hybridization can significantly increase power outputs and improve space utilization efficiency. Here, we present a review of recent progress in hybrid energy-harvesting systems for sustainable green energy harvesting and their applications in different fields. This paper starts with an introduction to hybrid energy harvesting, showing different hybrid energy harvester configurations, i.e., the integration of piezoelectric and electromagnetic energy harvesters; the integration of piezoelectric and triboelectric energy harvesters; the integration of piezoelectric, triboelectric, and electromagnetic energy harvesters; and others. The output performance of common hybrid systems that are reported in the literature is also outlined in this review. Afterwards, various potential applications of hybrid energy harvesting are discussed, showing the practical attainability of the technology. Finally, this paper concludes by making recommendations for future research to overcome the difficulties in developing hybrid energy harvesters. The recommendations revolve around improving energy conversion efficiency, developing advanced integration techniques, and investigating new hybrid configurations. Overall, this study offers insightful information on sustainable hybrid energy harvesting together with quantitative information, numerical findings, and useful research recommendations that progress and promote the use of this technology. Full article

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16 pages, 2454 KiB

Open AccessArticle

Application Specific Reconfigurable Processor for Eyeblink Detection from Dual-Channel EOG Signal

by Diba Das, Mehdi Hasan Chowdhury, Aditta Chowdhury, Kamrul Hasan, Quazi Delwar Hossain and Ray C. C. Cheung

J. Low Power Electron. Appl. 2023, 13(4), 61; https://doi.org/10.3390/jlpea13040061 - 23 Nov 2023

Viewed by 1583

Abstract

The electrooculogram (EOG) is one of the most significant signals carrying eye movement information, such as blinks and saccades. There are many human–computer interface (HCI) applications based on eye blinks. For example, the detection of eye blinks can be useful for paralyzed people [...] Read more.

The electrooculogram (EOG) is one of the most significant signals carrying eye movement information, such as blinks and saccades. There are many human–computer interface (HCI) applications based on eye blinks. For example, the detection of eye blinks can be useful for paralyzed people in controlling wheelchairs. Eye blink features from EOG signals can be useful in drowsiness detection. In some applications of electroencephalograms (EEGs), eye blinks are considered noise. The accurate detection of eye blinks can help achieve denoised EEG signals. In this paper, we aimed to design an application-specific reconfigurable binary EOG signal processor to classify blinks and saccades. This work used dual-channel EOG signals containing horizontal and vertical EOG signals. At first, the EOG signals were preprocessed, and then, by extracting only two features, the root mean square (RMS) and standard deviation (STD), blink and saccades were classified. In the classification stage, 97.5% accuracy was obtained using a support vector machine (SVM) at the simulation level. Further, we implemented the system on Xilinx Zynq-7000 FPGAs by hardware/software co-design. The processing was entirely carried out using a hybrid serial–parallel technique for low-power hardware optimization. The overall hardware accuracy for detecting blinks was 95%. The on-chip power consumption for this design was 0.8 watts, whereas the dynamic power was 0.684 watts (86%), and the static power was 0.116 watts (14%). Full article

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16 pages, 5007 KiB

Open AccessArticle

Design of Current Equalization Circuit in Dual Ethernet Power Supply System

by Xingyu Guan, Xinyuan Hu, Junkai Zhang and Yanfeng Jiang

J. Low Power Electron. Appl. 2023, 13(4), 60; https://doi.org/10.3390/jlpea13040060 - 18 Nov 2023

Viewed by 1473

Abstract

A current-balancing circuit for a dual-channel Ethernet power supply system is designed in this paper, which can be used to solve the mismatch between the two channels caused by unavoidable factors, such as mismatched resistances, temperatures and voltages. Based on the design, the [...] Read more.

A current-balancing circuit for a dual-channel Ethernet power supply system is designed in this paper, which can be used to solve the mismatch between the two channels caused by unavoidable factors, such as mismatched resistances, temperatures and voltages. Based on the design, the mismatch of the currents between the two power transmission paths can be controlled to be less than 1% of the original ones. It can be operated under these conditions with the changes of the load current and the PSE output voltage. The maximum output power of the dual-channel power supply can reach up to 96.5 W. When the DC–DC conversion efficiency is less than 75%, it can still provide 72 W for the PD end, meeting the requirements of the PoE power system. The current-balancing circuit designed in the paper has potential application value to improve the dual PoE power supply system. Full article

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16 pages, 1828 KiB

Open AccessArticle

From SW Timing Analysis and Safety Logging to HW Implementation: A Possible Solution with an Integrated and Low-Power Logger Approach

by Francesco Cosimi, Antonio Arena, Paolo Gai and Sergio Saponara

J. Low Power Electron. Appl. 2023, 13(4), 59; https://doi.org/10.3390/jlpea13040059 - 02 Nov 2023

Viewed by 1358

Abstract

In this manuscript, we propose a configurable hardware device in order to build a coherent data log unit. We address the need for analyzing mixed-criticality systems, thus guaranteeing the best performances without introducing additional sources of interference. Log data are essential to inspect [...] Read more.

In this manuscript, we propose a configurable hardware device in order to build a coherent data log unit. We address the need for analyzing mixed-criticality systems, thus guaranteeing the best performances without introducing additional sources of interference. Log data are essential to inspect the behavior of running applications when safety analyses or worst-case execution time measurements are performed. Furthermore, performance and timing investigations are useful for solving scheduling issues to balance resource budgets and investigate misbehavior and failure causes. We additionally present a performance evaluation and log capabilities by means of simulations on a RISC-V use case. The simulations highlight that such a data log unit can trace the execution from a single- to an octa-core microcontroller. Such an analysis allows a silicon developer to obtain the right sizings and timings of devices during the development phase. Finally, we present an analysis of a real RISC-V implementation for a Xilinx UltraScale+ FPGA, which was obtained with Vivado 2018. The results show that our data log unit implementation does not introduce a significant area overhead if compared to the RISC-V core targeted for tests, and that the timing constraints are not violated. Full article

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20 pages, 1805 KiB

Open AccessArticle

Analog System High-Level Synthesis for Energy-Efficient Reconfigurable Computing

by Afolabi Ige, Linhao Yang, Hang Yang, Jennifer Hasler and Cong Hao

J. Low Power Electron. Appl. 2023, 13(4), 58; https://doi.org/10.3390/jlpea13040058 - 26 Oct 2023

Viewed by 1490

Abstract

The design of analog computing systems requires significant human resources and domain expertise due to the lack of automation tools to enable these highly energy-efficient, high-performance computing nodes. This work presents the first automated tool flow from a high-level representation to a reconfigurable [...] Read more.

The design of analog computing systems requires significant human resources and domain expertise due to the lack of automation tools to enable these highly energy-efficient, high-performance computing nodes. This work presents the first automated tool flow from a high-level representation to a reconfigurable physical device. This tool begins with a high-level algorithmic description, utilizing either our custom Python framework or the XCOS GUI, to compile and optimize computations for integration into an Integrated Circuit (IC) design or a Field Programmable Analog Array (FPAA). An energy-efficient embedded speech classifier benchmark illustrates the tool demonstration, automatically generating GDSII layout or FPAA switch list targeting. Full article

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19 pages, 5138 KiB

Open AccessArticle

Design and Implementation of an Open-Source and Internet-of-Things-Based Health Monitoring System

by Sehrash Ashraf, Shahnaz Parveen Khattak and Mohammad Tariq Iqbal

J. Low Power Electron. Appl. 2023, 13(4), 57; https://doi.org/10.3390/jlpea13040057 - 22 Oct 2023

Cited by 1 | Viewed by 2410

Abstract

Across the globe, COVID-19 had far-reaching impacts that included healthcare facilities, public health, as well as all forms of transport. Hospitals were experiencing staffing shortages at the same time as patients were experiencing healthcare issues. Consequently, even in developing countries without full access [...] Read more.

Across the globe, COVID-19 had far-reaching impacts that included healthcare facilities, public health, as well as all forms of transport. Hospitals were experiencing staffing shortages at the same time as patients were experiencing healthcare issues. Consequently, even in developing countries without full access to technology, remote health monitoring became necessary. There was a greater severity of the pandemic in countries with fewer financial and technical resources. It became evident that such remote health monitoring systems that not only allowed the user to monitor their basic health information, but also to communicate that information to healthcare personnel, were essential. In this article, we present an open-source, Internet-of-Things (IoT)-based health monitoring system that is intended to mitigate the basic healthcare challenges posed by remote areas of developing countries. To facilitate remote health monitoring, an IoT server has been configured on an ESP32 chip as part of this study. The microcontroller was also connected to a Max 30100 sensor, a DHT11 sensor, and a global positioning system GPS module. As a result of this, the user is able to measure the heart rate (HR), blood oxygen level (SpO₂), human body temperature, ambient temperature and humidity, as well as the location of the user. Through the internet protocol, the important vital signs can be displayed in real time on the dashboard using a private communication network. This article presents the details of a complete system design, implementation, testing, and results. Such systems can help limit the spread of infectious diseases like COVID-19. Full article

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22 pages, 1584 KiB

Open AccessArticle

Theoretical Validation and Hardware Implementation of Dynamic Adaptive Scheduling for Heterogeneous Systems on Chip

by A. Alper Goksoy, Sahil Hassan, Anish Krishnakumar, Radu Marculescu, Ali Akoglu and Umit Y. Ogras

J. Low Power Electron. Appl. 2023, 13(4), 56; https://doi.org/10.3390/jlpea13040056 - 17 Oct 2023

Cited by 1 | Viewed by 1337

Abstract

Domain-specific systems on chip (DSSoCs) aim to narrow the gap between general-purpose processors and application-specific designs. CPU clusters enable programmability, whereas hardware accelerators tailored to the target domain minimize task execution times and power consumption. Traditional operating system (OS) schedulers can diminish the [...] Read more.

Domain-specific systems on chip (DSSoCs) aim to narrow the gap between general-purpose processors and application-specific designs. CPU clusters enable programmability, whereas hardware accelerators tailored to the target domain minimize task execution times and power consumption. Traditional operating system (OS) schedulers can diminish the potential of DSSoCs, as their execution times can be orders of magnitude larger than the task execution time. To address this problem, we propose a dynamic adaptive scheduling (DAS) framework that combines the advantages of a fast, low-overhead scheduler and a sophisticated, high-performance scheduler with a larger overhead. We present a novel runtime classifier that chooses the better scheduler type as a function of the system workload, leading to improved system performance and energy-delay product (EDP). Experiments with five real-world streaming applications indicate that DAS consistently outperforms fast, low-overhead, and slow, sophisticated schedulers. DAS achieves a 1.29× speedup and a 45% lower EDP than the sophisticated scheduler under low data rates and a 1.28× speedup and a 37% lower EDP than the fast scheduler when the workload complexity increases. Furthermore, we demonstrate that the superior performance of the DAS framework also applies to hardware platforms, with up to a 48% and 52% reduction in the execution time and EDP, respectively. Full article

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11 pages, 3211 KiB

Open AccessCommunication

A Low-Power Analog Cell for Implementing Spiking Neural Networks in 65 nm CMOS

by John S. Venker, Luke Vincent and Jeff Dix

J. Low Power Electron. Appl. 2023, 13(4), 55; https://doi.org/10.3390/jlpea13040055 - 17 Oct 2023

Viewed by 1626

Abstract

A Spiking Neural Network (SNN) is realized within a 65 nm CMOS process to demonstrate the feasibility of its constituent cells. Analog hardware neural networks have shown improved energy efficiency in edge computing for real-time-inference applications, such as speech recognition. The proposed network [...] Read more.

A Spiking Neural Network (SNN) is realized within a 65 nm CMOS process to demonstrate the feasibility of its constituent cells. Analog hardware neural networks have shown improved energy efficiency in edge computing for real-time-inference applications, such as speech recognition. The proposed network uses a leaky integrate and fire neuron scheme for computation, interleaved with a Spike Timing Dependent Plasticity (STDP) circuit for implementing synaptic-like weights. The low-power, asynchronous analog neurons and synapses are tailored for the VLSI environment needed to effectively make use of hardware SSN systems. To demonstrate functionality, a feed-forward Spiking Neural Network composed of two layers, the first with ten neurons and the second with six, is implemented. The neuron design operates with 2.1 pJ of power per spike and 20 pJ per synaptic operation. Full article

(This article belongs to the Special Issue Energy Efficiency in Edge Computing)

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21 pages, 4797 KiB

Open AccessArticle

Design and Optimization of an Ultra-Low-Power Cross-Coupled LC VCO with a DFF Frequency Divider for 2.4 GHz RF Receivers Using 65 nm CMOS Technology

by Muhammad Faisal Siddiqui, Mukesh Kumar Maheshwari, Muhammad Raza and Aurangzeb Rashid Masud

J. Low Power Electron. Appl. 2023, 13(4), 54; https://doi.org/10.3390/jlpea13040054 - 07 Oct 2023

Cited by 1 | Viewed by 2234

Abstract

This article presents the design and optimization of a tunable quadrature differential LC CMOS voltage-controlled oscillator (VCO) with a D flip-flop (DFF) frequency divider. The VCO is designed for the low-power and low-phase-noise applications of 2.4 GHz IoT/BLE receivers and wireless sensor devices. [...] Read more.

This article presents the design and optimization of a tunable quadrature differential LC CMOS voltage-controlled oscillator (VCO) with a D flip-flop (DFF) frequency divider. The VCO is designed for the low-power and low-phase-noise applications of 2.4 GHz IoT/BLE receivers and wireless sensor devices. The proposed design comprises the proper stacking of an LC VCO and a DFF frequency divider and is simulated using a TSMC 65 nm CMOS technology, and it has a tuning range of 4.4 to 5.7 GHz. The voltage headroom is preserved using a high-impedance on-chip passive inductor at the tail for filtering and enabling true differential operation. The VCO and frequency divider consume as low as 2.02 mW altogether, with the VCO section consuming only 0.47 mW. The active area of the chip including the pads is only 0.47 mm². The designed VCO achieved a much better phase noise of −118.36 dBc/Hz at a 1 MHz offset frequency with 1.2 V supply voltages. The design produced a much better FoM of −196.44 dBc/Hz compared to other related research. Full article

(This article belongs to the Special Issue Ultra-Low-Power ICs for the Internet of Things Vol. 2)

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15 pages, 10415 KiB

Open AccessArticle

A Power-Gated 8-Transistor Physically Unclonable Function Accelerates Evaluation Speeds

by Yujin Zheng, Alex Yakovlev and Alex Bystrov

J. Low Power Electron. Appl. 2023, 13(4), 53; https://doi.org/10.3390/jlpea13040053 - 29 Sep 2023

Cited by 1 | Viewed by 1404

Abstract

The proposed 8-Transistor (8T) Physically Unclonable Function (PUF), in conjunction with the power gating technique, can significantly accelerate a single evaluation cycle more than 100,000 times faster than a 6-Transistor (6T) Static Random-Access Memory (SRAM) PUF. The 8T PUF is built to swiftly [...] Read more.

The proposed 8-Transistor (8T) Physically Unclonable Function (PUF), in conjunction with the power gating technique, can significantly accelerate a single evaluation cycle more than 100,000 times faster than a 6-Transistor (6T) Static Random-Access Memory (SRAM) PUF. The 8T PUF is built to swiftly eliminate data remanence and maximise physical mismatch. Moreover, a two-phase power gating module is devised to provide controllable power on/off cycles for the chosen PUF clusters in order to facilitate fast statistical measurements and curb the in-rush current. The architecture and hardware implementation of the power-gated PUF are developed to accommodate fast multiple evaluations of PUF Responses. The fast speed enables a new data processing method, which coordinates Dark-bit masking and Multiple Temporal Majority Voting (TMV) in different Process, Voltage and Temperature (PVT) corners or during field usage, hence greatly reducing the Bit Error Rate (BER) and the hardware penalty for error correction. The designs are based on the UMC 65 nm technology and aim to tape out an Application-Specific Integrated Circuit (ASIC) chip. Post-layout Monte Carlo (MC) simulations are performed with Cadence, and the extracted PUF Responses are processed with Matlab to evaluate the 8T PUF performance and statistical metrics for subsequent inclusion in PUF Responses, which comprise the novelty of this approach. Full article

(This article belongs to the Special Issue Ultra-Low-Power ICs for the Internet of Things Vol. 2)

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J. Low Power Electron. Appl., Volume 13, Issue 4 (December 2023) – 13 articles

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