# An Ultra Low Power Integer-N PLL with a High-Gain Sampling Phase Detector for IOT Applications in 65 nm CMOS

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## Abstract

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## 1. Introduction

## 2. Exploring a 1.2 GHz INPLL Design with High-Gain LSPD

#### 2.1. Constraints of Traditional PFD-CP PLL

#### 2.2. Noise Contributions in Conventional PFD-CP PLL

## 3. Design of the Proposed PLL Utilizing LSPD

#### 3.1. Proposed High-Gain LSPD

_{REF}represents the frequency of the input reference clock. Assuming a constant f

_{REF}, the PD’s gain is determined by $\raisebox{1ex}{$\mathrm{I}$}\!\left/ \!\raisebox{-1ex}{$\mathrm{C}$}\right.$, which is equivalent to the slope of the ramp voltage. The maximum DPE is directly proportional to this term, as illustrated in Figure 3b. As previously mentioned, the proposed PD necessitates both REF and FB edges to occur during the rising phase from GND to VDD, which can be referred to as the “Phase Detection Window” (PDW). This time window dictates the maximum timing error or phase error that the PD can detect. By implementing a Lock Detector block, this timing window serves to identify out-of-lock conditions within the PLL.

_{REF}and Samp

_{FB}, correlates with the timing error between the REF and FB signals at the input of the LSPD. These sampled voltages are subsequently applied to the G

_{m}block, which produces the current flowing into the loop filter. It is crucial to choose the differential pair sizing and bias current such that the input offset voltage remains well below the desired minimum value of ΔV. The resultant current, denoted as ${I}_{Gm}$, is then introduced into the loop filter using a gate-switching structure, activated when the GMSW pulse is in its high state. Indeed, the Gm circuit in Figure 4a incorporates a conventional current mirror augmented by a gate-switching technique. The GMSW signal is generated using the circuit shown in Figure 4b.

_{REF}and Samp

_{FB}. This voltage difference determines the phase detection gain as follows:

#### 3.2. Proposed Sampling Integer-N PLL

#### 3.3. Lock Detector (LD) Block

_{1}-bit counters. Whenever each counter reaches the value A, it resets both counters and starts counting again from zero. The outputs of these counters are given to an equality comparator; if the output values of the counters are equal, the output of the comparator will be one. Since the frequency difference between REF and FB pulses is usually large at the startup, the two counters of the first stage always exhibit significantly different values. However, as the PLL approaches the phase-locked state, the counters’ output values get closer to each other, ultimately reaching the same value and indicating the phase-lock state.

_{2}-bit counter counts the number of cycles where the (CNT1==CNT2) condition is satisfied. Another equality comparator in the second stage verifies whether a certain number of cycles (identified as “B”) are counted, after which the LD is set. The phase-lock state is detected by the second-stage comparator, asserting the output signal of the LD block. Reset mechanisms are embedded in the LD block, allowing the structure to quickly recognize the transition of the PLL loop from the phase-locked to the out-of-lock state and reset the LD. The main parameters affecting the operation of the LD block are A, N

_{1}, B, and N

_{2}. In the proposed design, these parameters are set as $A=7,\text{}{N}_{1}=3,\text{}B=35,\text{}{N}_{2}=6$. The essential operation of the LD block at the PLL startup and moving into the phase-locked state is shown in Figure 7b. The frequency starts to increase and reaches its final value after PLL lock-time. Depending on the PLL transfer function, some overshooting behavior may be observed in the response, which can be minimized by adjusting the phase margin as necessary [23].

_{ref}–f

_{fb}, the condition in which the two counters of the first stage produce an equal output for A cycles should be investigated. In such cases, the maximum timing error $\Delta \mathrm{T}=\left|{\mathrm{T}}_{\mathrm{r}\mathrm{e}\mathrm{f}}-{\mathrm{T}}_{\mathrm{f}\mathrm{b}}\right|$ is ~$\frac{1}{\mathrm{A}}{\mathrm{T}}_{\mathrm{r}\mathrm{e}\mathrm{f}}$ (if ${\mathrm{T}}_{\mathrm{r}\mathrm{e}\mathrm{f}}<{\mathrm{T}}_{\mathrm{f}\mathrm{b}}$). In other words, the frequency error is in the range $\frac{\mathrm{A}-1}{\mathrm{A}}\frac{{\mathrm{F}}_{\mathrm{o}\mathrm{u}\mathrm{t}}}{\mathrm{N}}<\left|{\mathrm{f}}_{\mathrm{r}\mathrm{e}\mathrm{f}}-{\mathrm{f}}_{\mathrm{f}\mathrm{b}}\right|<\frac{\mathrm{A}+1}{\mathrm{A}}\frac{{\mathrm{F}}_{\mathrm{o}\mathrm{u}\mathrm{t}}}{\mathrm{N}}$ (N is the division modulus). For example, for A = 7 and ${\mathrm{F}}_{\mathrm{o}\mathrm{u}\mathrm{t}}=1.2\text{}\mathrm{G}\mathrm{H}\mathrm{z}$, the frequency range would be $1.03\text{}\mathrm{G}\mathrm{H}\mathrm{z}{\mathrm{f}}_{\mathrm{o}\mathrm{u}\mathrm{t}}1.37\text{}\mathrm{G}\mathrm{H}\mathrm{z}$. In transient state (i.e., PLL is not locked), the PLL frequency moves towards the desired frequency, and frequency error decreases. When the PLL output frequency reaches the frequency interval specified above (shown as F

_{min}< f < F

_{max}), the output of the first-stage comparator remains one. Then, the LD block works by first detecting when the frequency gets to the specified range (first stage). Once this point is reached, the counters in the second stage create a time delay equal to the expected locking time of the PLL. LD detects that PLL will lock if the frequency remains in the specified range (Figure 7b).

#### 3.4. Low-Power Class-C CMOS LC VCO

_{bias}, whose level can be adjusted to control the conduction angle, can be generated either on-chip or supplied from an external source. The PMOS cross-coupled pair also operates in class-C mode, since it shares the same bias current with the NMOS cross-coupled pair.

## 4. INPLL Simulation Results

_{REF}, is decreased from about 700 µV for the conventional INPLL to 30 µV in the LSPD-based INPLL, since the non-idealities associated with the conventional PFD-CP are eliminated. The phase noise performance of the two INPLLs is also simulated and compared with each other (Figure 13a). The noise contribution of critical blocks is also shown in the figure. For the proposed LSPD-based INPLL, the simulated integrated phase noise (IPN) from 10 kHz to 10 MHz is ~−37 dBc, resulting in ~0.02 rad rms jitter (2.9 ps rms jitter at 1.2 GHz). However, the simulated IPN for the conventional INPLL is ~−31.3 dBc, corresponding to ~2× larger jitter, i.e., ~0.038 rad rms or 5.1 ps rms at 1.2 GHz. This jitter reduction is directly attributed to the enhanced phase detection gain achieved through the use of the proposed LSPD. The simulated output spectrum of both INPLLs is shown in Figure 13b. The reference spurs are significantly attenuated, by as much as 22 dBc, in the proposed LSPD-based INPLL compared to the conventional INPLL. This improvement is mainly due to eliminating inherent non-idealities of the conventional PFD-CP structure (e.g., switching non-idealities).

## 5. Conclusions

## Author Contributions

## Funding

## Data Availability Statement

## Conflicts of Interest

## References

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**Figure 1.**(

**a**) Structure of a conventional three-state PFD and CP and its linear transfer characteristic; (

**b**) TSPC PFD structure.

**Figure 2.**(

**a**) Architecture of the conventional INPLL; (

**b**) linear phase domain model of conventional PFD-CP PLL.

**Figure 3.**(

**a**) Conceptual structure of the proposed LSPD (translating phase error into a voltage difference and then converting it into current injected into the loop filter); (

**b**) trade-off between phase detection gain and range.

**Figure 4.**(

**a**) Schematic of the proposed LSPD-Gm; (

**b**) tunable delay cell and GMSW pulse generation circuit; (

**c**) timing diagram of LSPD pulses; (

**d**) Pulse Generator Block (PGB); (REF-IN: Input Reference, PDWP: Phase Detection Window Pulse, REF: input to the loop, GMSW: G

_{m}window pulse, REFSW&FBSW: pulses determining the charging interval of the sampling capacitors).

**Figure 5.**Simulated performance of the proposed LSPD showing: (

**a**) transient response during the phase detection; (

**b**) Monte Carlo results of the phase detection gain; (

**c**) Gm output current across process corners and temperature; (

**d**) Monte Carlo results of the Gm output current for various input timing errors.

**Figure 6.**(

**a**) Block diagram of the proposed INPLL (details of PGB and LD are explained in Figure 4d and LD’s section respectively); (

**b**) utilized MMD structure.

**Figure 8.**Block diagram of the LD showing both stages and the reset paths (FCW: Frequency Control Word).

**Figure 10.**(

**a**) Class-C LC VCO Schematic; (

**b**) simulated performance of the designed inductor (SRF: Self-Resonance Frequency).

**Figure 11.**Simulated VCO tuning curves (

**a**) typical (TT), 27 °C; (

**b**) fast (FF), 85 °C and FF, −40 °C; and (

**c**) slow (SS), 85 °C and SS, −40 °C; (

**d**) VCO simulated phase noise showing both class-B and class-C performance.

**Figure 12.**(

**a**) The layout view of the proposed INPLL; (

**b**) simulated settling behavior of the proposed INPLL compared with that of an INPLL that uses conventional PFD-CP.

**Figure 13.**(

**a**) Simulated phase noise performance of the proposed INPLL compared with that of an INPLL that uses conventional PFD-CP; (

**b**) simulated output spectrum of the proposed INPLL compared with that of an INPLL that uses conventional PFD-CP.

Corner & Temp. | Supply (V) | Power Consumption $\left(\mathsf{\mu}\mathbf{W}\right)$ | Output Swing (mV) | Phase Noise @ 1 MHz (dBc/Hz) | Phase Noise @ 3 MHz (dBc/Hz) | FOM @ 3 MHz (dB) | ${\mathbf{K}}_{\mathbf{V}\mathbf{C}\mathbf{O}}$ (MHz/V) |
---|---|---|---|---|---|---|---|

TT, 27 | 1 | 150.1 | 380 | −119.6 | −129.5 | 189.7 | 153 |

1.05 | 152.4 | 383 | −120.4 | −129.6 | 189.8 | 155.1 | |

0.95 | 147.5 | 375 | −117.1 | −125 | 185.3 | 144 | |

FF, 85 | 1 | 150.5 | 300 | −117.5 | −127.4 | 187.6 | 129 |

1.05 | 152.9 | 303 | −118.2 | −127.6 | 187.7 | 131 | |

0.95 | 148.1 | 296.5 | −114.8 | −123 | 183.3 | 122.5 | |

FF, −40 | 1 | 150.1 | 343 | −122 | −131.8 | 192 | 150 |

1.05 | 152.5 | 346.5 | −122.7 | −131.9 | 192 | 152 | |

0.95 | 147.4 | 339 | −119.7 | −127 | 187.3 | 142 | |

SS, 85 | 1 | 151 | 348 | −119.1 | −128.8 | 189 | 155 |

1.05 | 153.4 | 351.5 | −117.3 | −127.3 | 187.5 | 157 | |

0.95 | 148.6 | 344 | −115.4 | −126.9 | 187.5 | 146.5 | |

SS, −40 | 1 | 151.5 | 412 | −123 | −131.8 | 192 | 181 |

1.05 | 154 | 416 | −121 | −130.2 | 190.4 | 183.5 | |

0.95 | 149 | 407.5 | −119.2 | −129.7 | 190 | 171 |

This Work | [11] | [12] | [13] | [14] | [3] | |
---|---|---|---|---|---|---|

PLL topology (INPLLs) | Analog | Sub-sampling | Analog | Type-I Analog | Sub-sampling | Sub-sampling |

Phase detection method | LSPD | SSPD | Conv. PFD-CP | XOR-PD & MSSF-LF | SSPD | SSPD |

Technology | 65 nm | 65 nm | 130 nm | 45 nm | 65 nm | 65 nm |

Supply voltage (V) | 1 | 0.935 | 1.2 | 1 | 1.2 | 1 |

Ref. Frequency (MHz) | 1 | 49.15 | 8.66 | 22.6 | 192 | 100 |

Output frequency (GHz) | 1.18–1.43 | 2.4 | 1.8 | 2.4 | 2.3 | 2.4 |

Power dissipation $\left(\mathsf{\mu}\mathrm{W}\right)$ | 350 | 5860 | 740 | 4000 | 4600 | 900 |

IPN (dBc) (10 kHz to 10 MHz) | −37 | −44 | −18 | −39.6 | −42 | −55 |

Rms Jitter (ps) | 2.9 | 0.63 | 15.97 | 0.97 | 0.72 | 0.161 |

Reference spur (dBc) | −62 | −55.2 | −52 | −65 | −37 | −67 |

Channel Selection | Y | N | N | N | N | N |

$FO{M}_{Jitter}$ [31] | −236.25 | −236.3 | −217.24 | −234.1 | −236 | −256 |

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## Share and Cite

**MDPI and ACS Style**

Tavakoli, J.; Lavasani, H.M.; Sheikhaei, S.
An Ultra Low Power Integer-N PLL with a High-Gain Sampling Phase Detector for IOT Applications in 65 nm CMOS. *J. Low Power Electron. Appl.* **2023**, *13*, 65.
https://doi.org/10.3390/jlpea13040065

**AMA Style**

Tavakoli J, Lavasani HM, Sheikhaei S.
An Ultra Low Power Integer-N PLL with a High-Gain Sampling Phase Detector for IOT Applications in 65 nm CMOS. *Journal of Low Power Electronics and Applications*. 2023; 13(4):65.
https://doi.org/10.3390/jlpea13040065

**Chicago/Turabian Style**

Tavakoli, Javad, Hossein Miri Lavasani, and Samad Sheikhaei.
2023. "An Ultra Low Power Integer-N PLL with a High-Gain Sampling Phase Detector for IOT Applications in 65 nm CMOS" *Journal of Low Power Electronics and Applications* 13, no. 4: 65.
https://doi.org/10.3390/jlpea13040065