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J. Low Power Electron. Appl., Volume 14, Issue 2 (June 2024) – 12 articles

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18 pages, 4842 KiB  
Article
Coordination of SRF-PLL and Grid Forming Inverter Control in Microgrid with Solar PV and Energy Storage
by V. Vignesh Babu, J. Preetha Roselyn and Prabha Sundaravadivel
J. Low Power Electron. Appl. 2024, 14(2), 29; https://doi.org/10.3390/jlpea14020029 - 21 May 2024
Viewed by 120
Abstract
Recently, there has been a huge advancement in renewable energy integration in power systems. Power converters with grid-forming or grid-following topologies are typically employed to link these decentralized power sources to the grid. However, because distributed generation has less inertia than synchronous generators, [...] Read more.
Recently, there has been a huge advancement in renewable energy integration in power systems. Power converters with grid-forming or grid-following topologies are typically employed to link these decentralized power sources to the grid. However, because distributed generation has less inertia than synchronous generators, their use of renewable energy sources threatens the electrical grid’s reliability. Suitable control approaches for ensuring frequency and voltage stability in the grid-connected form of operation are established in this study, which offers dynamic, seamless power switching in the islanded mode of operation. In this research, effective Phase Locked Loop (PLL) techniques for grid-forming (GFM) and grid-following (GFL) converters are designed to achieve a smooth transition from grid-tied to islanded mode of operation. In this work, PLL configurations are implemented while considering the active and reactive power, frequency, voltage, and current parameters of the system, and ensuring voltage and frequency stability. The simulation results in a microgrid network that ensures a smooth transition of power transfer while switching between modes of operation, and supports the voltage and frequency stability of the system. Full article
(This article belongs to the Special Issue Energy Aware Solutions for Battery Management Systems)
16 pages, 4060 KiB  
Article
A Microdevice in a Submicron CMOS for Closed-Loop Deep-Brain Stimulation (CLDBS)
by Tiago Matheus Nordi, Rodrigo Gounella, Marcio L. M. Amorim, Maximillam Luppe, João Navarro Soares Junior, Joao L. Afonso, Vitor Monteiro, Jose A. Afonso, Erich Talamoni Fonoff, Eduardo Colombari and João Paulo Carmo
J. Low Power Electron. Appl. 2024, 14(2), 28; https://doi.org/10.3390/jlpea14020028 - 17 May 2024
Viewed by 438
Abstract
Deep-brain stimulation (DBS) is a highly effective and safe medical treatment that improves the lives of patients with a wide range of neurological and psychiatric diseases. It has been established as a first-line tool in the treatment of these conditions for the past [...] Read more.
Deep-brain stimulation (DBS) is a highly effective and safe medical treatment that improves the lives of patients with a wide range of neurological and psychiatric diseases. It has been established as a first-line tool in the treatment of these conditions for the past two decades. Closed-loop deep-brain stimulation (CLDBS) advances this tool further by automatically adjusting the stimulation parameters in real time based on the brain’s response. In this context, this paper presents a low-noise amplifier (LNA) and a neurostimulator circuit fabricated using the low-power/low-voltage 65 nm CMOS process from TSMC. The circuits are specifically designed for implantable applications. To achieve the best tradeoff between input-referred noise and power consumption, metaheuristic algorithms were employed to determine and optimize the dimensions of the LNA devices during the design phase. Measurement results showed that the LNA had a gain of 41.2 dB; a 3 dB bandwidth spanning over three decades, from 1.5 Hz to 11.5 kHz; a power consumption of 5.9 µW; and an input-referred noise of 3.45 µVRMS, from 200 Hz to 11.5 kHz. The neurostimulator circuit is a programmable Howland current pump. Measurements have shown its capability to generate currents with arbitrary shapes and ranging from −325 µA to +318 µA. Simulations indicated a quiescent power consumption of 0.13 µW, with zero neurostimulation current. Both the LNA and the neurostimulator circuits are supplied with a 1.2 V voltage and occupy a microdevice area of 145 µm × 311 µm and 88 µm × 89 µm, respectively, making them suitable for implantation in applications involving closed-loop deep-brain stimulation. Full article
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20 pages, 377 KiB  
Review
A Survey of Short-Range Wireless Communication for Ultra-Low-Power Embedded Systems
by Billy Baker, John Woods, Martin J. Reed and Martin Afford
J. Low Power Electron. Appl. 2024, 14(2), 27; https://doi.org/10.3390/jlpea14020027 - 14 May 2024
Viewed by 453
Abstract
Wireless short-range communication has become widespread in the modern era, partly due to the advancement of the Internet of Things (IoT) and smart technology. This technology is now utilized in various sectors, including lighting, medical, and industrial applications. This article aims to examine [...] Read more.
Wireless short-range communication has become widespread in the modern era, partly due to the advancement of the Internet of Things (IoT) and smart technology. This technology is now utilized in various sectors, including lighting, medical, and industrial applications. This article aims to examine the historical, present, and forthcoming advancements in wireless short-range communication. Additionally, the review will analyze the modifications made to communication protocols, such as Bluetooth, RFID and NFC, in order to better accommodate modern applications. Batteryless technology, particularly batteryless NFC, is an emerging development in short-range wireless communication that combines power and data transmission into a single carrier. This modification will significantly influence the trajectory of short-range communication and its applications. The foundation of most low-power, short-range communication applications relies on an ultra-low-power microcontroller. Therefore, this study will encompass an analysis of ultra-low-power microcontrollers and an investigation into the potential limitations they might encounter in the future. In addition to offering a thorough examination of current Wireless short-range communication, this article will also attempt to forecast future patterns and identify possible obstacles that future research may address. Full article
(This article belongs to the Special Issue Ultra-Low-Power ICs for the Internet of Things Vol. 2)
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20 pages, 2282 KiB  
Article
Multibeam Wideband Transmit Beamforming Using 2D Sparse FIR Trapezoidal Filters
by Nadeeshan Dissanayake, Chamira U. S. Edussooriya, Chamith Wijenayake and Arjuna Madanayake
J. Low Power Electron. Appl. 2024, 14(2), 26; https://doi.org/10.3390/jlpea14020026 - 28 Apr 2024
Viewed by 658
Abstract
A low-complexity multibeam wideband transmit beamformer using a 2D sparse FIR filter design capable of multiple beams is proposed as a digital building block for fully digital beamformers. The 2D sparse FIR filter has multiple trapezoid-shaped passbands pertaining to wideband beams aimed at [...] Read more.
A low-complexity multibeam wideband transmit beamformer using a 2D sparse FIR filter design capable of multiple beams is proposed as a digital building block for fully digital beamformers. The 2D sparse FIR filter has multiple trapezoid-shaped passbands pertaining to wideband beams aimed at particular directions. The proposed multibeam digital beamformer drives a uniform linear array of wideband antenna elements to achieve the wideband multibeam transmit-mode signals desired by the communication system. The 2D sparse FIR filter is designed to be optimal in the minimax sense using convex optimization techniques. Full-wave electromagnetic simulations using real antenna models confirm that the proposed wideband transmit beamformer can achieve multibeam transmission in the 1.3–2.8 GHz frequency range, with more than 70% fractional bandwidth. Furthermore, the adoption of the wideband transmit multibeam beamformer leads to a significant reduction in digital arithmetic (computational) complexity compared with previously reported wideband transmit beamformers of similar transfer function type, without deteriorating beam directionality and causing increases in the side-lobe level. The proposed sparse 2D FIR multibeam beamformer architecture is well-suited for both sub-6 GHz (legacy) band transmit beamforming, frequency range three (FR3) beamforming up to 28 GHz, and mmWave operation for emerging 5G/6G applications. Full article
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12 pages, 1482 KiB  
Article
Gate-Level Hardware Priority Resolvers for Embedded Systems
by Padmanabhan Balasubramanian and Douglas L. Maskell
J. Low Power Electron. Appl. 2024, 14(2), 25; https://doi.org/10.3390/jlpea14020025 - 17 Apr 2024
Viewed by 602
Abstract
An N-bit priority resolver having N inputs and N outputs functions as polling hardware in an embedded system, enabling access to a resource when multiple devices initiate access requests at its inputs which may be located on-chip or off-chip. Subsystems such as data [...] Read more.
An N-bit priority resolver having N inputs and N outputs functions as polling hardware in an embedded system, enabling access to a resource when multiple devices initiate access requests at its inputs which may be located on-chip or off-chip. Subsystems such as data buses, comparators, fixed- and floating-point arithmetic units, interconnection network routers, etc., utilize the priority resolver function. In the literature, there are many transistor-level designs for the priority resolver based on dynamic CMOS logic, some of which are modular and others are not. This article presents a novel gate-level modular design of priority resolvers that can accommodate any number of inputs and outputs. Based on our modular design architecture, small-size priority resolvers can be conveniently combined to form medium- or large-size priority resolvers along with extra logic. The proposed modular design approach helps to reduce the coding complexity compared to the conventional direct design approach and facilitates scalability. We discuss the gate-level implementation of 4-, 8-, 16-, 32-, 64-, and 128-bit priority resolvers based on the direct and modular approaches and provide a performance comparison between these based on the design metrics. According to the modular approach, different sizes of priority resolver modules were used to implement larger-size priority resolvers. For example, a 4-bit priority resolver module was used to implement 8-, 16-, 32-, 64-, and 128-bit priority resolvers in a modular fashion. We used a 28 nm CMOS standard digital cell library and Synopsys EDA tools to synthesize the priority resolvers. The estimated design metrics show that the modular approach tends to facilitate increasing reductions in delay and power-delay product (PDP) compared to the direct approach, especially as the size of the priority resolver increases. For example, a 32-bit modular priority resolver utilizing 16-bit priority resolver modules had a 39.4% reduced delay and a 23.1% reduced PDP compared to a directly implemented 32-bit priority resolver, and a 128-bit modular priority resolver utilizing 16-bit priority resolver modules had a 71.8% reduced delay and a 61.4% reduced PDP compared to a directly implemented 128-bit priority resolver. Full article
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8 pages, 2415 KiB  
Brief Report
Efficient Addition Circuits Using Three-Gate Reconfigurable Field Effect Transistors
by Fanny Spagnolo, Pasquale Corsonello, Fabio Frustaci and Stefania Perri
J. Low Power Electron. Appl. 2024, 14(2), 24; https://doi.org/10.3390/jlpea14020024 - 14 Apr 2024
Viewed by 655
Abstract
Reconfigurable FETs (RFETs) are widely recognized as a promising way to overcome conventional CMOS architectures. This paper presents novel addition circuit intentionally designed to exploit the ability of RFETs to operate efficiently on demand as n- or p-type FETs. First, a novel Full [...] Read more.
Reconfigurable FETs (RFETs) are widely recognized as a promising way to overcome conventional CMOS architectures. This paper presents novel addition circuit intentionally designed to exploit the ability of RFETs to operate efficiently on demand as n- or p-type FETs. First, a novel Full Adder (FA) is proposed and characterized. A comparison with other designs shows that the proposed FA achieves a worst-case delay and a dynamic power consumption of up to 43.5% and 79% lower. As a drawback, in terms of the estimated area, it is up to 32% larger than the competitors. Then, the new FA is used to implement Ripple-Carry Adders (RCAs). A 32-bit adder designed as proposed herein reaches an energy–delay product (EDP) ~25.7× and ~141× lower than its CMOS and the RFET-based counterparts. Full article
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15 pages, 1776 KiB  
Article
Vehicle Detection in Adverse Weather: A Multi-Head Attention Approach with Multimodal Fusion
by Nujhat Tabassum and Mohamed El-Sharkawy
J. Low Power Electron. Appl. 2024, 14(2), 23; https://doi.org/10.3390/jlpea14020023 - 13 Apr 2024
Viewed by 644
Abstract
In the realm of autonomous vehicle technology, the multimodal vehicle detection network (MVDNet) represents a significant leap forward, particularly in the challenging context of weather conditions. This paper focuses on the enhancement of MVDNet through the integration of a multi-head attention layer, aimed [...] Read more.
In the realm of autonomous vehicle technology, the multimodal vehicle detection network (MVDNet) represents a significant leap forward, particularly in the challenging context of weather conditions. This paper focuses on the enhancement of MVDNet through the integration of a multi-head attention layer, aimed at refining its performance. The integrated multi-head attention layer in the MVDNet model is a pivotal modification, advancing the network’s ability to process and fuse multimodal sensor information more efficiently. The paper validates the improved performance of MVDNet with multi-head attention through comprehensive testing, which includes a training dataset derived from the Oxford Radar RobotCar. The results clearly demonstrate that the multi-head MVDNet outperforms the other related conventional models, particularly in the average precision (AP) of estimation, under challenging environmental conditions. The proposed multi-head MVDNet not only contributes significantly to the field of autonomous vehicle detection but also underscores the potential of sophisticated sensor fusion techniques in overcoming environmental limitations. Full article
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18 pages, 12068 KiB  
Article
A Low Power Injection-Locked CDR Using 28 nm FDSOI Technology for Burst-Mode Applications
by Yuqing Mao, Yoann Charlon, Yves Leduc and Gilles Jacquemod
J. Low Power Electron. Appl. 2024, 14(2), 22; https://doi.org/10.3390/jlpea14020022 - 7 Apr 2024
Viewed by 760
Abstract
In this paper, a low-power Injection-Locked Clock and Data Recovery (ILCDR) using a 28 nm Ultra-Thin Body and Box-Fully Depleted Silicon On Insulator (UTBB-FDSOI) technology is presented. The back-gate auto-biasing of UTBB-FDSOI transistors enables the creation of a Quadrature Ring Oscillator (QRO) reducing [...] Read more.
In this paper, a low-power Injection-Locked Clock and Data Recovery (ILCDR) using a 28 nm Ultra-Thin Body and Box-Fully Depleted Silicon On Insulator (UTBB-FDSOI) technology is presented. The back-gate auto-biasing of UTBB-FDSOI transistors enables the creation of a Quadrature Ring Oscillator (QRO) reducing both size and power consumption compared to an LC tank oscillator. By injecting a digital signal into this circuit, we realize an Injection-Locked Oscillator (ILO) with low jitter. Thanks to the good performance of this oscillator, we propose a low-power ILCDR with fast locking time and low jitter for burst-mode applications. The main novelty consists of the implementation of a complementary QRO based on back-gate control using FDSOI technology to realize a simple and efficient ILCDR circuit. With a Pseudo-Random Binary Sequence (PRBS7) at 868 Mbps, the recovered clock jitter is 26.7 ps (2.3% UIp-p) and the recovered data jitter is 11.9 ps (1% UIp-p). With a 0.6 V power supply, the power consumption is 318μW. All the results presented here are based on post-layout simulations, as no prototypes have been produced. Similarly, we can estimate the surface area of the chip (without the pad ring) at around 6600 μm2. Full article
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19 pages, 677 KiB  
Article
A 0.3 V OTA with Enhanced CMRR and High Robustness to PVT Variations
by Riccardo Della Sala, Francesco Centurelli, Giuseppe Scotti and Alessandro Trifiletti
J. Low Power Electron. Appl. 2024, 14(2), 21; https://doi.org/10.3390/jlpea14020021 - 2 Apr 2024
Viewed by 924
Abstract
In this paper, we present a 0.3 V body-driven operational transconductance amplifier (OTA) that exploits a biasing approach based on the use of a replica loop with gain. An auxiliary amplifier is exploited both in the current mirror load of the first stage [...] Read more.
In this paper, we present a 0.3 V body-driven operational transconductance amplifier (OTA) that exploits a biasing approach based on the use of a replica loop with gain. An auxiliary amplifier is exploited both in the current mirror load of the first stage of the OTA and in the replica loop in order to achieve super-diode behavior, resulting in low mirror gain error, which enhances CMRR, and robust biasing. Common-mode feedforward, provided by the replica loop, further enhances CMRR. Simulations in a 180 nm CMOS technology show 65 dB gain with 2 kHz unity-gain frequency on a 200 pF load when consuming 9 nW. Very high linearity with a 0.24% THD at 90% full-scale and robustness to PVT variations are also achieved. Full article
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14 pages, 4880 KiB  
Article
Dual-Band Large-Frequency Ratio Power Divider Using Mode Composite Transmission Line for 5G Communication Systems
by Kaijun Song, Lele Fang and Yedi Zhou
J. Low Power Electron. Appl. 2024, 14(2), 20; https://doi.org/10.3390/jlpea14020020 - 31 Mar 2024
Viewed by 890
Abstract
In this paper, a novel kind of mode composite transmission line (MC-TL) is proposed, and a dual-band power divider with a large frequency ratio using this novel MC-TL for 5G communication systems was developed. The proposed MC-TL was developed using spoof surface plasmon [...] Read more.
In this paper, a novel kind of mode composite transmission line (MC-TL) is proposed, and a dual-band power divider with a large frequency ratio using this novel MC-TL for 5G communication systems was developed. The proposed MC-TL was developed using spoof surface plasmon polaritons (SSPPs) and a corrugated substrate-integrated waveguide (CSIW) transmission line, which supports both a surface plasmon mode and TE10 mode, independently. The surface plasmon mode operates in the grooves of the surface metal layer, while the TE10 mode works in the substrate between two metal layers. These two parts can transmit different modes at independent frequencies. This structure can be used in dual-band transmission lines with a high frequency ratio. The characteristics and design of the MC-TL (SSPPs and CSIW) are analyzed and illustrated. The MC-TL was fabricated and measured to demonstrate its performance. Moreover, based on the proposed MC-TL, a dual-band power divider with a large frequency ratio (operating at 3 GHz and 28 GHz simultaneously) was also designed and fabricated. It can cover the frequency of a fifth-generation communication system perfectly. The measured outcomes align closely with the simulated results, demonstrating robust agreement and showcasing excellent transmission capabilities. Full article
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20 pages, 3068 KiB  
Article
A Citizen Science Tool Based on an Energy Autonomous Embedded System with Environmental Sensors and Hyperspectral Imaging
by Charalampos S. Kouzinopoulos, Eleftheria Maria Pechlivani, Nikolaos Giakoumoglou, Alexios Papaioannou, Sotirios Pemas, Panagiotis Christakakis, Dimosthenis Ioannidis and Dimitrios Tzovaras
J. Low Power Electron. Appl. 2024, 14(2), 19; https://doi.org/10.3390/jlpea14020019 - 27 Mar 2024
Viewed by 1292
Abstract
Citizen science reinforces the development of emergent tools for the surveillance, monitoring, and early detection of biological invasions, enhancing biosecurity resilience. The contribution of farmers and farm citizens is vital, as volunteers can strengthen the effectiveness and efficiency of environmental observations, improve surveillance [...] Read more.
Citizen science reinforces the development of emergent tools for the surveillance, monitoring, and early detection of biological invasions, enhancing biosecurity resilience. The contribution of farmers and farm citizens is vital, as volunteers can strengthen the effectiveness and efficiency of environmental observations, improve surveillance efforts, and aid in delimiting areas affected by plant-spread diseases and pests. This study presents a robust, user-friendly, and cost-effective smart module for citizen science that incorporates a cutting-edge developed hyperspectral imaging (HI) module, integrated in a single, energy-independent device and paired with a smartphone. The proposed module can empower farmers, farming communities, and citizens to easily capture and transmit data on crop conditions, plant disease symptoms (biotic and abiotic), and pest attacks. The developed HI-based module is interconnected with a smart embedded system (SES), which allows for the capture of hyperspectral images. Simultaneously, it enables multimodal analysis using the integrated environmental sensors on the module. These data are processed at the edge using lightweight Deep Learning algorithms for the detection and identification of Tuta absoluta (Meyrick), the most important invaded alien and devastating pest of tomato. The innovative Artificial Intelligence (AI)-based module offers open interfaces to passive surveillance platforms, Decision Support Systems (DSSs), and early warning surveillance systems, establishing a seamless environment where innovation and utility converge to enhance crop health and productivity and biodiversity protection. Full article
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9 pages, 2773 KiB  
Communication
A Compact 0.73~3.1 GHz CMOS VCO Based on Active-Inductor and Active-Resistor Topology
by Chatrpol Pakasiri, Ke-Chung Hsu and Sen Wang
J. Low Power Electron. Appl. 2024, 14(2), 18; https://doi.org/10.3390/jlpea14020018 - 25 Mar 2024
Viewed by 925
Abstract
In this paper, a wideband VCO that covers popular Long-Term Evolution (LTE) 0.7 GHz and LTE 2.6 GHz frequencies is designed and developed in a standard 0.18 μm CMOS process. The VCO utilizes active inductors to achieve coarse-tuning of the inductance and a [...] Read more.
In this paper, a wideband VCO that covers popular Long-Term Evolution (LTE) 0.7 GHz and LTE 2.6 GHz frequencies is designed and developed in a standard 0.18 μm CMOS process. The VCO utilizes active inductors to achieve coarse-tuning of the inductance and a compact chip area. Moreover, an active feedback resistor is introduced into the active inductor for fine-tuning of the inductance. The feedback resistor also affects the equivalent resistance of the active inductor; therefore, wide inductance tuning and low power consumption can be obtained by optimizing the resistor. The core area of the fabricated CMOS chip is merely 0.046 mm2, excluding all testing pads. With a 6.7~10.1 mW DC consumption, the measured oscillation frequencies range from 0.73 GHz to 3.1 GHz, which demonstrates a 123.8% tuning range. At the frequencies of interest, the measured phase noises are from −80.7 to −84.5 dBc/Hz at a 1 MHz offset frequency. Full article
(This article belongs to the Special Issue Analog/Mixed-Signal Integrated Circuit Design)
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