Ultra-Low-Power ICs for the Internet of Things Vol. 2

A special issue of Journal of Low Power Electronics and Applications (ISSN 2079-9268).

Deadline for manuscript submissions: 31 May 2024 | Viewed by 8894

Special Issue Editor


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Guest Editor
Department of Electrical, Electronic, Telecommunications Engineering and Naval Architecture (DITEN), University of Genoa, Via Opera Pia 11a, I-16145 Genova, Italy
Interests: energy-efficient integrated circuit design; mostly digital/synthesizable interfaces; ultra-low-power ICs for the Internet of Things (IoT); ultra-low-voltage and voltage scalable ICs
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Special Issue Information

Dear Colleagues,

Ultra-low-voltage/power analog and digital ICs, powered by energy harvesters, face the challenges of small area occupation, low design effort, and technology/design portability, which are needed in this Internet-of-Things (IoT) era, which, in itself, has experienced exponential growth in relation to interconnected sensor nodes.

In this framework, the aim of this Special Issue is to attract original research articles related to the design and application of ultra-low-voltage/power, digital-based, and fully synthesizable ICs.

The topics of this Special Issue include but are not limited to

  • Ultra-low-power interfaces for the Internet of Things: energy-efficient and power/voltage scalable, analog, and mixed-signal IC;
  • Inverter- and digital-based design methodologies of ultra-low power ICs;
  • IC solution for ultra-low-voltage, energy and standby power consumption systems;
  • Automated design methodology to decrease the time-to-market;
  • Energy harvesting and power management circuit for IoT devices;
  • Ultra-low-power/voltage ICs for instrumentation and communication applications.

Dr. Orazio Aiello
Guest Editor

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Journal of Low Power Electronics and Applications is an international peer-reviewed open access quarterly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 1800 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • ultra-low-power/voltage ICs for IoT applications
  • advancements in energy-aware design techniques
  • ultra-low-power front-end electronics
  • energy-efficient ICs
  • digital-based design methodologies
  • ultra-low-power sensors and energy-neutral devices
  • energy harvesting and power management circuit

Related Special Issue

Published Papers (5 papers)

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Research

17 pages, 2747 KiB  
Article
A Sub-1-V Nanopower MOS-Only Voltage Reference
by Siqi Wang, Zhenghao Lu, Kunpeng Xu, Hongguang Dai, Zhanxia Wu and Xiaopeng Yu
J. Low Power Electron. Appl. 2024, 14(1), 13; https://doi.org/10.3390/jlpea14010013 - 29 Feb 2024
Viewed by 1069
Abstract
A novel low-power MOS-only voltage reference is presented. The Enz–Krummenacher–Vittoz (EKV) model is adopted to provide a new perspective on the operating principle. The normalized charge density, introduced as a new variable, serves as an indicator when trimming the output temperature coefficient. The [...] Read more.
A novel low-power MOS-only voltage reference is presented. The Enz–Krummenacher–Vittoz (EKV) model is adopted to provide a new perspective on the operating principle. The normalized charge density, introduced as a new variable, serves as an indicator when trimming the output temperature coefficient. The proposed voltage reference consists of a specific current generator and a 5-bit trimmable load. Thanks to the good match between the current source stage and the output stage, the nonlinear temperature dependence of carrier mobility is automatically canceled out. The circuit is designed using 55 nm COMS technology. The operating temperature ranges from −40 °C to 120 °C. The average temperature coefficient of the output voltage can be reduced to 21.7 ppm/°C by trimming. The power consumption is only 23.2 nW with a supply voltage of 0.8 V. The line sensitivity and the power supply rejection ratio at 100 Hz are 0.011 %/V and −89 dB, respectively. Full article
(This article belongs to the Special Issue Ultra-Low-Power ICs for the Internet of Things Vol. 2)
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9 pages, 3852 KiB  
Communication
Design of a Low-Power Delay-Locked Loop-Based 8× Frequency Multiplier in 22 nm FDSOI
by Naveed and Jeff Dix
J. Low Power Electron. Appl. 2023, 13(4), 64; https://doi.org/10.3390/jlpea13040064 - 12 Dec 2023
Viewed by 1557
Abstract
A low-power delay-locked loop (DLL)-based frequency multiplier is presented. The multiplier is designed in 22 nm FDSOI and achieves 8× multiplication. The proposed DLL uses a new simple duty cycle correction circuit and is XOR logic-based for frequency multiplication. Current starved delay cells [...] Read more.
A low-power delay-locked loop (DLL)-based frequency multiplier is presented. The multiplier is designed in 22 nm FDSOI and achieves 8× multiplication. The proposed DLL uses a new simple duty cycle correction circuit and is XOR logic-based for frequency multiplication. Current starved delay cells are used to make the circuit power efficient. The circuit uses three 2× stages instead of an edge combiner to achieve 8× multiplication, thus requiring far less power and chip area as compared to conventional phase-locked loop (PLL) circuits. The proposed 8× multiplier occupies an active area of 0.09 mm2. The measurement result shows ultra-low power consumption of 130 µW at 0.8 V supply. The post-layout simulation shows a timing jitter of 24 ps (pk-pk) at 2.44 GHz. Full article
(This article belongs to the Special Issue Ultra-Low-Power ICs for the Internet of Things Vol. 2)
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21 pages, 4797 KiB  
Article
Design and Optimization of an Ultra-Low-Power Cross-Coupled LC VCO with a DFF Frequency Divider for 2.4 GHz RF Receivers Using 65 nm CMOS Technology
by Muhammad Faisal Siddiqui, Mukesh Kumar Maheshwari, Muhammad Raza and Aurangzeb Rashid Masud
J. Low Power Electron. Appl. 2023, 13(4), 54; https://doi.org/10.3390/jlpea13040054 - 07 Oct 2023
Cited by 1 | Viewed by 2148
Abstract
This article presents the design and optimization of a tunable quadrature differential LC CMOS voltage-controlled oscillator (VCO) with a D flip-flop (DFF) frequency divider. The VCO is designed for the low-power and low-phase-noise applications of 2.4 GHz IoT/BLE receivers and wireless sensor devices. [...] Read more.
This article presents the design and optimization of a tunable quadrature differential LC CMOS voltage-controlled oscillator (VCO) with a D flip-flop (DFF) frequency divider. The VCO is designed for the low-power and low-phase-noise applications of 2.4 GHz IoT/BLE receivers and wireless sensor devices. The proposed design comprises the proper stacking of an LC VCO and a DFF frequency divider and is simulated using a TSMC 65 nm CMOS technology, and it has a tuning range of 4.4 to 5.7 GHz. The voltage headroom is preserved using a high-impedance on-chip passive inductor at the tail for filtering and enabling true differential operation. The VCO and frequency divider consume as low as 2.02 mW altogether, with the VCO section consuming only 0.47 mW. The active area of the chip including the pads is only 0.47 mm2. The designed VCO achieved a much better phase noise of −118.36 dBc/Hz at a 1 MHz offset frequency with 1.2 V supply voltages. The design produced a much better FoM of −196.44 dBc/Hz compared to other related research. Full article
(This article belongs to the Special Issue Ultra-Low-Power ICs for the Internet of Things Vol. 2)
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15 pages, 10415 KiB  
Article
A Power-Gated 8-Transistor Physically Unclonable Function Accelerates Evaluation Speeds
by Yujin Zheng, Alex Yakovlev and Alex Bystrov
J. Low Power Electron. Appl. 2023, 13(4), 53; https://doi.org/10.3390/jlpea13040053 - 29 Sep 2023
Cited by 1 | Viewed by 1365
Abstract
The proposed 8-Transistor (8T) Physically Unclonable Function (PUF), in conjunction with the power gating technique, can significantly accelerate a single evaluation cycle more than 100,000 times faster than a 6-Transistor (6T) Static Random-Access Memory (SRAM) PUF. The 8T PUF is built to swiftly [...] Read more.
The proposed 8-Transistor (8T) Physically Unclonable Function (PUF), in conjunction with the power gating technique, can significantly accelerate a single evaluation cycle more than 100,000 times faster than a 6-Transistor (6T) Static Random-Access Memory (SRAM) PUF. The 8T PUF is built to swiftly eliminate data remanence and maximise physical mismatch. Moreover, a two-phase power gating module is devised to provide controllable power on/off cycles for the chosen PUF clusters in order to facilitate fast statistical measurements and curb the in-rush current. The architecture and hardware implementation of the power-gated PUF are developed to accommodate fast multiple evaluations of PUF Responses. The fast speed enables a new data processing method, which coordinates Dark-bit masking and Multiple Temporal Majority Voting (TMV) in different Process, Voltage and Temperature (PVT) corners or during field usage, hence greatly reducing the Bit Error Rate (BER) and the hardware penalty for error correction. The designs are based on the UMC 65 nm technology and aim to tape out an Application-Specific Integrated Circuit (ASIC) chip. Post-layout Monte Carlo (MC) simulations are performed with Cadence, and the extracted PUF Responses are processed with Matlab to evaluate the 8T PUF performance and statistical metrics for subsequent inclusion in PUF Responses, which comprise the novelty of this approach. Full article
(This article belongs to the Special Issue Ultra-Low-Power ICs for the Internet of Things Vol. 2)
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12 pages, 5396 KiB  
Article
Ultra-Low Power Programmable Bandwidth Capacitively-Coupled Chopper Instrumentation Amplifier Using 0.2 V Supply for Biomedical Applications
by Xuan Thanh Pham, Xuan Thuc Kieu and Manh Kha Hoang
J. Low Power Electron. Appl. 2023, 13(2), 37; https://doi.org/10.3390/jlpea13020037 - 24 May 2023
Viewed by 1589
Abstract
This paper presents a capacitively coupled chopper instrumentation amplifier (CCIA) with ultra-low power consumption and programmable bandwidth for biomedical applications. To achieve a flexible bandwidth from 0.2 to 10 kHz without additional power consumption, a programmable Miller compensation technique was proposed and used [...] Read more.
This paper presents a capacitively coupled chopper instrumentation amplifier (CCIA) with ultra-low power consumption and programmable bandwidth for biomedical applications. To achieve a flexible bandwidth from 0.2 to 10 kHz without additional power consumption, a programmable Miller compensation technique was proposed and used in the CCIA. By using a Squeezed inverter amplifier (SQI) that employs a 0.2-V supply, the proposed CCIA addresses the primary noise source in the first stage, resulting in high noise power efficiency. The proposed CCIA is designed using a 0.18 µm CMOS technology process and has a chip area of 0.083 mm2. With a power consumption of 0.47 µW at 0.2 and 0.8 V supply, the proposed amplifier architecture achieves a thermal noise of 28 nV/√Hz, an input-related noise (IRN) of 0.9 µVrms, a closed-loop gain (AV) of 40 dB, a power supply rejection ratio (PSRR) of 87.6 dB, and a common-mode rejection ratio (CMRR) of 117.7 dB according to post-simulation data. The proposed CCIA achieves a noise efficiency factor (NEF) of 1.47 and a power efficiency factor (PEF) of 0.56, which allows comparison with the latest research results. Full article
(This article belongs to the Special Issue Ultra-Low-Power ICs for the Internet of Things Vol. 2)
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