Journal of Low Power Electronics and Applications

10 pages, 4576 KiB

Open AccessCommunication

FFC-NMR Power Supply with Hybrid Control of the Semiconductor Devices

by António Roque, Duarte M. Sousa, Pedro J. Sebastião, Vítor Silva and Elmano Margato

J. Low Power Electron. Appl. 2023, 13(3), 52; https://doi.org/10.3390/jlpea13030052 - 19 Sep 2023

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The performance of FFC-NMR power supplies is evaluated not only considering the technique requirements but also comparing efficiencies and power consumption. Since the characteristics of FFC-NMR power supplies depend on the power circuit topology and on the control solutions, the control design is [...] Read more.

The performance of FFC-NMR power supplies is evaluated not only considering the technique requirements but also comparing efficiencies and power consumption. Since the characteristics of FFC-NMR power supplies depend on the power circuit topology and on the control solutions, the control design is a core aspect for the development of new FFC systems. A new hybrid solution is described that allows controlling the power of semiconductors by switches (ON/OFF mode) or as a linear device. The approach avoids over-design of the power supply and makes it possible to implement new low power solutions constituting a novel design by joining a continuous match between the ON/OFF mode and the linear control of the power semiconductor devices. Full article

(This article belongs to the Topic Application of Innovative Power Electronic Technologies, 2nd Volume)

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14 pages, 1514 KiB

Open AccessArticle

An Investigation of the Operating Principles and Power Consumption of Digital-Based Analog Amplifiers

by Anna Richelli, Paolo Faustini, Andrea Rosa and Luigi Colalongo

J. Low Power Electron. Appl. 2023, 13(3), 51; https://doi.org/10.3390/jlpea13030051 - 08 Sep 2023

Viewed by 1359

Abstract

Digital-based differential amplifiers (DDA) are particularly suitable to low voltage digital integrated circuit technologies. This paper presents an exhaustive analysis of digital-based analog amplifiers to take advantage of today’s high-performance digital technologies, and of computer aided design (CAD), which is commonly employed to [...] Read more.

Digital-based differential amplifiers (DDA) are particularly suitable to low voltage digital integrated circuit technologies. This paper presents an exhaustive analysis of digital-based analog amplifiers to take advantage of today’s high-performance digital technologies, and of computer aided design (CAD), which is commonly employed to design integrated circuits. The operating principle and the main mathematical relations of digital-based differential amplifiers are discussed along with an exhaustive explanation of its operating regions and of the corresponding power consumption. These aspects, which are not discussed in the literature, are very important for the circuit designers. Finally, a detailed description of the design procedure of the UMC 180nm standard CMOS technology is provided. Full article

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15 pages, 729 KiB

Open AccessArticle

Address Obfuscation to Protect against Hardware Trojans in Network-on-Chips

by Thomas Mountford, Abhijitt Dhavlle, Andrew Tevebaugh, Naseef Mansoor, Sai Manoj Pudukotai Dinakarrao and Amlan Ganguly

J. Low Power Electron. Appl. 2023, 13(3), 50; https://doi.org/10.3390/jlpea13030050 - 06 Sep 2023

Viewed by 1450

Abstract

In modern computing, which relies on the interconnection of networks used in many/multi-core systems, any system can be critically subverted if the interconnection is compromised. This can be done in a multitude of ways, but the threat of a hardware Trojan (HT) being [...] Read more.

In modern computing, which relies on the interconnection of networks used in many/multi-core systems, any system can be critically subverted if the interconnection is compromised. This can be done in a multitude of ways, but the threat of a hardware Trojan (HT) being injected into a system is particularly prevalent due to the increase in third-party manufacturers for system-on-chip (SoC) designs. With a local injection of an HT in an SoC, an adversary can gain access to information about applications running on the system by revealing specific communications of the SoC, and the network-on-chip (NoC) as a whole. This heavily compromises the system and gives information to the attacker, which can lead to more tailored, compromising attacks. In this paper, we demonstrate an HT that exploits communication patterns inside an SoC to reveal applications that are running on an NoC with multi/many-core processors. This is performed by leaking packet counts, after which the attacker then uses machine learning techniques to identify applications running on processors, and the SoC as a whole. We also propose a LUT-based obfuscation technique to limit the information available to the hardware Trojan. Our results indicate that this obfuscation method can reduce the accuracy of this attack from 99% to <8% in multi/many-core systems. Full article

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19 pages, 4691 KiB

Open AccessArticle

An Improved Lightweight Network Using Attentive Feature Aggregation for Object Detection in Autonomous Driving

by Priyank Kalgaonkar and Mohamed El-Sharkawy

J. Low Power Electron. Appl. 2023, 13(3), 49; https://doi.org/10.3390/jlpea13030049 - 10 Aug 2023

Viewed by 1437

Abstract

Object detection, a more advanced application of computer vision than image classification, utilizes deep neural networks to predict objects in an input image and determine their locations through bounding boxes. The field of artificial intelligence has increasingly focused on the demands of autonomous [...] Read more.

Object detection, a more advanced application of computer vision than image classification, utilizes deep neural networks to predict objects in an input image and determine their locations through bounding boxes. The field of artificial intelligence has increasingly focused on the demands of autonomous driving, which require both high accuracy and fast inference speeds. This research paper aims to address this demand by introducing an efficient lightweight network for object detection specifically designed for self-driving vehicles. The proposed network, named MobDet3, incorporates a modified MobileNetV3 as its backbone, leveraging its lightweight convolutional neural network algorithm to extract and aggregate image features. Furthermore, the network integrates altered techniques in computer vision and adjusts to the most recent iteration of the PyTorch framework. The MobDet3 network enhances not only object positioning ability but also the reusability of feature maps across different scales. Extensive evaluations were conducted to assess the effectiveness of the proposed network, utilizing an autonomous driving dataset, as well as large-scale everyday human and object datasets. These evaluations were performed on NXP BlueBox 2.0, an advanced edge development platform designed for autonomous vehicles. The results demonstrate that the proposed lightweight object detection network achieves a mean precision of up to 58.30% on the BDD100K dataset and a high inference speed of up to 88.92 frames per second on NXP BlueBox 2.0, making it well-suited for real-time object detection in autonomous driving applications. Full article

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18 pages, 3686 KiB

Open AccessArticle

TCI Tester: A Chip Tester for Inductive Coupling Wireless Through-Chip Interface

by Hideto Kayashima and Hideharu Amano

J. Low Power Electron. Appl. 2023, 13(3), 48; https://doi.org/10.3390/jlpea13030048 - 04 Aug 2023

Viewed by 1200

Abstract

The building block computation system is constructed by stacking various chips three-dimensionally. The stacked chips incorporate the same TCI IP (Through Chip Interface Intellectual Property) but cannot provide identical characteristics, requiring adjustments in power supply and bias voltage. However, providing characteristics measurement hardware [...] Read more.

The building block computation system is constructed by stacking various chips three-dimensionally. The stacked chips incorporate the same TCI IP (Through Chip Interface Intellectual Property) but cannot provide identical characteristics, requiring adjustments in power supply and bias voltage. However, providing characteristics measurement hardware for all chips is difficult due to the limitation of chip area or pin numbers. To address this problem, we developed TCI Tester, a small chip to measure electric characteristics by stacking on TCI of every chip. By stacking two TCI Tester chips, it appears that the up-directional data transfer has a stricter condition than down directional one on power supply voltage and operational frequency. Also, the transfer performance is poorer than designed. Similar measurement results are obtained by stacking TCI Tester on other chips with TCI IP. To investigate the reason, we analyzed the power grid resistance of various chips with the TCI IP. Results also showed that the chips with higher resistance have a narrow operational condition and poorer performance. The results suggest that the power grid design is important for keeping the performance through the TCI channel. Full article

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26 pages, 3383 KiB

Open AccessArticle

Programmable Energy-Efficient Analog Multilayer Perceptron Architecture Suitable for Future Expansion to Hardware Accelerators

by Jeff Dix, Jeremy Holleman and Benjamin J. Blalock

J. Low Power Electron. Appl. 2023, 13(3), 47; https://doi.org/10.3390/jlpea13030047 - 31 Jul 2023

Cited by 1 | Viewed by 1132

Abstract

A programmable, energy-efficient analog hardware implementation of a multilayer perceptron (MLP) is presented featuring a highly programmable system that offers the user the capability to create an MLP neural network hardware design within the available framework. In addition to programmability, this implementation provides [...] Read more.

A programmable, energy-efficient analog hardware implementation of a multilayer perceptron (MLP) is presented featuring a highly programmable system that offers the user the capability to create an MLP neural network hardware design within the available framework. In addition to programmability, this implementation provides energy-efficient operation via analog/mixed-signal design. The configurable system is made up of 12 neurons and is fabricated in a standard 130 nm CMOS process occupying approximately 1 mm² of on-chip area. The system architecture is analyzed in several different configurations with each achieving a power efficiency of greater than 1 tera-operations per watt. This work offers an energy-efficient and scalable alternative to digital configurable neural networks that can be built upon to create larger networks capable of standard machine learning applications, such as image and text classification. This research details a programmable hardware implementation of an MLP that achieves a peak power efficiency of 5.23 tera-operations per watt while consuming considerably less power than comparable digital and analog designs. This paper describes circuit elements that can readily be scaled up at the system level to create a larger neural network architecture capable of improved energy efficiency. Full article

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19 pages, 2143 KiB

Open AccessReview

Review of Orthogonal Frequency Division Multiplexing-Based Modulation Techniques for Light Fidelity

by Rahmayati Alindra, Purnomo Sidi Priambodo and Kalamullah Ramli

J. Low Power Electron. Appl. 2023, 13(3), 46; https://doi.org/10.3390/jlpea13030046 - 26 Jul 2023

Viewed by 1525

Abstract

Light Fidelity (LiFi) technology has gained attention and is growing rapidly today. Utilizing light as a propagation medium allows LiFi to promise a wider bandwidth than existing Wireless Fidelity (WiFi) technology and enables the implementation of cellular technology to improve bandwidth utilization. In [...] Read more.

Light Fidelity (LiFi) technology has gained attention and is growing rapidly today. Utilizing light as a propagation medium allows LiFi to promise a wider bandwidth than existing Wireless Fidelity (WiFi) technology and enables the implementation of cellular technology to improve bandwidth utilization. In addition, LiFi is very attractive because it can utilize lighting facilities consisting of light-emitting diodes (LEDs). A LiFi system that uses intensity modulation and direct detection requires the signal of orthogonal frequency division multiplexing (OFDM) to have a real and non-negative value; therefore, certain adjustments must be made. The proposed methods for generating unipolar signals vary from adding a direct current, clipping the signal, superposing several unipolar signals, and hybrid methods as in DC-biased optical (DCO)-OFDM, asymmetrically clipped optical (ACO)-OFDM, layered ACO (LACO)-OFDM, and asymmetrically clipped DC-biased optical (ADO)-OFDM, respectively. In this paper, we review and compare various modulation techniques to support the implementation of LiFi systems using commercial LEDs. The main objective is to obtain a modulation technique with good energy efficiency, efficient spectrum utilization, and low computational complexity so that it is easy for us to apply it in experiments on a laboratory scale. Full article

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20 pages, 1326 KiB

Open AccessArticle

BFT—Low-Latency Bit-Slice Design of Discrete Fourier Transform

by Cataldo Guaragnella, Agostino Giorgio and Maria Rizzi

J. Low Power Electron. Appl. 2023, 13(3), 45; https://doi.org/10.3390/jlpea13030045 - 18 Jul 2023

Cited by 1 | Viewed by 1700

Abstract

Structures for the evaluation of fast Fourier transforms are important components in several signal-processing applications and communication systems. Their capabilities play a key role in the performance enhancement of the whole system in which they are embedded. In this paper, a novel implementation [...] Read more.

Structures for the evaluation of fast Fourier transforms are important components in several signal-processing applications and communication systems. Their capabilities play a key role in the performance enhancement of the whole system in which they are embedded. In this paper, a novel implementation of the discrete Fourier transform is proposed, based on a bit-slice approach and on the exploitation of the input sequence finite word length. Input samples of the sequence to be transformed are split into binary sequences and each one is Fourier transformed using only complex sums. An FPGA-based solution characterized by low latency and low power consumption is designed. Simulations have been carried out, first in the Matlab environment, then emulated in Quartus IDE with Intel. The hardware implementation of the conceived system and the test for the functional accuracy verification have been performed, adopting the DE2-115 development board from Terasic, which is equipped with the Cyclone IV EP4CE115F29C7 FPGA by Intel. Full article

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15 pages, 2055 KiB

Open AccessArticle

Electromigration-Aware Memory Hierarchy Architecture

by Freddy Gabbay and Avi Mendelson

J. Low Power Electron. Appl. 2023, 13(3), 44; https://doi.org/10.3390/jlpea13030044 - 11 Jul 2023

Viewed by 1119

Abstract

New mission-critical applications, such as autonomous vehicles and life-support systems, set a high bar for the reliability of modern microprocessors that operate in highly challenging conditions. However, while cutting-edge integrated circuit (IC) technologies have intensified microprocessors by providing remarkable reductions in the silicon [...] Read more.

New mission-critical applications, such as autonomous vehicles and life-support systems, set a high bar for the reliability of modern microprocessors that operate in highly challenging conditions. However, while cutting-edge integrated circuit (IC) technologies have intensified microprocessors by providing remarkable reductions in the silicon area and power consumption, they also introduce new reliability challenges through the complex design rules they impose, creating a significant hurdle in the design process. In this paper, we focus on electromigration (EM), which is a crucial factor impacting IC reliability. EM refers to the degradation process of IC metal nets when used for both power supply and interconnecting signals. Typically, EM concerns have been addressed at the backend, circuit, and layout levels, where EM rules are enforced assuming extreme conditions to identify and resolve violations. This study presents new techniques that leverage architectural features to mitigate the effect of EM on the memory hierarchy of modern microprocessors. Architectural approaches can reduce the complexity of solving EM-related violations, and they can also complement and enhance common existing methods. In this study, we present a comprehensive simulation analysis that demonstrates how the proposed solution can significantly extend the lifetime of a microprocessor’s memory hierarchy with minimal overhead in terms of performance, power, and area while relaxing EM design efforts. Full article

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14 pages, 1832 KiB

Open AccessArticle

An Extended Range Divider Technique for Multi-Band PLL

by Rizwan Shaik Peerla, Ashudeb Dutta and Bibhu Datta Sahoo

J. Low Power Electron. Appl. 2023, 13(3), 43; https://doi.org/10.3390/jlpea13030043 - 05 Jul 2023

Cited by 1 | Viewed by 1621

Abstract

This paper presents a multiplexer-based extended range multi-modulus divider (ER-MMD) technique for multi-band phase locked loop (PLL). The architecture maintains a modular structure by using conventional

2 / 3

divider cells and a multiplexer without adding any extra logic circuitry. The area and [...] Read more.

This paper presents a multiplexer-based extended range multi-modulus divider (ER-MMD) technique for multi-band phase locked loop (PLL). The architecture maintains a modular structure by using conventional

2 / 3

divider cells and a multiplexer without adding any extra logic circuitry. The area and power overhead is minimal. The

2 / 3

divider cells are designed using true single phase clock (TSPC) logic for ER-MMD to operate in the sub-10 GHz range. A division range of 2 to 511 is achieved using this logic. The ER-MMD operates at a maximum frequency of 6 GHz with a worst-case current of 625

μ

A when powered with a 1 V supply. A dual voltage controlled oscillator (VCO),

L 5

/S band PLL for Indian Regional Navigation Satellite System (IRNSS) application is designed, which incorporates an ER-MMD based on the proposed approach as a proof of concept. This technique achieves the best power efficiency of 12 GHz/mW, among the state-of-the-art ER-MMD designs. Full article

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Graphical abstract

16 pages, 1057 KiB

Open AccessArticle

FTFNet: Multispectral Image Segmentation

by Justin Edwards and Mohamed El-Sharkawy

J. Low Power Electron. Appl. 2023, 13(3), 42; https://doi.org/10.3390/jlpea13030042 - 30 Jun 2023

Viewed by 1135

Abstract

Semantic segmentation is a machine learning task that is seeing increased utilization in multiple fields, from medical imagery to land demarcation and autonomous vehicles. A real-time autonomous system must be lightweight while maintaining reasonable accuracy. This research focuses on leveraging the fusion of [...] Read more.

Semantic segmentation is a machine learning task that is seeing increased utilization in multiple fields, from medical imagery to land demarcation and autonomous vehicles. A real-time autonomous system must be lightweight while maintaining reasonable accuracy. This research focuses on leveraging the fusion of long-wave infrared (LWIR) imagery with visual spectrum imagery to fill in the inherent performance gaps when using visual imagery alone. This approach culminated in the Fast Thermal Fusion Network (FTFNet), which shows marked improvement over the baseline architecture of the Multispectral Fusion Network (MFNet) while maintaining a low footprint. Full article

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J. Low Power Electron. Appl., Volume 13, Issue 3 (September 2023) – 11 articles

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