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Ultra-Low-Voltage and Ultra-Low-Power Integrated Circuits and Systems Evolution

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A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Circuit and Signal Processing".

Deadline for manuscript submissions: 15 November 2024 | Viewed by 17891

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Special Issue Editors

Dr. Andrea Ballo

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Dipartimento di Ingegneria Elettrica Elettronica e Informatica (DIEEI), University of Catania, I-95125 Catania, Italy
Interests: electronic engineering; switched capacitor AC/DC–DC converters; energy harvesting; low-power CMOS design; microelectronics
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Prof. Dr. Gaetano Palumbo

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Dipartimento di Ingegneria Elettrica Elettronica e Informatica, Università di Catania, I-95125 Catania, Italy
Interests: low-power electronics; CMOS integrated circuits; operational amplifiers; integrated circuit design; CMOS logic circuits; CMOS analogue integrated circuits
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Dr. Orazio Aiello

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Department of Electrical, Electronic, Telecommunications Engineering and Naval Architecture (DITEN), University of Genoa, Via Opera Pia 11a, I-16145 Genova, Italy
Interests: energy-efficient integrated circuit design; mostly-digital/synthesizable interfaces; ultra low power ICs for the Internet of Things (IoT); ultra-low-voltage and voltage scalable ICs
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

Dear Colleagues,

In the modern era of the interconnected world, ultra-low-voltage/power electronics is the true enabling factor for higher-impact applications. The use of analog and digital integrated circuits—often powered by energy harvesters—are becoming pervasive, while the challenges of small area occupation, low design effort, and technology/design portability have experienced exponential growth in relation to interconnected sensor nodes.

In this framework, the aim of this Special Issue is to attract reviews and original research outcomes related to the design and application of ultra-low-voltage/power, analog/digital, or mixed-signal-based integrated circuits.

The topics of interest for this Special Issue include but are not limited to:

Ultra-low-power interfaces for the Internet of Things: energy-efficient and power/voltage scalable, analog, mixed-signal IC;
Energy harvesting and power management circuit for IoT devices;
IC solutions for ultra-low-voltage/energy and standby power consumption systems;
Inverter- and digital-based design methodologies of ultra-low power ICs;
Ultra-low-power/voltage ICs for instrumentation and communication applications;
Automated design methodology to shorten the time-to-market.

Dr. Andrea Ballo
Prof. Dr. Gaetano Palumbo
Dr. Orazio Aiello
Guest Editors

Manuscript Submission Information

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Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

low-voltage analog and digital design techniques
low-power, low-voltage analog front-end (AFE) circuits
circuits for implantable and wearable devices
circuits for Internet of Things
switched capacitor converters
subthreshold analog and digital circuits
bulk-driven, inverter-based, multistage amplifiers
oscillators and filters
digitally assisted analog circuits
voltage and current references

Published Papers (10 papers)

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Research

18 pages, 10254 KiB

Open AccessArticle

Design and Performance Analysis of a [8/8/8] Charge Domain Mixed-Signal Multiply-Accumulator

by Akira Matsuzawa, Abdel Martinez Alonso and Masaya Miyahara

Electronics 2024, 13(1), 50; https://doi.org/10.3390/electronics13010050 - 21 Dec 2023

Viewed by 603

Abstract

This article describes the design and performance analysis of a charge domain mixed-signal multiply-accumulator (MAC) using RDAC, CDAC, and SAR-ADC with an 8-bit resolution for input, weight, and output. The arithmetic accuracy is mainly determined by the ADC, and the gain error has a significant impact. The mismatches and thermal noises of the RDAC and the CDAC are averaged by the number of multiply-accumulate units m connected to one ADC. As a result, if m is large enough, mismatches and thermal noises have a limited impact on the computation accuracy. Most of the computational energy is determined by the energy consumed by the SAR-ADC, and the computational energy per operation can be reduced by increasing m. This last metric is mainly determined by the charge and discharge energy of the CDAC for sufficiently large m values. Furthermore, since RDAC consumes energy unnecessarily, the turn-off timing of RDAC should be optimized. These MAC units have been designed and prototyped using 28 nm CMOS technology, integrating 12,288 arithmetic units while operating at 180 MHz, resulting in an arithmetic speed of 4.4 TOPS. The r-MVM accuracy is about 1% and a high energy efficiency of 240 TOPS/W as a MAC macro and 64.4 TOPS/W as a system has been achieved. Full article

(This article belongs to the Special Issue Ultra-Low-Voltage and Ultra-Low-Power Integrated Circuits and Systems Evolution)

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16 pages, 8096 KiB

Open AccessFeature PaperArticle

Modeling of Cross-Coupled AC–DC Charge Pump Operating in Subthreshold Region

by Ryoma Kotsubo and Toru Tanzawa

Electronics 2023, 12(24), 5031; https://doi.org/10.3390/electronics12245031 - 16 Dec 2023

Viewed by 876

Abstract

This paper proposes a circuit model of a cross-coupled CMOS AC–DC charge pump (XC–CP) operating in the subthreshold region. The aim is to improve the efficiency of designing XC–CPs with a variety of specifications, e.g., input and output voltages and AC input frequency. First, it is shown that the output resistance (Ro) of XC–CP is much higher than those of CPs with single diodes (SD–CP) and ultra-low-power diodes (ULPD–CP) as charge transfer switches (CTSs). Second, the reason behind the above feature of XC–CP, identified by a simple model, is that the gate-to-source voltages of CTS MOSFETs are independent of the output voltage of the CP. Third, the high but finite Ro of XC–CP is explainable with a more accurate model that includes the dependence of the saturation current of MOSFETs operating in the subthreshold region on the drain-to-source voltage, which is a function of the output voltage of CP. The model is in good agreement with measured and simulated results of XC–, SD–, and ULPD–CPs fabricated in a 250 nm CMOS. Full article

(This article belongs to the Special Issue Ultra-Low-Voltage and Ultra-Low-Power Integrated Circuits and Systems Evolution)

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18 pages, 6792 KiB

Open AccessArticle

A Double-Edge-Triggered Digital LDO with Built-In Adaptive VCO Clock for Fast Transient Response and Low Power Consumption

by Xin Xin, Dongdong Wei and Xingyuan Tong

Electronics 2023, 12(19), 4100; https://doi.org/10.3390/electronics12194100 - 29 Sep 2023

Viewed by 1002

Abstract

A double-edge-triggered digital low dropout regulator (DLDO) is proposed with a built-in adaptive voltage-controlled oscillator (VCO) clock (AVC) for a system-on-chip (SoC) application. To achieve a fast transient response, the main comparator generates the comparison result at the rising edge of the AVC, and this result is sampled by the coarse or fine bidirectional shifter register at the falling edge of the AVC. Furthermore, the clock frequency can be boosted from 8 MHz at the steady state to 50 MHz by the AVC when the output current suffers from a sudden change, and it can also be adjusted in real-time according to the output voltage, which avoids the oscillation phenomenon and decreases the power consumption during the recovery process. To further lower the power consumption, the self-clock comparator replaces the conventional static comparator in the transient detector. The post-simulation results show that the proposed DLDO consumes a quiescent current of 95.13 μA in the steady state, and drives a maximum load current of 25 mA at the supply power of 0.6 V with an active area of 0.053-mm² in a 180 nm CMOS process. When the load current jumps from 0.5 mA to 25 mA at the edge of 100 ps, the undershoot voltage and overshoot voltage are only 335 mV with the recovery time of 2.7 μs and 47.6 mV with the recovery time of 2.1 μs at the total on-chip capacitor of 50 pF, respectively, resulting in two competitive figures of merits (FoMs) than the previous works. Full article

(This article belongs to the Special Issue Ultra-Low-Voltage and Ultra-Low-Power Integrated Circuits and Systems Evolution)

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13 pages, 3705 KiB

Open AccessArticle

A Wirelessly-Powered Body-Coupled Data Transmission with Multi-Stage and Multi-Source Rectifier

by Byeongseol Kim and Joonsung Bae

Electronics 2023, 12(10), 2181; https://doi.org/10.3390/electronics12102181 - 10 May 2023

Cited by 1 | Viewed by 1284

Abstract

This paper demonstrates body-coupled (BC) data transmission and multi-source power delivery systems for neural interface applications. The implanted data transmitter and power receiver utilize an electrode interface rather than an antenna or coil interface for battery-free wireless transmission, enabling the external data receiver and power transmitter with patch electrodes to be placed away from the implant without requiring precise alignment, which is a critical issue in the conventional communication modalities of inductive coupling. Significantly, the implanted power receiver produces the supply voltage using ambient body-coupled 50/60 Hz signals from the Mains, on top of the 40.68 MHz wireless power source from the external power transmitter, to increase the recovered power level and the voltage conversion efficiency (VCE). The body-coupled wireless systems for implanted and external devices are implemented with integrated circuits (ICs) fabricated in a 180 nm CMOS process. When 650 mVpp AC voltage is applied to the implanted device, the power receiver recovers up to 780 μW with ambient (60 Hz signals) BC energy harvesting, achieving 93% VCE, while 600 μW is recovered without ambient (60 Hz signals) signal. The recovered power supplies the regulated voltage to the direct-digital signaling transceiver, which consumes 460 μW with an uplink data rate of 10 Mbps and a downlink data rate of 200 kbps, corresponding to an energy efficiency of 46 pJ/b. Full article

(This article belongs to the Special Issue Ultra-Low-Voltage and Ultra-Low-Power Integrated Circuits and Systems Evolution)

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14 pages, 8749 KiB

Open AccessFeature PaperArticle

A −31.7 dBm Sensitivity 0.011 mm² CMOS On-Chip Rectifier for Microwave Wireless Power Transfer

by Takuma Hashimoto, Hikaru Nekozuka, Yoshitaka Toeda, Masayuki Otani, Yasuhiko Fukuoka and Toru Tanzawa

Electronics 2023, 12(6), 1400; https://doi.org/10.3390/electronics12061400 - 15 Mar 2023

Cited by 1 | Viewed by 1374

Abstract

This paper pursued both the lower operating power limit and small area of on-chip rectifiers for microwave wireless power transfer (MWPT). RF–DC charge pump rectifiers can operate in the fast switching limit at a high frequency of 920 MHz even with a small stage capacitor C_in of 100 fF, which contributes to an area reduction in the on-chip rectifiers. Circuit design starts with C_in determined as small as possible, followed by the determination of switching transistors and the number of stages. Even at an extremely low input power of 1 μW, wiring resistance in RF inputs is critical. Routing of the RF inputs is designed in line with stage capacitors. Bonding pad structure also affects the lower input power limit. Ground-shielded pad design can reduce the lower limit. Various types of RF–DC charge pump rectifiers are fabricated in 65 nm CMOS. An ultra-low-power diode RF–DC charge pump rectifier with 32 stages had a lower input power limit of −31.7 dBm at an output voltage of 1.0 V. Its small silicon area of 0.011 mm² allows RF–DC rectifiers to be integrated in sensor ICs. More advanced technology providing MIM capacitors with higher capacitance density and placing switching MOSFETs under the MIM capacitors will further reduce the area of RF–DC charge pump rectifiers, allowing them to be integrated in sensor ICs. Full article

(This article belongs to the Special Issue Ultra-Low-Voltage and Ultra-Low-Power Integrated Circuits and Systems Evolution)

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20 pages, 4001 KiB

Open AccessArticle

Ultra-Low-Power Voice Activity Detection System Using Level-Crossing Sampling

by Maral Faghani, Hamidreza Rezaee-Dehsorkh, Nassim Ravanshad and Hamed Aminzadeh

Electronics 2023, 12(4), 795; https://doi.org/10.3390/electronics12040795 - 05 Feb 2023

Cited by 5 | Viewed by 2670

Abstract

This paper presents an ultra-low-power voice activity detection (VAD) system to discriminate speech from non-speech parts of audio signals. The proposed VAD system uses level-crossing sampling for voice activity detection. The useless samples in the non-speech parts of the signal are eliminated due to the activity-dependent nature of this sampling scheme. A 40 ms moving window with a 30 ms overlap is exploited as a feature extraction block, within which the output samples of the level-crossing analog-to-digital converter (LC-ADC) are counted as the feature. The only variable used to distinguish speech and non-speech segments in the audio input signal is the number of LC-ADC output samples within a time window. The proposed system achieves an average of 91.02% speech hit rate and 82.64% non-speech hit rate over 12 noise types at −5, 0, 5, and 10 dB signal-to-noise ratios (SNR) over the TIMIT database. The proposed system including LC-ADC, feature extraction, and classification circuits was designed in 0.18 µm CMOS technology. Post-layout simulation results show a power consumption of 394.6 nW with a silicon area of 0.044 mm², which makes it suitable as an always-on device in an automatic speech recognition system. Full article

(This article belongs to the Special Issue Ultra-Low-Voltage and Ultra-Low-Power Integrated Circuits and Systems Evolution)

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14 pages, 7949 KiB

Open AccessArticle

A Monostable Physically Unclonable Function Based on Improved RCCMs with 0–1.56% Native Bit Instability at 0.6–1.2 V and 0–75 °C

by Riccardo Della Sala, Davide Bellizia, Francesco Centurelli and Giuseppe Scotti

Electronics 2023, 12(3), 755; https://doi.org/10.3390/electronics12030755 - 02 Feb 2023

Cited by 7 | Viewed by 1210

Abstract

In this work, a Physically Unclonable Function (PUF) based on an improved regulated cascode current mirror (IRCCM) is presented. The proposed IRCCM improves the loop-gain of the gain-boosting branch over the conventional RCCM PUF, thereby increasing the output resistance and amplifying the mismatches due to random variations. The introduction of an explicit reference current in the biasing branch of the IRCCM results in lower native unstable bits, good robustness against environmental variations and very stable power consumption. The proposed PUF has been validated through measurement results on a test-chip implemented in a 130 nm CMOS process. The PUF performance was measured for supply voltages between 0.6 and 1.2V, and temperatures ranging from 0 °C to 75 °C. A comparison against similar designs from the literature has shown that the proposed PUF exhibits state of the art performance with improved reliability under supply voltage variations. Full article

(This article belongs to the Special Issue Ultra-Low-Voltage and Ultra-Low-Power Integrated Circuits and Systems Evolution)

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17 pages, 1872 KiB

Open AccessArticle

Design Automation of Low Dropout Voltage Regulators: A General Approach

by Karimeldeen Mohamed, Sherif Nafea and Hesham Omran

Electronics 2023, 12(1), 205; https://doi.org/10.3390/electronics12010205 - 31 Dec 2022

Cited by 1 | Viewed by 4176

Abstract

Analog design is an inherently intricate process comprising many trade-offs; as a result, it is an iterative time-consuming operation. A low dropout voltage regulator (LDO) is an example of such analog blocks that involve a myriad of trade-offs. In this paper, we present [...] Read more.

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methodology. Using a symbolic solver and the precomputed LUTs, a design database for an LDO that contains one million design points is generated in a few seconds. The database provides visualization of the design space and exploration of the trade-offs across different corners and load currents. A design example is provided to demonstrate the procedure using 40 nm technology and the results are verified using Cadence Spectre simulator. The approach is holistic in the sense that it uses an accurate symbolic solver to capture the small signal model complexities, incorporates LUTs for accurate calculation of the large signal solution and the small signal parameters, is fast because the simulator in the loop scenario is omitted, and almost all the specifications of LDOs are incorporated. Full article

(This article belongs to the Special Issue Ultra-Low-Voltage and Ultra-Low-Power Integrated Circuits and Systems Evolution)

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15 pages, 3975 KiB

Open AccessFeature PaperArticle

A Reconfigurable Hybrid RF Front-End Rectifier for Dynamic PCE Enhancement of Ambient RF Energy Harvesting Systems

by Wen Xun Lian, Jack Kee Yong, Gabriel Chong, Kishore Kumar Pakkirisami Churchill, Harikrishnan Ramiah, Yong Chen, Pui-In Mak and Rui P. Martins

Electronics 2023, 12(1), 175; https://doi.org/10.3390/electronics12010175 - 30 Dec 2022

Cited by 6 | Viewed by 1897

Abstract

This paper presents a reconfigurable hybrid Radio Frequency (RF) rectifier designed to efficiently convert AC RF power to DC voltages for an energy harvesting system. The proposed reconfigurable rectifier adopts the advantage of low conduction loss in the switch-connected rectifier and low reverse current loss in the diode-connection rectifier topology to enhance its power conversion efficiency (PCE). Capable of reconfiguring into different rectifier topologies, the proposed circuit can reconfigure into a switch-based cross-coupling differential drive (CCDD) at low input power and a diode-based hybrid rectifier at higher input power for a wide dynamic range operation. Designed and implemented on a CMOS 65 nm technology, the post-layout result records a peak PCE of 88.7% and a wide PCE dynamic range (PDR) of 16 dBm for PCE >40%. The proposed circuit also demonstrates a −21 dBm sensitivity output across a 1 MΩ output load. Full article

(This article belongs to the Special Issue Ultra-Low-Voltage and Ultra-Low-Power Integrated Circuits and Systems Evolution)

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17 pages, 1192 KiB

Open AccessArticle

A Differential-to-Single-Ended Converter Based on Enhanced Body-Driven Current Mirrors Targeting Ultra-Low-Voltage OTAs

by Riccardo Della Sala, Francesco Centurelli, Giuseppe Scotti, Pasquale Tommasino and Alessandro Trifiletti

Electronics 2022, 11(23), 3838; https://doi.org/10.3390/electronics11233838 - 22 Nov 2022

Cited by 7 | Viewed by 1317

Abstract

In this work, an ultra-low-voltage (ULV) technique to improve body-driven current mirrors is proposed. The proposed technique is employed to improve the performance of conventional differential-to-single-ended (D2S) converters which at these low voltages suffer from a low common-mode rejection ratio (CMRR). In addition, the technique aims to improve the performance of the conventional D2S also under a large signal swing and with respect to the process, voltage and temperature (PVT) variations, resulting in a very low distortion, high current mirror accuracy and robust performance. An enhanced body-driven current mirror was designed in a 130 nm CMOS technology from STMicroelectronics and an exhaustive campaign of simulations was conducted to confirm the effectiveness of the strategy and the robustness of the results. The enhanced D2S was also employed to design a ULV operational transconductance amplifier (OTA) and a comparison with an OTA based on a conventional D2S was provided. The simulation results have shown that the proposed enhanced D2S allows achieving the ULV OTAs with a CMRR and a PSRR which are 18 and 9 dB higher than the ones obtained with the conventional D2S topology, respectively. Moreover, the linearity performance is also improved as shown by the THD, whose value is decreased of about 5 dB. Full article

(This article belongs to the Special Issue Ultra-Low-Voltage and Ultra-Low-Power Integrated Circuits and Systems Evolution)

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