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Open AccessArticle

A Universal-Verification-Methodology-Based Testbench for the Coverage-Driven Functional Verification of an Instruction Cache Controller

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Electronics 2023, 12(18), 3821; https://doi.org/10.3390/electronics12183821 - 09 Sep 2023

Viewed by 340

Abstract

The Cache plays an important role in computer architecture by reducing the access time of the processor and improving its performance. The hardware design of the Cache is complex and it is challenging to verify its functions, so the traditional Verilog-based verification method [...] Read more.

The Cache plays an important role in computer architecture by reducing the access time of the processor and improving its performance. The hardware design of the Cache is complex and it is challenging to verify its functions, so the traditional Verilog-based verification method is no longer applicable. This paper proposes a comprehensive and efficient verification testbench based on the SystemVerilog language and universal verification methodology (UVM) for an instruction Cache (I-Cache) controller. Corresponding testcases are designed for each feature of the I-Cache controller and automatically executed using a python script on an electronic design automation (EDA) tool. After simulating a large number of testcases, the statistics reveal that the module’s code coverage is 99.13%. Additionally, both the function coverage and the assertion coverage of the module reach 100%. Our results demonstrate that these coverage metrics meet the requirements and ensure the thoroughness of function verification. Furthermore, the established verification testbench exhibits excellent scalability and reusability, making it easily applicable to higher-level verification scenarios. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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Open AccessArticle

A Master Multi-Slave System Based on Structural Modal Frequencies

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Electronics 2023, 12(15), 3260; https://doi.org/10.3390/electronics12153260 - 29 Jul 2023

Viewed by 528

Abstract

Structural Health Monitoring (SHM) is a process where, through sensors-based electronic systems and output data analysis, the structural integrity of a building or an infrastructure is observed and determined through periodically sampled measurements for material and geometric variations, ensuring safety and minimizing risk [...] Read more.

Structural Health Monitoring (SHM) is a process where, through sensors-based electronic systems and output data analysis, the structural integrity of a building or an infrastructure is observed and determined through periodically sampled measurements for material and geometric variations, ensuring safety and minimizing risk factors. Over the years, the approach to this problem evolved both in terms of system technology, with the use of more accurate sensors, and the parameters used to determine the building status, i.e., the extraction of the damage index. In these terms, structural modal harmonics-based analysis is acquiring more and more relevance. In this paper, we propose a fully custom master multi-slave system used for SHM purposes, capable of acquiring data from six different channels coming from two independent accelerometers suitably configured as to synchronously produce spectrograms and static trim of the monitored structure. A test of the system has been performed on a modular structure subject to random perturbation. Time and frequency domain results were analyzed before and after structural alterations. Their effects were studied in a 500 Hz bandwidth, showing a drift in the resonant frequency of the structure from 145 Hz to 152 Hz, and, additionally, a harmonic displacement: medium-frequency components experienced a 50 Hz drift, while low-frequency components collapsed into two harmonics at 60 Hz and 90 Hz. These tests proved the system’s functionality and the feasibility of this method for structural integrity analysis and, eventually, damage evaluation. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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Open AccessArticle

Simple and Accurate Model for the Propagation Delay in MCML Gates

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Gianluca Giustolisi

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Giuseppe Scotti

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Gaetano Palumbo

Electronics 2023, 12(12), 2680; https://doi.org/10.3390/electronics12122680 - 15 Jun 2023

Viewed by 638

Abstract

In this article, we develop a simple and accurate model for evaluating the propagation delay in MOS Current-Mode Logic (MCML) gates. The model describes the behavior of MCML gates in a linear fashion despite the circuits themselves being non-linear. Indeed, we demonstrate that [...] Read more.

In this article, we develop a simple and accurate model for evaluating the propagation delay in MOS Current-Mode Logic (MCML) gates. The model describes the behavior of MCML gates in a linear fashion despite the circuits themselves being non-linear. Indeed, we demonstrate that a linear model can be used, provided that, for each small-signal parameter, its average value calculated between the two different switching logic states is used. The proposed model is validated through simulations of MCML universal gates designed using modern nanometer processes. The model forecasts simulated values with an error lower than 4% and 20% in 65-nm standard CMOS and 28-nm Fully-Depleted Silicon-On-Insulator (FD-SOI), respectively. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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Open AccessArticle

A Wireless, Battery-Powered Probe Based on a Dual-Tier CMOS SPAD Array for Charged Particle Sensing

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Joana Minga

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Paolo Brogi

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Gianmaria Collazuol

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Gian-Franco Dalla Betta

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Pier Simone Marrocchesi

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Electronics 2023, 12(11), 2549; https://doi.org/10.3390/electronics12112549 - 05 Jun 2023

Viewed by 689

Abstract

A compact probe for charged particle imaging, with potential applications in source activity mapping and radio-guided surgery was designed and tested. The development of this technology holds significant implications for medical imaging, offering healthcare professionals accurate and efficient tools for diagnoses and treatments. [...] Read more.

A compact probe for charged particle imaging, with potential applications in source activity mapping and radio-guided surgery was designed and tested. The development of this technology holds significant implications for medical imaging, offering healthcare professionals accurate and efficient tools for diagnoses and treatments. To fulfill the portability requirements of these applications, the probe was designed for battery operation and wireless communication with a PC. The core sensor is a dual-layer CMOS SPAD detector, fabricated using 150 nm technology, which uses overlapping cells to produce a coincidence signal and reduce the dark count rate (DCR). The sensor is managed and interfaced with a microcontroller, and custom firmware was developed to facilitate communication with the sensor. The performance of the probe was evaluated by characterizing the on-board SPAD detector in terms of the DCR, and the results were consistent with the characterization measurements taken on the same chip samples using a purposely developed benchtop setup. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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Open AccessFeature PaperArticle

Elucidation of Response and Electrochemical Mechanisms of Bio-Inspired Rubber Sensors with Supercapacitor Paradigm

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Kunio Shimada

Electronics 2023, 12(10), 2304; https://doi.org/10.3390/electronics12102304 - 19 May 2023

Viewed by 540

Abstract

The electrochemical paradigm of a supercapacitor (SC) is effective for investigating cutting-edge deformable and haptic materials made of magnetic compound fluid (MCF) rubber in order to advance the production of bio-inspired sensors as artificial haptic sensors mimicking human tissues. In the present study, [...] Read more.

The electrochemical paradigm of a supercapacitor (SC) is effective for investigating cutting-edge deformable and haptic materials made of magnetic compound fluid (MCF) rubber in order to advance the production of bio-inspired sensors as artificial haptic sensors mimicking human tissues. In the present study, we measure the cyclic voltammetry (CV) profiles and electric properties with electrochemical impedance spectroscopy (EIS) to morphologically evaluate the intrinsic structure of MCF rubber containing fillers and agents. In addition, the electrochemical mechanisms of molecule and particle behavior are theorized using the SC physical framework. The solid-doped fillers in the MCF rubber characterized the behavior of the electrical double-layer capacitor (EDLC). Meanwhile, the liquid agents showed the characteristics of a pseudocapacitor (PC) due to the redox response among the molecules and particles. The potential responses to extraneous stimuli relevant to the EIS properties, categorized as slow adaption (SA), fast adaption (FA), and other type (OT), were also analyzed in terms of the sensory response of the bio-inspired sensor. The categories were based on how the response was induced from the EIS properties. By controlling the EIS properties with different types of doping agents, sensors with various sensory responses become feasible. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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Open AccessArticle

Analysis of Doherty Power Amplifier Matching Assisted by Physics-Based Device Modelling

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Simona Donati Guerrieri

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Eva Catoggio

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Fabrizio Bonani

Electronics 2023, 12(9), 2101; https://doi.org/10.3390/electronics12092101 - 04 May 2023

Viewed by 708

Abstract

The Doherty Power Amplifier represents one of the most promising solutions for the design of high-efficiency power stages. In the widely adopted ABC scheme, the Doherty Amplifier design critically depends on the accuracy of the device model in different operating conditions, ranging from [...] Read more.

The Doherty Power Amplifier represents one of the most promising solutions for the design of high-efficiency power stages. In the widely adopted ABC scheme, the Doherty Amplifier design critically depends on the accuracy of the device model in different operating conditions, ranging from class AB to class C. For the class C case, library models are often inaccurate, while experimental characterization is difficult since it must be carried out in large signal conditions and with varying gate bias. In this paper, we propose an alternative approach, based on physics-based Technological CAD (TCAD) simulations of the complete Doherty amplifier along with the analysis of its individual MAIN (class AB) and AUXILIARY (class C) stages. TCAD simulations seamlessly provide an accurate modelling of the device behavior in all operation classes, including the device turn-on and the nonlinear capacitances, and easily account for the cross-loading effects of the MAIN and AUXILIARY devices through the output network and the effect of the device feedback (gate-drain) capacitance on the input matching. Analyzing a GaAs Doherty stage at 12 GHz, we show that the input phase of the auxiliary stage can be exploited for the Doherty power amplifier optimization in terms of gain, linearity and efficiency, showing a 9 dB gain with less than 1 dB gain variation from back-off to peak power with a power-added efficiency exceeding 45% over a Doherty region extending to a more than 6 dB output power back-off. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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Open AccessArticle

Parameter Identification of Li-ion Batteries: A Comparative Study

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Shahenda M. Abdelhafiz

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Mohammed E. Fouda

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Ahmed G. Radwan

Electronics 2023, 12(6), 1478; https://doi.org/10.3390/electronics12061478 - 21 Mar 2023

Cited by 1 | Viewed by 1123

Abstract

Lithium-ion batteries are crucial building stones in many applications. Therefore, modeling their behavior has become necessary in numerous fields, including heavyweight ones such as electric vehicles and plug-in hybrid electric vehicles, as well as lightweight ones like sensors and actuators. Generic models are [...] Read more.

Lithium-ion batteries are crucial building stones in many applications. Therefore, modeling their behavior has become necessary in numerous fields, including heavyweight ones such as electric vehicles and plug-in hybrid electric vehicles, as well as lightweight ones like sensors and actuators. Generic models are in great demand for modeling the current change over time in real-time applications. This paper proposes seven dynamic models to simulate the behavior of lithium-ion batteries discharging. This was achieved using NASA room temperature random walk discharging datasets. The efficacy of these models in fitting different time-domain responses was tested through parameter identification with the Marine Predator Algorithm (MPA). In addition, each model’s term’s impact was analyzed to understand its effect on the fitted curve. The proposed models show an average absolute normalized error as low as

0.0057

. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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Open AccessCommunication

An Encryption Application and FPGA Realization of a Fractional Memristive Chaotic System

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Electronics 2023, 12(5), 1219; https://doi.org/10.3390/electronics12051219 - 03 Mar 2023

Cited by 6 | Viewed by 1084

Abstract

The work in this paper extends a memristive chaotic system with transcendental nonlinearities to the fractional-order domain. The extended system’s chaotic properties were validated through bifurcation analysis and spectral entropy. The presented system was employed in the substitution stage of an image encryption [...] Read more.

The work in this paper extends a memristive chaotic system with transcendental nonlinearities to the fractional-order domain. The extended system’s chaotic properties were validated through bifurcation analysis and spectral entropy. The presented system was employed in the substitution stage of an image encryption algorithm, including a generalized Arnold map for the permutation. The encryption scheme demonstrated its efficiency through statistical tests, key sensitivity analysis and resistance to brute force and differential attacks. The fractional-order memristive system includes a reconfigurable coordinate rotation digital computer (CORDIC) and Grünwald–Letnikov (GL) architectures, which are essential for trigonometric and hyperbolic functions and fractional-order operator implementations, respectively. The proposed system was implemented on the Artix-7 FPGA board, achieving a throughput of 0.396 Gbit/s. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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Open AccessArticle

Improving the Spatial Characteristics of Three-Level LUT-Based Mealy FSM Circuits

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Alexander Barkalov

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Larysa Titarenko

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Małgorzata Mazurkiewicz

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Kazimierz Krzywicki

Electronics 2023, 12(5), 1133; https://doi.org/10.3390/electronics12051133 - 26 Feb 2023

Viewed by 854

Abstract

The main purpose of the method proposed in this article is to reduce the number of look-up-table (LUT) elements in logic circuits of sequential devices. The devices are represented by models of Mealy finite state machines (FSMs). Thesee are so-called MPY FSMs based [...] Read more.

The main purpose of the method proposed in this article is to reduce the number of look-up-table (LUT) elements in logic circuits of sequential devices. The devices are represented by models of Mealy finite state machines (FSMs). Thesee are so-called MPY FSMs based on two methods of structural decomposition (the replacement of inputs and encoding of output collections). The main idea is to use two types of state codes for implementing systems of partial Boolean functions. Some functions are based on maximum binary codes; other functions depend on extended state codes. The reduction in LUT counts is based on using the method of twofold state assignment. The proposed method makes it possible to obtain FPGA-based FSM circuits with four logic levels. Only one LUT is required to implement the circuit corresponding to any partial function. An example of FSM synthesis using the proposed method is shown. The results of the conducted experiments show that the proposed approach produces LUT-based FSM circuits with better area-temporal characteristics than for circuits produced using such methods as Auto and One-hot of Vivado, JEDI, and MPY FSMs. Compared to MPY FSMs, the values of LUT counts are improved. On average, this improvement is 8.98%, but the gain reaches 13.65% for fairly complex FSMs. The maximum operating frequency is slightly improved as compared with the circuits of MPY FSMs (up to 0.64%). For both LUT counts and frequency, the gain increases together with the growth for the numbers of FSM inputs, outputs and states. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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Open AccessFeature PaperArticle

MWIRGAN: Unsupervised Visible-to-MWIR Image Translation with Generative Adversarial Network

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Mohammad Shahab Uddin

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Chiman Kwan

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Jiang Li

Electronics 2023, 12(4), 1039; https://doi.org/10.3390/electronics12041039 - 20 Feb 2023

Cited by 2 | Viewed by 1255

Abstract

Unsupervised image-to-image translation techniques have been used in many applications, including visible-to-Long-Wave Infrared (visible-to-LWIR) image translation, but very few papers have explored visible-to-Mid-Wave Infrared (visible-to-MWIR) image translation. In this paper, we investigated unsupervised visible-to-MWIR image translation using generative adversarial networks (GANs). We proposed [...] Read more.

Unsupervised image-to-image translation techniques have been used in many applications, including visible-to-Long-Wave Infrared (visible-to-LWIR) image translation, but very few papers have explored visible-to-Mid-Wave Infrared (visible-to-MWIR) image translation. In this paper, we investigated unsupervised visible-to-MWIR image translation using generative adversarial networks (GANs). We proposed a new model named MWIRGAN for visible-to-MWIR image translation in a fully unsupervised manner. We utilized a perceptual loss to leverage shape identification and location changes of the objects in the translation. The experimental results showed that MWIRGAN was capable of visible-to-MWIR image translation while preserving the object’s shape with proper enhancement in the translated images and outperformed several competing state-of-the-art models. In addition, we customized the proposed model to convert game-engine-generated (a commercial software) images to MWIR images. The quantitative results showed that our proposed method could effectively generate MWIR images from game-engine-generated images, greatly benefiting MWIR data augmentation. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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Open AccessFeature PaperArticle

PSO-Based Target Localization and Tracking in Wireless Sensor Networks

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Electronics 2023, 12(4), 905; https://doi.org/10.3390/electronics12040905 - 10 Feb 2023

Cited by 6 | Viewed by 1590

Abstract

Research of target localization and tracking is always a remarkable problem in the application of wireless sensor networks (WSNs) technology. There are many kinds of research and applications of target localization and tracking, such as Angle of Arrival (AOA), Time of Arrival (TOA), [...] Read more.

Research of target localization and tracking is always a remarkable problem in the application of wireless sensor networks (WSNs) technology. There are many kinds of research and applications of target localization and tracking, such as Angle of Arrival (AOA), Time of Arrival (TOA), and Time Difference of Arrival (TDOA). The target localization accuracy for TOA, TDOA, and AOA is better than RSS. However, the required devices in the TOA, TDOA, and AOA are more expensive than RSS. In addition, the computational complexity of TOA, TDOA, and AOA is also more complicated than RSS. This paper uses a particle swarm optimization (PSO) algorithm with the received signal strength index (RSSI) channel model for indoor target localization and tracking. The performance of eight different method combinations of random or regular points, fixed or adaptive weights, and the region segmentation method (RSM) proposed in this paper for target localization and tracking is investigated for the number of particles in the PSO algorithm with 12, 24, 52, 72, and 100. The simulation results show that the proposed RSM method can reduce the number of particles used in the PSO algorithm and improve the speed of positioning and tracking without affecting the accuracy of target localization and tracking. The total average localization time for target localization and tracking with the RSM method can be reduced by 48.95% and 34.14%, respectively, and the average accuracy of target tracking reaches up to 93.09%. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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Open AccessCommunication

High-Throughput Bit-Pattern Matching under Heavy Interference on FPGA

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Dimitris Nikolaidis

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Panos Groumas

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Christos Kouloumentas

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Hercules Avramopoulos

Electronics 2023, 12(4), 803; https://doi.org/10.3390/electronics12040803 - 06 Feb 2023

Viewed by 868

Abstract

Bit-pattern matching is an important technological capability, used in many fields such as network intrusion detection (NID) and packet classification systems. Essentially, it involves the matching of an input bit pattern to a bit-pattern entry of a memory structure inside the system. Contemporary [...] Read more.

Bit-pattern matching is an important technological capability, used in many fields such as network intrusion detection (NID) and packet classification systems. Essentially, it involves the matching of an input bit pattern to a bit-pattern entry of a memory structure inside the system. Contemporary methods focus on the decomposition of the input bit pattern into smaller and more manageable parts, with the subsequent parallel processing of these elements. This fragmentation promotes the use of advanced pipeline techniques and hardware optimizations, enabling these methods to achieve very high throughputs and reasonable efficiency. However, the functionality of their respective circuits is limited to only performing pattern matching when there is no interference. In this article, we intend to present a circuit that performs pattern matching under heavy interference; instead of fragmentation, a more holistic approach will be adopted. To improve the throughput of the circuit, long bit sequences will be directly compared to many memory entries simultaneously. The minimization of hardware consumption and maximization of efficiency in these comparisons will be achieved with the use of novel hardware architecture that is based on pipelined adder trees and comparators. The platform of implementation is an FPGA (Field-Programmable Gate Array). Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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Open AccessArticle

Asymmetric 5.5 GHz Three-Stage Voltage-Controlled Ring-Oscillator in 65 nm CMOS Technology

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Electronics 2023, 12(3), 778; https://doi.org/10.3390/electronics12030778 - 03 Feb 2023

Viewed by 1272

Abstract

The current trend of increasing the complexity of hardware accelerators to improve their functionality is highlighting the problem of sharing a high-frequency clock signal for all integrated modules. As the clock itself is becoming the main limitation to the performance of accelerators, in [...] Read more.

The current trend of increasing the complexity of hardware accelerators to improve their functionality is highlighting the problem of sharing a high-frequency clock signal for all integrated modules. As the clock itself is becoming the main limitation to the performance of accelerators, in this manuscript, we present the design of an asymmetric Ring Oscillator-Voltage-Controlled Oscillator (RO-VCO) based on the Current Mode Logic architecture. The RO-VCO was designed on commercial-grade 65 nm CMOS technology, and it is capable of driving large capacitance loads, avoiding the need for additional buffers for clock-trees, reducing the silicon area and power consumption. The proposed RO-VCO is composed of three closed-loop differential and asymmetrical stages, and it is able to tune the working frequency in the range from 4.72 GHz to 6.12 GHz. The phase noise and a figure of merit of −103.2 dBc/Hz and −186 dBc/Hz were obtained at 1 MHz offset from the 5.5 GHz carrier. In this article, the analytical model, full custom schematic, and layout of the proposed RO-VCO are presented and discussed in detail together with the experimental electrical and thermal characterization of the fabricated device. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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Open AccessFeature PaperArticle

Supervised Contrastive Learning for Voice Activity Detection

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Youngjun Heo

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Sunggu Lee

Electronics 2023, 12(3), 705; https://doi.org/10.3390/electronics12030705 - 31 Jan 2023

Viewed by 1133

Abstract

The noise robustness of voice activity detection (VAD) tasks, which are used to identify the human speech portions of a continuous audio signal, is important for subsequent downstream applications such as keyword spotting and automatic speech recognition. Although various aspects of VAD have [...] Read more.

The noise robustness of voice activity detection (VAD) tasks, which are used to identify the human speech portions of a continuous audio signal, is important for subsequent downstream applications such as keyword spotting and automatic speech recognition. Although various aspects of VAD have been recently studied by researchers, a proper training strategy for VAD has not received sufficient attention. Thus, a training strategy for VAD using supervised contrastive learning is proposed for the first time in this paper. The proposed method is used in conjunction with audio-specific data augmentation methods. The proposed supervised contrastive learning-based VAD (SCLVAD) method is trained using two common speech datasets and then evaluated using a third dataset. The experimental results show that the SCLVAD method is particularly effective in improving VAD performance in noisy environments. For clean environments, data augmentation improves VAD accuracy by 8.0 to 8.6%, but there is no improvement due to the use of supervised contrastive learning. On the other hand, for noisy environments, the SCLVAD method results in VAD accuracy improvements of 2.9% and 4.6% for “speech with noise” and “speech with music”, respectively, with only a negligible increase in processing overhead during training. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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Open AccessArticle

FPGA-Based Tactile Sensory Platform with Optical Fiber Data Link for Feedback Systems in Prosthetics

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Guido Di Patrizio Stanchieri

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Electronics 2023, 12(3), 627; https://doi.org/10.3390/electronics12030627 - 27 Jan 2023

Cited by 1 | Viewed by 868

Abstract

In this paper, we propose and validate a tactile sensory feedback system for prosthetic applications based on an optical communication link. The optical link features a low power and wide transmission bandwidth, which makes the feedback system suitable for a large number and [...] Read more.

In this paper, we propose and validate a tactile sensory feedback system for prosthetic applications based on an optical communication link. The optical link features a low power and wide transmission bandwidth, which makes the feedback system suitable for a large number and variety of tactile sensors. The low-power transmission is derived from the employed UWB-based optical modulation technique. A system prototype, consisting of digital transmitter and receiver boards and acquisition circuits to interface 32 piezoelectric sensors, was implemented and experimentally tested. The system functionality was demonstrated by processing and transmitting data from the piezoelectric sensor at a 100 Mbps data rate through the optical link, measuring a communication energy consumption of 50 pJ/bit. The reported experimental results validate the functionality of the proposed sensory feedback system and demonstrate its real-time operation capabilities. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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Open AccessArticle

Software Engineering of Resistive Elements Electrophysical Parameters Simulation in the Process of Laser Trimming

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Vladimir V. Kondrashov

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Oleg S. Seredin

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Vyacheslav V. Chapkin

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Evgeny V. Zemlyakov

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Ilya K. Topalov

Electronics 2023, 12(3), 589; https://doi.org/10.3390/electronics12030589 - 25 Jan 2023

Viewed by 827

Abstract

This study continues a series of papers covering the R&D of circuit simulators embedded into manufacturing equipment for the laser trimming of film and foil resistors intended to improve the final product’s performance and reduce process costs. Our paper describes the development of [...] Read more.

This study continues a series of papers covering the R&D of circuit simulators embedded into manufacturing equipment for the laser trimming of film and foil resistors intended to improve the final product’s performance and reduce process costs. Our paper describes the development of the ResModel laser trimming simulation software. Various types of trims and their features are presented for a circuit with a dynamic measurement DC source, and the optimal trim configurations are identified. The software can be used to estimate and display resistive element properties during the trimming such as its electrophysical parameters and their trends. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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Open AccessArticle

Improving Performance of Hardware Accelerators by Optimizing Data Movement: A Bioinformatics Case Study

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Peter Knoben

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Nikolaos Alachiotis

Electronics 2023, 12(3), 586; https://doi.org/10.3390/electronics12030586 - 24 Jan 2023

Viewed by 796

Abstract

Modern hardware accelerator cards create an accessible platform for developers to reduce execution times for computationally expensive algorithms. The most widely used systems, however, have dedicated memory spaces, resulting in the processor having to transfer data to the accelerator-card memory space before the [...] Read more.

Modern hardware accelerator cards create an accessible platform for developers to reduce execution times for computationally expensive algorithms. The most widely used systems, however, have dedicated memory spaces, resulting in the processor having to transfer data to the accelerator-card memory space before the computation can be executed. Currently, the performance increase from using an accelerator card for data-intensive algorithms is limited by the data movement. To this end, this work aims to reduce the effect of data movement and improve overall performance by systematically caching data on the accelerator card. We designed a software-controlled split cache where data are cached on the accelerator and assessed its efficacy using a data-intensive Bioinformatics application that infers the evolutionary history of a set of organisms by constructing phylogenetic trees. Our results revealed that software-controlled data caching on a datacenter-grade FPGA accelerator card reduced the overhead of data movement by 90%. This resulted in a reduction of the total execution time between 32% and 40% for the entire application when phylogenetic trees of various sizes were constructed. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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Open AccessFeature PaperArticle

Dynamical Analysis and Synchronization of a New Memristive Chialvo Neuron Model

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Gayathri Vivekanandhan

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Hayder Natiq

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Yaser Merrikhi

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Karthikeyan Rajagopal

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Sajad Jafari

Electronics 2023, 12(3), 545; https://doi.org/10.3390/electronics12030545 - 20 Jan 2023

Cited by 6 | Viewed by 1058

Abstract

Chialvo is one of the two-dimensional map-based neural models. In this paper, a memristor is added to this model to consider the electromagnetic induction’s effects. The memristor is defined based on a hyperbolic tangent function. The dynamical variations are analyzed by obtaining the [...] Read more.

Chialvo is one of the two-dimensional map-based neural models. In this paper, a memristor is added to this model to consider the electromagnetic induction’s effects. The memristor is defined based on a hyperbolic tangent function. The dynamical variations are analyzed by obtaining the bifurcation diagrams and Lyapunov spectra. It is shown that the most effective parameters on the dynamics are the magnetic strength and the injected current. The memristive Chialvo can exhibit different neural behaviors. It is also proven that, like the primary Chialvo model, the memristive version has coexisting attractors; an oscillating state coexists with a fixed point. In addition, to understand how memristive neurons behave in a network, two memristive Chialvo models are coupled with electrochemical synapses. By connecting two neurons and calculating the synchronization error, we can determine the system’s synchronizability. It is indicated that the electrical coupling is essential for the occurrence of complete synchronization in the network of memristive Chialvo, and the sole chemical coupling does not lead to synchronization. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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Open AccessArticle

Design of Generalized Enhanced Static Segment Multiplier with Minimum Mean Square Error for Uniform and Nonuniform Input Distributions

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Gennaro Di Meo

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Gerardo Saggese

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Antonio G. M. Strollo

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Davide De Caro

Electronics 2023, 12(2), 446; https://doi.org/10.3390/electronics12020446 - 15 Jan 2023

Viewed by 827

Abstract

In this paper, we analyze the performances of an Enhanced Static Segment Multiplier (ESSM) when the inputs have both uniform and non-uniform distribution. The enhanced segmentation divides the multiplicands into a lower, a middle, and an upper segment. While the middle segment is [...] Read more.

In this paper, we analyze the performances of an Enhanced Static Segment Multiplier (ESSM) when the inputs have both uniform and non-uniform distribution. The enhanced segmentation divides the multiplicands into a lower, a middle, and an upper segment. While the middle segment is placed at the center of the inputs in other implementations, we seek the optimal position able to minimize the approximation error. To this aim, two design parameters are exploited: m, defining the size and the accuracy of the multiplier, and q, defining the position of the middle segment for further accuracy tuning. A hardware implementation is proposed for our generalized ESSM (gESSM), and an analytical model is described, able to find m and q which minimize the mean square approximation error. With uniform inputs, the error slightly improves by increasing q, whereas a large error decrease is observed by properly choosing q when the inputs are half-normal (with a NoEB up to 18.5 bits for a 16-bit multiplier). Implementation results in 28 nm CMOS technology are also satisfactory, with area and power reductions up to 71% and 83%. We report image and audio processing applications, showing that gESSM is a suitable candidate in applications with non-uniform inputs. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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Open AccessArticle

Implementation and Experimental Verification of Resistorless Fractional-Order Basic Filters

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Electronics 2022, 11(23), 3988; https://doi.org/10.3390/electronics11233988 - 01 Dec 2022

Viewed by 785

Abstract

Novel structures of fractional-order differentiation and integration stages are presented in this work, where passive resistors are not required for their implementation. This has been achieved by considering the inherent resistive behavior of fractional-order capacitors. The implementation of the presented stages is performed [...] Read more.

Novel structures of fractional-order differentiation and integration stages are presented in this work, where passive resistors are not required for their implementation. This has been achieved by considering the inherent resistive behavior of fractional-order capacitors. The implementation of the presented stages is performed using a current feedback operational amplifier as active element and fractional-order capacitors based on multi-walled carbon nano-tubes. Basic filter and controller stages are realized using the introduced fundamental blocks, and their behavior is evaluated through experimental results. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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Open AccessArticle

A Universal Electronically Controllable Memelement Emulator Based on VDCC with Variable Configuration

by

Predrag B. Petrović

Electronics 2022, 11(23), 3957; https://doi.org/10.3390/electronics11233957 - 29 Nov 2022

Cited by 2 | Viewed by 821

Abstract

In this paper, a universal fractional order memelement (FOME) emulator is proposed based on the use of a voltage differentiating current conveyor (VDCC) as active block. The emulation circuit was implemented without an analog voltage multiplier and with only one type of grounded [...] Read more.

In this paper, a universal fractional order memelement (FOME) emulator is proposed based on the use of a voltage differentiating current conveyor (VDCC) as active block. The emulation circuit was implemented without an analog voltage multiplier and with only one type of grounded passive element—capacitors. Specially designed switching networks allow controlling the type of memelement and the emulator mode—floating or/and grounded, electronically controlled (by changing the bias voltage of the VDCC) FOMEs. The proposed emulator was theoretically analyzed, and the influence of possible non-idealities and parasitic effects was also been analyzed to reduce the undesirable effects by selecting the passive circuit elements. The proposed designs are very simple compared to most of the designs available in the literature and can operate in a wide frequency range (up to 50 MHz) and also satisfy the non-volatility test. All realized memelements can be used in incremental and decremental modes as well as in inverse configuration. The performance of the circuit was verified by HSPICE simulations using 0.18 μm TSMC process parameters and ±0.9 V power supply. The proposal is also supported by experimental results with off-the-shelf components (LM13700 and one AD844) in order to confirm the proposed solution’s workability. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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Open AccessArticle

Knowledge Distillation for Image Signal Processing Using Only the Generator Portion of a GAN

by

Youngjun Heo

and

Sunggu Lee

Electronics 2022, 11(22), 3815; https://doi.org/10.3390/electronics11223815 - 20 Nov 2022

Viewed by 838

Abstract

Knowledge distillation, in which the parameter values learned in a large teacher network are transferred to a smaller student network, is a popular and effective network compression method. Recently, researchers have proposed methods to improve the performance of a student network by using [...] Read more.

Knowledge distillation, in which the parameter values learned in a large teacher network are transferred to a smaller student network, is a popular and effective network compression method. Recently, researchers have proposed methods to improve the performance of a student network by using a Generative Adverserial Network (GAN). However, because a GAN is an architecture that is ideally used to create realistic synthetic images, a pure GAN architecture may not be ideally suited for knowledge distillation. In knowledge distillation for image signal processing, synthetic images do not need to be realistic, but instead should include features that help the training of the student network. In the proposed Generative Image Processing (GIP) method, this is accomplished by using only the generator portion of a GAN and utilizing special techniques to capture the distinguishing feature capability of the teacher network. Experimental results show that the GIP method outperforms knowledge distillation using GANs as well as training using only knowledge distillation. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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Open AccessArticle

Hybrid Full Adders: Optimized Design, Critical Review and Comparison in the Energy-Delay Space

by

Gianluca Giustolisi

and

Gaetano Palumbo

Electronics 2022, 11(19), 3220; https://doi.org/10.3390/electronics11193220 - 08 Oct 2022

Viewed by 1197

Abstract

In this paper, we design and compare seven meaningful hybrid one-bit full adders topologies that are optimized in terms of energy-delay trade-offs to operate in multibit ripple carry adders. The goal is to provide the designer with a simple and powerful approach for [...] Read more.

In this paper, we design and compare seven meaningful hybrid one-bit full adders topologies that are optimized in terms of energy-delay trade-offs to operate in multibit ripple carry adders. The goal is to provide the designer with a simple and powerful approach for choosing the best topology for a given power budget, speed performance, or any combination of both. The design and comparison deal with 4-bit and 8-bit ripple carry adders and exploit the derivation of the energy-efficient curves in the energy-delay space. To do so, first we define the procedures to obtain energy consumption and propagation delay by simulating a ripple carry adder designed at a transistor level. Then, we introduce a design methodology to optimize a ripple carry adder by minimizing some significant figures-of-merit in terms of energy-delay trade-offs. The comparison of the energy-efficient curves allows us to make a simple and effective comparison as well as to identify the best one-bit full adder topologies. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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Open AccessArticle

On Unstable Spatial Modes and Patterns in Cellular and Graph Neural Circuits

by

Liviu Goras

Electronics 2022, 11(19), 3033; https://doi.org/10.3390/electronics11193033 - 23 Sep 2022

Viewed by 737

Abstract

The aim of this paper is to discuss several aspects regarding the dynamics and pattern formation in select cellular and graph neural circuit type architectures and to propose a new application. A unifying approach for these types of neural circuits based on unstable [...] Read more.

The aim of this paper is to discuss several aspects regarding the dynamics and pattern formation in select cellular and graph neural circuit type architectures and to propose a new application. A unifying approach for these types of neural circuits based on unstable spatial modes using the mode decoupling technique is presented. The main objective of this study is that of showing the way the dynamics can be prescribed by speculating the relationship between the extended graph Laplacian and nodal equations of a specific architecture. Based on the above, the possibility of designing a so-called spatial comparator that can extract the sign of a prescribed spatial mode contained in a spatial signal, using unstable circuits for which that mode is associated with a right half-plane eigenvalue, is analyzed and illustrated with simulations in CMOS technology. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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Open AccessArticle

Bridging the Gap between Physical and Circuit Analysis for Variability-Aware Microwave Design: Power Amplifier Design

by

Simona Donati Guerrieri

,

Chiara Ramella

,

Eva Catoggio

and

Fabrizio Bonani

Electronics 2022, 11(18), 2832; https://doi.org/10.3390/electronics11182832 - 08 Sep 2022

Cited by 1 | Viewed by 1088

Abstract

Process Induced Variability (PIV) stemming from fabrication tolerance can impact the performance of integrated circuits. This issue is particularly significant at high frequencies, since Monolithic Microwave Integrated Circuits (MMICs) rely on advanced semiconductor technologies exploiting device sizes at the nanoscale in conjunction with [...] Read more.

Process Induced Variability (PIV) stemming from fabrication tolerance can impact the performance of integrated circuits. This issue is particularly significant at high frequencies, since Monolithic Microwave Integrated Circuits (MMICs) rely on advanced semiconductor technologies exploiting device sizes at the nanoscale in conjunction with complex passive structures, featuring both distributed elements (transmission lines) and lumped components. Black-box (behavioral) models extracted from accurate physical simulations can be profitably exploited to incorporate PIV into circuit-level MMIC analysis. In this paper, these models are applied to the statistical analysis of a single and of a combined MMIC power amplifier designed in GaAs technology for X-band applications. The relative impact of the active device variability towards the passive matching networks one is evaluated, demonstrating the relevance of PIV. The significant spread found, with only two variable parameters, confirms the importance of a PIV-aware PA design approach, with suitable margins and careful network optimization. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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Open AccessFeature PaperArticle

A Second Order 1.8–1.9 GHz Tunable Active Band-Pass Filter with Improved Noise Performances

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Electronics 2022, 11(17), 2781; https://doi.org/10.3390/electronics11172781 - 03 Sep 2022

Viewed by 1193

Abstract

In this paper, a novel active tunable band-pass filter with improved noise performances is presented. This filter is based on a negative resistance circuit (or active capacitance), where the gain obtained with a transistor is used to compensate for inductor losses. Moreover, the [...] Read more.

In this paper, a novel active tunable band-pass filter with improved noise performances is presented. This filter is based on a negative resistance circuit (or active capacitance), where the gain obtained with a transistor is used to compensate for inductor losses. Moreover, the capacitance of the resonator is obtained through a voltage-controlled reverse-biased varactor, which allows for frequency tuning. Despite the active component, the proposed filter also has good noise performance. Measurements show a tunability range from 1.816 GHz to 1.886 GHz, with a bandwidth of 38 MHz. The insertion loss maximum value is 0.4 dB, while the noise figure value has a minimum value of 2.5 dB at the center frequency within the tunability range. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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Open AccessArticle

0.4-V, 81.3-nA Bulk-Driven Single-Stage CMOS OTA with Enhanced Transconductance

by

Andrea Ballo

,

Alfio Dario Grasso

and

Salvatore Pennisi

Electronics 2022, 11(17), 2704; https://doi.org/10.3390/electronics11172704 - 29 Aug 2022

Cited by 3 | Viewed by 1726

Abstract

The paper describes a single-stage operational transconductance amplifier suitable for very-low-voltage operation in power-constrained applications. The proposed circuit avoids the tail current generator in the differential pair while preventing pseudo-differential operation. Moreover, the adoption of positive feedback allows increasing the stage transconductance while [...] Read more.

The paper describes a single-stage operational transconductance amplifier suitable for very-low-voltage operation in power-constrained applications. The proposed circuit avoids the tail current generator in the differential pair while preventing pseudo-differential operation. Moreover, the adoption of positive feedback allows increasing the stage transconductance while minimizing the current consumption. Experimental measurements on prototypes implemented in a standard CMOS 180-nm technology, show superior performance as compared to the state of the art. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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Open AccessArticle

High−Performance 4H−SiC UV p−i−n Photodiode: Numerical Simulations and Experimental Results

by

Sandro Rao

,

Elisa D. Mallemace

and

Francesco G. Della Corte

Electronics 2022, 11(12), 1839; https://doi.org/10.3390/electronics11121839 - 09 Jun 2022

Cited by 4 | Viewed by 1365

Abstract

In this work, the optical response of a high−performance 4H−SiC−based p−i−n ultraviolet (UV) photodiode was studied by means of an ad hoc numerical model. The spectral responsivity and the corresponding external photodiode quantum efficiency were calculated under different reverse biases, up to 60 [...] Read more.

In this work, the optical response of a high−performance 4H−SiC−based p−i−n ultraviolet (UV) photodiode was studied by means of an ad hoc numerical model. The spectral responsivity and the corresponding external photodiode quantum efficiency were calculated under different reverse biases, up to 60 V, and in the wavelength range from λ = 190 to 400 nm. The responsivity peak is R = 0.168 A/W at λ = 292 nm at 0 V and improves as bias increases, reaching R = 0.212 A/W at 60 V and λ = 298 nm. The external quantum efficiency is about 71% and 88%. The good quality of the simulation setup was confirmed by comparison with experimental measurements performed on a p−i−n device fabricated starting from a commercial 4H−SiC wafer. The developed numerical model, together with the material electrical and optical parameters used in our simulations, can be therefore explored for the design of more complex 4H−SiC−based solid−state electronic and optoelectronic devices. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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Open AccessArticle

CNTFET-Based Ternary Multiply-and-Accumulate Unit

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Electronics 2022, 11(9), 1455; https://doi.org/10.3390/electronics11091455 - 30 Apr 2022

Cited by 3 | Viewed by 1381

Abstract

Multiply-Accumulate (MAC) is one of the most commonly used operations in modern computing systems due to its use in matrix multiplication, signal processing, and in new applications such as machine learning and deep neural networks. Ternary number system offers higher information processing within [...] Read more.

Multiply-Accumulate (MAC) is one of the most commonly used operations in modern computing systems due to its use in matrix multiplication, signal processing, and in new applications such as machine learning and deep neural networks. Ternary number system offers higher information processing within the same number of digits when compared to binary systems. In this paper, a MAC is proposed using a CNTFET-based ternary logic number. Specifically, we build a 5-trit multiplier and 10-trit adder as building blocks of two ternary MAC unit designs. The first is a basic MAC which has two methods to implement, serial and pipeline. The second is an improved MAC design that optimizes the number of transistors, offers higher performance and lower power consumption. The designed MAC unit can operate up to 300 MHz. Finally, a comparative study in terms of power, delay, and area variations is conducted under different supply voltages and temperature levels. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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Open AccessFeature PaperArticle

A Novel Low-Power High-Precision Implementation for Sign–Magnitude DLMS Adaptive Filters

by

Gennaro Di Meo

,

Davide De Caro

,

Nicola Petra

and

Antonio G. M. Strollo

Electronics 2022, 11(7), 1007; https://doi.org/10.3390/electronics11071007 - 24 Mar 2022

Cited by 1 | Viewed by 1233

Abstract

This paper investigates the use of approximate fixed-width and static segment multipliers in the design of Delayed Least Mean Square (DLMS) adaptive filters based on the sign–magnitude representation for the error signal. The fixed-width approximation discards part of the partial product matrix and [...] Read more.

This paper investigates the use of approximate fixed-width and static segment multipliers in the design of Delayed Least Mean Square (DLMS) adaptive filters based on the sign–magnitude representation for the error signal. The fixed-width approximation discards part of the partial product matrix and introduces a compensation function for minimizing the approximation error, whereas the static segmented multipliers reduce the bit-width of the multiplicands at runtime. The use of sign–magnitude representation for the error signal reduces the switching activity in the filter learning section, minimizing power dissipation. Simulation results reveal that, by properly sizing the two approaches, a steady state mean square error practically unchanged with respect to the exact DLMS can be achieved. The hardware syntheses in a 28 nm CMOS technology reveal that the static segmented multipliers perform better in the learning section of the filter and are the most efficient approach to reduce area occupation, while the fixed-width multipliers offer the best performances in the finite impulse response section and provide the lowest power dissipation. The investigated adaptive filters overcome the state-of-the-art, exhibiting an area and power reduction with respect to the standard implementation up to −18.0% and −64.1%, respectively, while preserving the learning capabilities. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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Open AccessArticle

Novel Approach and Methods for Optimizing Highly Sensitive Low Noise Amplifier CMOS IC Design for Congested RF Environments

by

Jooik Chung

and

Agis A. Iliadis

Electronics 2022, 11(7), 976; https://doi.org/10.3390/electronics11070976 - 22 Mar 2022

Viewed by 1560

Abstract

This work details the optimization and evaluation of a CMOS low-noise amplifier by developing a new algorithm for the

g_{m} / I_{D}

approach and combining with a modified figure of merit index method. The amplifier includes on-chip matching elements (such as [...] Read more.

This work details the optimization and evaluation of a CMOS low-noise amplifier by developing a new algorithm for the

g_{m} / I_{D}

approach and combining with a modified figure of merit index method. The amplifier includes on-chip matching elements (such as IC inductors) for resonance at the targeted frequencies. The simulation results of the optimized LNA model showed scattering parameter

S_{21}

= 19.91 dB, noise figure NF = 3.54 dB and excellent linearity for third-order intermodulation parameter IIP3 = 5.89 dBm for the targeted frequency of

f_{0}

= 2.4 GHz. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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Open AccessArticle

Improving Characteristics of LUT-Based Three-Block Mealy FSMs’ Circuits

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Electronics 2022, 11(6), 950; https://doi.org/10.3390/electronics11060950 - 18 Mar 2022

Cited by 2 | Viewed by 1369

Abstract

One of the very important problems connected with FPGA-based design is reducing the hardware amount in implemented circuits. In this paper, we discuss the implementation of Mealy finite state machines (FSMs) by circuits consisting of look-up tables (LUT). A method is proposed to [...] Read more.

One of the very important problems connected with FPGA-based design is reducing the hardware amount in implemented circuits. In this paper, we discuss the implementation of Mealy finite state machines (FSMs) by circuits consisting of look-up tables (LUT). A method is proposed to reduce the LUT count of three-block circuits of Mealy FSMs. The method is based on finding a partition of set of internal states by classes of compatible states. To reduce the LUT count, we propose a special kind of state code, named complex state codes. The complex codes include two parts. The first part includes the binary codes of a state as the element of some partition class. The second part consists of the code of corresponding partition class. Using complex state codes allows obtaining FPGA-based FSM circuits with exactly four logic blocks. If some conditions hold, then any FSM function from the first and second blocks is implemented by a single LUT. The third level is represented as a network of multiplexers. These multiplexers generate either additional variable encoding collections of outputs or input memory functions. The fourth level generates FSM outputs. An example of synthesis and experimental results is shown and discussed. The experiments prove that the proposed approach allows reducing hardware compared to such methods as auto and one-hot of Vivado, JEDI. Further, the proposed approach produces circuits with fewer LUTs than for three-level Mealy FSMs based on joint use of several methods of structural decomposition. The experiments show that our approach allows reducing the LUT counts on average from 11 to 77 percent. As the complexity of an FSM increases, the gain from the application of the proposed method grows; the same is true for both the FSM performance and power consumption. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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Open AccessArticle

Low-Cost Data Acquisition System for Solar Thermal Collectors

by

Orestis Panagopoulos

and

Athanassios A. Argiriou

Electronics 2022, 11(6), 934; https://doi.org/10.3390/electronics11060934 - 17 Mar 2022

Cited by 2 | Viewed by 2280

Abstract

Solar thermal collectors are among the most popular renewable energy research subjects. Automatic Data Acquisition Systems (ADAS) have greatly facilitated their experimental testing, but their high cost is a drawback. In this paper, we present the design and testing of a decentralized, low-cost [...] Read more.

Solar thermal collectors are among the most popular renewable energy research subjects. Automatic Data Acquisition Systems (ADAS) have greatly facilitated their experimental testing, but their high cost is a drawback. In this paper, we present the design and testing of a decentralized, low-cost alternative ADAS based on the ESP32 microcontroller and on open-source software. The proposed system can be used for the experimental characterization of water (or air) operated solar thermal collectors in accordance with the ISO 9806:2017 requirements, but it is also compatible with sensors with lower specifications. We present also its performance results when applied for the testing of a solar thermal collector. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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Open AccessArticle

A New Fully Closed-Loop, High-Precision, Class-AB CCII for Differential Capacitive Sensor Interfaces

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and

Alessandro Trifiletti

Electronics 2022, 11(6), 903; https://doi.org/10.3390/electronics11060903 - 15 Mar 2022

Viewed by 1376

Abstract

The use of capacitive sensors has advantages in different industrial applications due to their low cost and low-temperature dependence. In this sense, the current-mode approach by means of second-generation current conveyors (CCIIs) allows for improvements in key features, such as sensitivity and resolution. [...] Read more.

The use of capacitive sensors has advantages in different industrial applications due to their low cost and low-temperature dependence. In this sense, the current-mode approach by means of second-generation current conveyors (CCIIs) allows for improvements in key features, such as sensitivity and resolution. In this paper, a novel architecture of CCII for differential capacitive sensor interfaces is presented. The proposed topology shows a closed-loop configuration for both the voltage and the current buffer, thus leading to better interface impedances at terminals X and Z. Moreover, a low power consumption of 600 µW was obtained due to class-AB biasing of both buffers, and the inherent drawbacks in terms of linearity under the mismatch of class-AB buffering are overcome by its closed-loop configuration. The advantages of the novel architecture are demonstrated by circuit analysis and simulations; in particular, very good robustness under process, supply voltage and temperature variations and mismatches were obtained due to the closed-loop approach. The CCII was also used to design a capacitive sensor interface in integrated CMOS technology, where it was possible to achieve a sensitivity of 2.34 nA/fF, with a full-scale sensor variation of 8 pF and a minimum detectable capacitance difference of 40 fF. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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Open AccessFeature PaperArticle

Bridging the Gap between Physical and Circuit Analysis for Variability-Aware Microwave Design: Modeling Approaches

by

Simona Donati Guerrieri

,

Chiara Ramella

,

Eva Catoggio

and

Fabrizio Bonani

Electronics 2022, 11(6), 860; https://doi.org/10.3390/electronics11060860 - 09 Mar 2022

Cited by 6 | Viewed by 1766

Abstract

Process-induced variability is a growing concern in the design of analog circuits, and in particular for monolithic microwave integrated circuits (MMICs) targeting the 5G and 6G communication systems. The RF and microwave (MW) technologies developed for the deployment of these communication systems exploit [...] Read more.

Process-induced variability is a growing concern in the design of analog circuits, and in particular for monolithic microwave integrated circuits (MMICs) targeting the 5G and 6G communication systems. The RF and microwave (MW) technologies developed for the deployment of these communication systems exploit devices whose dimension is now well below 100 nm, featuring an increasing variability due to the fabrication process tolerances and the inherent statistical behavior of matter at the nanoscale. In this scenario, variability analysis must be incorporated into circuit design and optimization, with ad hoc models retaining a direct link to the fabrication process and addressing typical MMIC nonlinear applications like power amplification and frequency mixing. This paper presents a flexible procedure to extract black-box models from accurate physics-based simulations, namely TCAD analysis of the active devices and EM simulations for the passive structures, incorporating the dependence on the most relevant fabrication process parameters. We discuss several approaches to extract these models and compare them to highlight their features, both in terms of accuracy and of ease of extraction. We detail how these models can be implemented into EDA tools typically used for RF and MMIC design, allowing for fast and accurate statistical and yield analysis. We demonstrate the proposed approaches extracting the black-box models for the building blocks of a power amplifier in a GaAs technology for X-band applications. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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Open AccessFeature PaperArticle

28-GHz CMOS Direct-Conversion RF Transmitter with Precise and Wide-Range Mismatch Calibration Techniques

by

Yongho Lee

,

Byeonghyeon Kim

and

Hyunchol Shin

Electronics 2022, 11(6), 840; https://doi.org/10.3390/electronics11060840 - 08 Mar 2022

Cited by 5 | Viewed by 2358

Abstract

A millimeter-wave direct-conversion radio-frequency (RF) transmitter requires precise in-/quadrature-phase (I/Q) mismatch calibration and dc offset cancellation to minimize image rejection ratio (IRR) and LO feedthrough (LOFT) for ensuring satisfactory output spectral purity. We present a 28-GHz CMOS RF transmitter with an improved calibration [...] Read more.

A millimeter-wave direct-conversion radio-frequency (RF) transmitter requires precise in-/quadrature-phase (I/Q) mismatch calibration and dc offset cancellation to minimize image rejection ratio (IRR) and LO feedthrough (LOFT) for ensuring satisfactory output spectral purity. We present a 28-GHz CMOS RF transmitter with an improved calibration technique for fifth generation (5G) wireless communication applications. The RF transmitter comprises a baseband amplifier, quadrature up-conversion mixer, power amplifier driver, and quadrature LO generator. The I/Q amplitude mismatch is calibrated by tuning the gate biases of the switching stage FETs of the mixer, the I/Q phase mismatch is calibrated by tuning the varactor capacitances at the LC load of LO buffer, and the dc offset is cancelled by tuning the body voltages of the differential-pair FETs at the baseband amplifier. The proposed technique provides precise calibration accuracy by employing mV-resolution tuning voltage generation via 6-bit voltage digital-to-analog converters. It also covers wide calibration range while minimizing the impact on the circuit’s bias point and dissipated current during calibration. Implemented in a 65 nm CMOS process, the RF transmitter integrated circuit shows output-referred 1 dB compression power of +6.5 dBm, saturated output power of +12.6 dBm, and an operating band of 27.5–29.3 GHz while demonstrating satisfactory performances of −55.9 dBc of IRR and −36.8 dBc of LOFT. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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Open AccessArticle

Fast Design Space Exploration and Multi-Objective Optimization of Wide-Band Noise-Canceling LNAs

by

Karim Elmeligy

and

Hesham Omran

Electronics 2022, 11(5), 816; https://doi.org/10.3390/electronics11050816 - 05 Mar 2022

Cited by 5 | Viewed by 2752

Abstract

Design optimization of RF low-noise amplifiers (LNAs) remains a time-consuming and complex process. Iterations are needed to adjust impedance matching, gain, and noise figure (NF) simultaneously. The process can involve more iterations to adjust the non-linear behavior of the circuit which can be [...] Read more.

Design optimization of RF low-noise amplifiers (LNAs) remains a time-consuming and complex process. Iterations are needed to adjust impedance matching, gain, and noise figure (NF) simultaneously. The process can involve more iterations to adjust the non-linear behavior of the circuit which can be represented by the input-referred third-order intercept (IIP3). In this work, we present a variation-aware automated design and optimization flow for a wide-band noise-canceling LNA. We include the circuit non-linearity in the optimization flow without using a simulator in the loop. By describing the transistors using precomputed lookup tables (LUTs), a design database that contains 200,000 design points is generated in 3 s only without non-linearity computation and 10 s when non-linearity is taken into account. Using a gm/ID-based correct-by-construction design procedure, the generated design points automatically satisfy proper biasing, input matching, and gain matching requirements. The generated database enables the designer to visualize the design space and explore the design trade-offs. Moreover, multi-objective optimization across corners for a given set of specifications is applied to find the Pareto-optimal fronts of the design figures-of-merit. We demonstrate the presented flow using two design examples in a 65 nm process and the results are verified using Cadence Spectre. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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Open AccessFeature PaperArticle

A Tunable Microstrip Bandpass Filter with Two Concurrently Tuned Transmission Zeros

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Electronics 2022, 11(5), 807; https://doi.org/10.3390/electronics11050807 - 04 Mar 2022

Cited by 1 | Viewed by 2335

Abstract

In this paper, an electrically small tunable microstrip bandpass filter with two concurrently tuned transmission zeros (TZs) is presented. The filter consists of two coupled resonators and varactors as tuning elements. An application of a multipath coupling network results in TZs on both [...] Read more.

In this paper, an electrically small tunable microstrip bandpass filter with two concurrently tuned transmission zeros (TZs) is presented. The filter consists of two coupled resonators and varactors as tuning elements. An application of a multipath coupling network results in TZs on both sides of the passband. The filter controlled by a single voltage has a wide tuning range from 370 MHz to 800 MHz and a low insertion loss ranging from 1.9 dB to 3.4 dB. To achieve high attenuation in the stopband, two sections of the designed filter were cascaded. Both one-section and two-section filters were validated by measurements. The obtained results are in a very good agreement with simulations. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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Open AccessArticle

An Accurate Bandgap Voltage Reference Ready-Indicator

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Electronics 2022, 11(5), 723; https://doi.org/10.3390/electronics11050723 - 26 Feb 2022

Viewed by 2376

Abstract

An accurate indication that the bandgap voltage reference (BGR) circuit is settled on its nominal value is essential in analog or mixed signal systems. In this paper, a generic method for accurate bandgap voltage reference (BGR) Ready-Indication (RI) is proposed. A RI signal [...] Read more.

An accurate indication that the bandgap voltage reference (BGR) circuit is settled on its nominal value is essential in analog or mixed signal systems. In this paper, a generic method for accurate bandgap voltage reference (BGR) Ready-Indication (RI) is proposed. A RI signal shows that the BGR operates correctly but also is used to enable PoR circuits when those employ the bandgap voltage to generate the required thresholds. In many low power applications, several systems are periodically switched on and off to save power and to increase battery life. In such systems, most circuits must remain off, while BGR is not in ready mode, saving battery energy. In other critical applications, the Ready-Indicator can ensure that critical systems can be set on and the reference voltage is within the operating range. In this paper, the introduced methodology is applied to different reference voltage generators. Initially, a BGR with Ready-Indication is presented extensively, including post-layout simulations results in 22 nm, while thereafter, the study of this method is extended in other BGR topologies. The universality of the proposed method is proved by verifying the operation in all the BGR topologies under study covering designs in 22 nm and 65 nm and with supply voltages 1.8 V, 1 V, 0.55 V. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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Open AccessArticle

Run-Time Thermal Management for Lifetime Optimization in Low-Power Designs

by

Daniele Rossi

and

Vasileios Tenentes

Electronics 2022, 11(3), 411; https://doi.org/10.3390/electronics11030411 - 29 Jan 2022

Viewed by 1504

Abstract

In this paper, the magnitude of the temperature and stress variability of dynamic voltage and frequency scaling (DVFS) designs is analyzed, and their impact on the bias temperature instability (BTI) degradation and lifetime of DVFS designs is assessed. For this purpose, a design-time [...] Read more.

In this paper, the magnitude of the temperature and stress variability of dynamic voltage and frequency scaling (DVFS) designs is analyzed, and their impact on the bias temperature instability (BTI) degradation and lifetime of DVFS designs is assessed. For this purpose, a design-time evaluation framework for BTI degradation was developed, which considered the statistical workload and die temperature profiles of DVFS operating modes. The performed analysis showed that, together with high stress variability, DVFS designs exhibited even higher temperature variability, depending on the workload and utilized operating modes, and the impact of temperature variability on lifetime could be up to 2× higher than that due to stress. In order to account for temperature variability on aging detrimental effects, a thermal management run-time system is proposed that honors the desired lifetime constraints by properly selecting temperature constraints that govern the utilized operating modes. The proposed run-time system was applied on the largest benchmark circuit from the IWLS 2005 suite, Ethernet circuit, synthesized with the 32 nm CMOS technology. The proposed system was verified to obtain lifetime and performance estimation and the trade-off with up to 35.8% and 26.3% higher accuracy, respectively, when compared to a system that ignores temperature variability and accounts for average temperature only. The proposed framework can be suitably utilized for tuning run-time throttling policies of low-power designs, thus allowing designers to optimize lifetime–performance trade-offs, depending on the requirements mandated by specific applications and operating environments. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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Realization of an Electronically Tunable Resistor-Less Floating Inductance Simulator Using VCII

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Electronics 2022, 11(3), 312; https://doi.org/10.3390/electronics11030312 - 19 Jan 2022

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Abstract

In this paper, a new implementation of an electronically tunable resistor-less floating inductance simulator using a second-generation voltage conveyor (VCII) is presented. The proposed circuit is resistor-free (benefiting from the intrinsic resistors at the Y terminals of the employed VCIIs) and composed of [...] Read more.

In this paper, a new implementation of an electronically tunable resistor-less floating inductance simulator using a second-generation voltage conveyor (VCII) is presented. The proposed circuit is resistor-free (benefiting from the intrinsic resistors at the Y terminals of the employed VCIIs) and composed of three VCIIs and a single grounded capacitor. Using a control current (I_con), the value of impedance at the Y terminal of the VCII is varied, whereby the value of the simulated inductance is tuned. The proposed circuit is designed at a transistor level using 0.18 µm TSMC CMOS parameters and ±0.9 V supply voltage. PSpice simulations are carried out to confirm the effectiveness of the proposed circuit. For a range of Icon from 0 µA to 50 µA, the value of the simulated L can be varied from −576 µH to −324 µH and from +316 µH to +576 µH for negative and positive simulators, respectively, in the frequency range of 100 kHz–3 MHz. Favorably, the value of the series resistance remains below 76 Ω. Simulation results show an error value below 4.8% and power consumption variation is from 1.64 mW to 1.92 mW. Moreover, application of the proposed circuit as a standard band-pass RLC filter is also included. Full article

(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)

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