Ultra-Low-Power ICs for the Internet of Things

A special issue of Journal of Low Power Electronics and Applications (ISSN 2079-9268).

Deadline for manuscript submissions: closed (30 October 2022) | Viewed by 49591

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Guest Editor
Department of Electrical and Computer Engineering, National University of Singapore (NUS), Singapore 117583, Singapore
Interests: energy-efficient integrated circuit design; mostly-digital/synthesizable interfaces; ultra low power ICs for the Internet Of Things (IoT); ultra-low-voltage and voltage scalable ICs; electromagnetic compatibility issues at IC level
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Special Issue Information

Dear Colleagues,

Ultra-low-voltage/power analog and digital IC, powered by energy harvesters, faces the challenges of small area occupation, low design effort, and technology/design portability, which are needed in this Internet-of-Things (IoT) era that, in itself, has experienced exponential growth in relation to interconnected sensor nodes.

In this framework, the aim of this Special Issue is to attract original research outcomes related to the design and application of ultra-low-voltage/power, digital-based and fully synthesizable ICs.

The topics of this Special Issue include but are not limited to:  

  • Ultra-low-power interfaces for the Internet of Things: energy-efficient and power/voltage scalable, analog, mixed-signal IC;
  • Inverter- and digital-based design methodologies of ultra-low power ICs;
  • IC solution for ultra-low-voltage, energy and standby power consumption systems;
  • Automated design methodology to fasten the time-to-market;
  • Energy harvesting and power management circuit for IoT devices;
  • Ultra-low-power/voltage ICs for instrumentation and communication applications.

Dr. Orazio Aiello
Guest Editor

Manuscript Submission Information

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Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 1800 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • Ultra-Low Power/Voltage ICs for IoT applications 
  • Advancements in energy-aware design techniques       
  • Ultra-low power front-end electronics 
  • Energy efficient ICs 
  • Digital-based design methodologies 
  • Ultra-low power sensors and energy-neutral devices  
  • Energy harvesting and power management circuit 

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Published Papers (15 papers)

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Editorial

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2 pages, 194 KiB  
Editorial
Ultra-Low-Power ICs for the Internet of Things
by Orazio Aiello
J. Low Power Electron. Appl. 2023, 13(2), 38; https://doi.org/10.3390/jlpea13020038 - 26 May 2023
Cited by 1 | Viewed by 1345
Abstract
The collection of research works in this Special Issue focuses on Ultra-Low-Power (ULP) Integrated Circuits (ICs) operating under a tight budget of power as a criterion to build electronic devices relying less and less on batteries [...] Full article
(This article belongs to the Special Issue Ultra-Low-Power ICs for the Internet of Things)

Research

Jump to: Editorial

17 pages, 6975 KiB  
Article
A 1.1 V 25 ppm/°C Relaxation Oscillator with 0.045%/V Line Sensitivity for Low Power Applications
by Yizhuo Liao and Pak Kwong Chan
J. Low Power Electron. Appl. 2023, 13(1), 15; https://doi.org/10.3390/jlpea13010015 - 07 Feb 2023
Cited by 3 | Viewed by 2009
Abstract
A fully-integrated CMOS relaxation oscillator, realized in 40 nm CMOS technology, is presented. The oscillator includes a stable two-transistor based voltage reference without an operational amplifier, a simple current reference employing the temperature-compensated composite resistor, and the approximated complementary to absolute temperature (CTAT) [...] Read more.
A fully-integrated CMOS relaxation oscillator, realized in 40 nm CMOS technology, is presented. The oscillator includes a stable two-transistor based voltage reference without an operational amplifier, a simple current reference employing the temperature-compensated composite resistor, and the approximated complementary to absolute temperature (CTAT) delay-based comparators compensate for the approximated proportional to absolute temperature (PTAT) delay arising from the leakage currents in the switches. This relaxation oscillator is designed to output a square wave with a frequency of 64 kHz in a duty cycle of 50% at a 1.1 V supply. The simulation results demonstrated that the circuit can generate a square wave, with stable frequency, against temperature and supply variation, while exhibiting low current consumption. For the temperature range from −20 °C to 80 °C at a 1.1 V supply, the oscillator’ output frequency achieved a temperature coefficient (T.C.) of 12.4 ppm/°C in a typical corner in one sample simulation. For a 200-sample Monte Carlo simulation, the obtained T.C. is 25 ppm/°C. Under typical corners and room temperatures, the simulated line sensitivity is 0.045%/V with the supply from 1.1 V to 1.6 V, and the dynamic current consumption is 552 nA. A better figure-of-merit (FoM), which equals 0.129%, is displayed when compared to the representative prior-art works. Full article
(This article belongs to the Special Issue Ultra-Low-Power ICs for the Internet of Things)
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15 pages, 888 KiB  
Article
Wideband Cascaded and Stacked Receiver Front-Ends Employing an Improved Clock-Strategy Technique
by Arash Abbasi and Frederic Nabki
J. Low Power Electron. Appl. 2023, 13(1), 14; https://doi.org/10.3390/jlpea13010014 - 02 Feb 2023
Cited by 1 | Viewed by 1644
Abstract
A wideband cascaded receiver and a stacked receiver using an improved clock strategy are proposed to support the software-defined radio (SDR). The improved clock strategy reduces the number of mixer switches and the number of LO clock paths required to drive the mixer [...] Read more.
A wideband cascaded receiver and a stacked receiver using an improved clock strategy are proposed to support the software-defined radio (SDR). The improved clock strategy reduces the number of mixer switches and the number of LO clock paths required to drive the mixer switches. This reduces the dynamic power consumption. The cascaded receiver includes an inverter-based low-noise transconductance amplifier (LNTA) using a feed-forward technique to enhance the noise performance; a passive mixer; and an inverter-based transimpedance amplifier (TIA). The stacked receiver architecture is used to reduce the power consumption by sharing the current between the LNTA and the TIA from a single supply. It utilizes a wideband LNTA with a capacitor cross-coupled (CCC) common-gate (CG) topology, a passive mixer to convert the RF current to an IF current, an active inductor (AI) and a 1/f noise-cancellation (NC) technique to improve the noise performance, and a TIA to convert the IF current to an IF voltage at the output. Both cascaded and stacked receivers are simulated in 22 nm CMOS technology. The cascaded receiver achieves a conversion-gain from 26 dB to 36 dB, a double-sideband noise-figure (NFDSB) from 1.4 dB to 3.9 dB, S11<10 dB and an IIP3 from 7.5 dBm to 10.5 dBm, over the RF operating band from 0.4 GHz to 12 GHz. The stacked receiver achieves a conversion-gain from 34.5 dB to 36 dB, a NFDSB from 4.6 dB to 6.2 dB, S11<10 dB, and an IIP3 from 21 dBm to 17.5 dBm, over the RF operating band from 2.2 GHz to 3.2 GHz. The cascaded receiver consumes 11 m from a 1 V supply voltage, while the stacked receiver consumes 2.4 m from a 1.2 V supply voltage. Full article
(This article belongs to the Special Issue Ultra-Low-Power ICs for the Internet of Things)
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18 pages, 1200 KiB  
Article
A Fully-Differential CMOS Instrumentation Amplifier for Bioimpedance-Based IoT Medical Devices
by Israel Corbacho, Juan M. Carrillo, José L. Ausín, Miguel Á. Domínguez, Raquel Pérez-Aloe and J. Francisco Duque-Carrillo
J. Low Power Electron. Appl. 2023, 13(1), 3; https://doi.org/10.3390/jlpea13010003 - 30 Dec 2022
Cited by 3 | Viewed by 2504
Abstract
The implementation of a fully-differential (FD) instrumentation amplifier (IA), based on indirect current feedback (ICF) and aimed to electrical impedance measurements in an Internet of Things (IoT) biomedical scenario, is presented. The IA consists of two FD transconductors, to process the input signal [...] Read more.
The implementation of a fully-differential (FD) instrumentation amplifier (IA), based on indirect current feedback (ICF) and aimed to electrical impedance measurements in an Internet of Things (IoT) biomedical scenario, is presented. The IA consists of two FD transconductors, to process the input signal and feed back the output signal, a summing stage, used to add both contributions and generate the correcting current feedback signal, and a common-mode feedback network, which controls the DC level at the output nodes of the circuit. The transconductors are formed by a voltage-to-current conversion resistor and two voltage buffers, which are based on a super source follower cell in order to improve the overall response of the circuit. As a result, a compact single-stage structure, suitable for achieving a high bandwidth and a low power consumption, is obtained. The FD ICF IA has been designed and fabricated in 180 nm CMOS technology to operate with a 1.8-V supply and provide a nominal gain of 4 V/V. Experimental results show a voltage gain of 3.78 ± 0.06 V/V, a BW of 5.83 MHz, a CMRR at DC around 70 dB, a DC current consumption of 266.4 μA and a silicon area occupation of 0.0304 mm2. Full article
(This article belongs to the Special Issue Ultra-Low-Power ICs for the Internet of Things)
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13 pages, 6200 KiB  
Article
All-Standard-Cell-Based Analog-to-Digital Architectures Well-Suited for Internet of Things Applications
by Ana Correia, Vítor Grade Tavares, Pedro Barquinha and João Goes
J. Low Power Electron. Appl. 2022, 12(4), 64; https://doi.org/10.3390/jlpea12040064 - 07 Dec 2022
Cited by 3 | Viewed by 1823
Abstract
In this paper, the most suited analog-to-digital (A/D) converters (ADCs) for Internet of Things (IoT) applications are compared in terms of complexity, dynamic performance, and energy efficiency. Among them, an innovative hybrid topology, a digital–delta (Δ) modulator (ΔM) ADC employing noise shaping (NS), [...] Read more.
In this paper, the most suited analog-to-digital (A/D) converters (ADCs) for Internet of Things (IoT) applications are compared in terms of complexity, dynamic performance, and energy efficiency. Among them, an innovative hybrid topology, a digital–delta (Δ) modulator (ΔM) ADC employing noise shaping (NS), is proposed. To implement the active building blocks, several standard-cell-based synthesizable comparators and amplifiers are examined and compared in terms of their key performance parameters. The simulation results of a fully synthesizable Digital-ΔM with NS using passive and standard-cell-based circuitry show a peak of 72.5 dB in the signal-to-noise and distortion ratio (SNDR) for a 113 kHz input signal and 1 MHz bandwidth (BW). The estimated FoMWalden is close to 16.2 fJ/conv.-step. Full article
(This article belongs to the Special Issue Ultra-Low-Power ICs for the Internet of Things)
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17 pages, 600 KiB  
Article
0.6-V 1.65-μW Second-Order Gm-C Bandpass Filter for Multi-Frequency Bioimpedance Analysis Based on a Bootstrapped Bulk-Driven Voltage Buffer
by Juan M. Carrillo and Carlos A. de la Cruz-Blas
J. Low Power Electron. Appl. 2022, 12(4), 62; https://doi.org/10.3390/jlpea12040062 - 30 Nov 2022
Cited by 6 | Viewed by 2469
Abstract
A bootstrapping technique used to increase the intrinsic voltage gain of a bulk-driven MOS transistor is described in this paper. The proposed circuit incorporates a capacitor and a cutoff transistor to be connected to the gate terminal of a bulk-driven MOS device, thus [...] Read more.
A bootstrapping technique used to increase the intrinsic voltage gain of a bulk-driven MOS transistor is described in this paper. The proposed circuit incorporates a capacitor and a cutoff transistor to be connected to the gate terminal of a bulk-driven MOS device, thus achieving a quasi-floating-gate structure. As a result, the contribution of the gate transconductance is cancelled out and the voltage gain of the device is correspondingly increased. The technique allows for implementing a voltage follower with a voltage gain much closer to unity as compared to the conventional bulk-driven case. This voltage buffer, along with a pseudo-resistor, is used to design a linearized transconductor. The proposed transconductance cell includes an economic continuous tuning mechanism that permits programming the effective transconductance in a range sufficiently wide to counteract the typical variations that process parameters suffer during fabrication. The transconductor has been used to implement a second-order Gm-C bandpass filter with a relatively high selectivity factor, suited for multi-frequency bioimpedance analysis in a very low-voltage environment. All the circuits have been designed in 180 nm CMOS technology to operate with a 0.6-V single-supply voltage. Simulated results show that the proposed technique allows for increasing the linearity and reducing the input-referred noise of the bootstrapped bulk-driven MOS transistor, which results in an improvement of the overall performance of the transconductor. The center frequency of the bandpass filter designed can be programmed in the frequency range from 6.5 kHz to 37.5 kHz with a power consumption ranging between 1.34 μW and 2.19 μW. The circuit presents an in-band integrated noise of 190.5 μVrms and is able to process signals of 110 mVpp with a THD below −40 dB, thus leading to a dynamic range of 47.4 dB. Full article
(This article belongs to the Special Issue Ultra-Low-Power ICs for the Internet of Things)
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24 pages, 1827 KiB  
Article
Hardware Solutions for Low-Power Smart Edge Computing
by Lucas Martin Wisniewski, Jean-Michel Bec, Guillaume Boguszewski and Abdoulaye Gamatié
J. Low Power Electron. Appl. 2022, 12(4), 61; https://doi.org/10.3390/jlpea12040061 - 25 Nov 2022
Cited by 6 | Viewed by 4023
Abstract
The edge computing paradigm for Internet-of-Things brings computing closer to data sources, such as environmental sensors and cameras, using connected smart devices. Over the last few years, research in this area has been both interesting and timely. Typical services like analysis, decision, and [...] Read more.
The edge computing paradigm for Internet-of-Things brings computing closer to data sources, such as environmental sensors and cameras, using connected smart devices. Over the last few years, research in this area has been both interesting and timely. Typical services like analysis, decision, and control, can be realized by edge computing nodes executing full-fledged algorithms. Traditionally, low-power smart edge devices have been realized using resource-constrained systems executing machine learning (ML) algorithms for identifying objects or features, making decisions, etc. Initially, this paper discusses recent advances in embedded systems that are devoted to energy-efficient ML algorithm execution. A survey of the mainstream embedded computing devices for low-power IoT and edge computing is then presented. Finally, CYSmart is introduced as an innovative smart edge computing system. Two operational use cases are presented to illustrate its power efficiency. Full article
(This article belongs to the Special Issue Ultra-Low-Power ICs for the Internet of Things)
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20 pages, 2089 KiB  
Article
Bridging the Gap between Design and Simulation of Low-Voltage CMOS Circuits
by Cristina Missel Adornes, Deni Germano Alves Neto, Márcio Cherem Schneider and Carlos Galup-Montoro
J. Low Power Electron. Appl. 2022, 12(2), 34; https://doi.org/10.3390/jlpea12020034 - 16 Jun 2022
Cited by 5 | Viewed by 3307
Abstract
This work proposes a truly compact MOSFET model that contains only four parameters to assist an integrated circuits (IC) designer in a design by hand. The four-parameter model (4PM) is based on the advanced compact MOSFET (ACM) model and was implemented in Verilog-A [...] Read more.
This work proposes a truly compact MOSFET model that contains only four parameters to assist an integrated circuits (IC) designer in a design by hand. The four-parameter model (4PM) is based on the advanced compact MOSFET (ACM) model and was implemented in Verilog-A to simulate different circuits designed with the ACM model in Verilog-compatible simulators. Being able to simulate MOS circuits through the same model used in a hand design benefits designers in understanding how the main MOSFET parameters affect the design. Herein, the classic CMOS inverter, a ring oscillator, a self-biased current source and a common source amplifier were designed and simulated using either the 4PM or the BSIM model. The four-parameter model was simulated in many sorts of circuits with very satisfactory results in the low-voltage cases. As the ultra-low-voltage (ULV) domain is expanding due to applications, such as the internet of things and wearable circuits, so is the use of a simplified ULV MOSFET model. Full article
(This article belongs to the Special Issue Ultra-Low-Power ICs for the Internet of Things)
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16 pages, 34204 KiB  
Article
A Standard-Cell-Based CMFB for Fully Synthesizable OTAs
by Francesco Centurelli, Riccardo Della Sala and Giuseppe Scotti
J. Low Power Electron. Appl. 2022, 12(2), 27; https://doi.org/10.3390/jlpea12020027 - 05 May 2022
Cited by 14 | Viewed by 3267
Abstract
In this paper, we propose a fully standard-cell-based common-mode feedback (CMFB) loop with an explicit voltage reference to improve the CMRR of pseudo-differential standard-cell-based amplifiers and to stabilize the dc output voltage. This latter feature allows robust biasing of operational transconductance amplifiers (OTAs) [...] Read more.
In this paper, we propose a fully standard-cell-based common-mode feedback (CMFB) loop with an explicit voltage reference to improve the CMRR of pseudo-differential standard-cell-based amplifiers and to stabilize the dc output voltage. This latter feature allows robust biasing of operational transconductance amplifiers (OTAs) based on a cascade of such stages. A detailed analysis of the CMFB is reported to both provide insight into circuit behavior and to derive useful design guidelines. The proposed CMFB is then exploited to build a fully standard-cell OTA suitable for automatic place and route. Simulation results referring to the standard-cell library of a commercial 130 nm CMOS process illustrated a differential gain of 28.3 dB with a gain-bandwidth product of 15.4 MHz when driving a 1.5 pF load capacitance. The OTA exhibits good robustness under PVT and mismatch variations and achieves state-of-the-art FOMs also thanks to the limited area footprint. Full article
(This article belongs to the Special Issue Ultra-Low-Power ICs for the Internet of Things)
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17 pages, 5431 KiB  
Article
A 0.5 V Sub-Threshold CMOS Current-Controlled Ring Oscillator for IoT and Implantable Devices
by Andrea Ballo, Salvatore Pennisi, Giuseppe Scotti and Chiara Venezia
J. Low Power Electron. Appl. 2022, 12(1), 16; https://doi.org/10.3390/jlpea12010016 - 09 Mar 2022
Cited by 6 | Viewed by 5933
Abstract
A current-controlled CMOS ring oscillator topology, which exploits the bulk voltages of the inverter stages as control terminals to tune the oscillation frequency, is proposed and analyzed. The solution can be adopted in sub-1 V applications, as it exploits MOSFETS in the subthreshold [...] Read more.
A current-controlled CMOS ring oscillator topology, which exploits the bulk voltages of the inverter stages as control terminals to tune the oscillation frequency, is proposed and analyzed. The solution can be adopted in sub-1 V applications, as it exploits MOSFETS in the subthreshold regime. Oscillators made up of 3, 5, and 7 stages designed in a standard 28-nm technology and supplied by 0.5 V, were simulated. By exploiting a programmable capacitor array, it allows a very large range of oscillation frequencies to be set, from 1 MHz to about 1 GHz, with a limited current consumption. Considering, for example, the five-stage topology, a nominal oscillation frequency of 516 MHz is obtained with an average power dissipation of about 29 µW. The solution provides a tuneable oscillation frequency, which can be adjusted from 360 to 640 MHz by controlling the bias current with a sensitivity of 0.43 MHz/nA. Full article
(This article belongs to the Special Issue Ultra-Low-Power ICs for the Internet of Things)
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19 pages, 1016 KiB  
Article
A Tree-Based Architecture for High-Performance Ultra-Low-Voltage Amplifiers
by Francesco Centurelli, Riccardo Della Sala, Pietro Monsurrò, Giuseppe Scotti and Alessandro Trifiletti
J. Low Power Electron. Appl. 2022, 12(1), 12; https://doi.org/10.3390/jlpea12010012 - 17 Feb 2022
Cited by 17 | Viewed by 3191
Abstract
In this paper, we introduce a novel tree-based architecture which allows the implementation of Ultra-Low-Voltage (ULV) amplifiers. The architecture exploits a body-driven input stage to guarantee a rail-to-rail input common mode range and body-diode loading to avoid Miller compensation, thanks to the absence [...] Read more.
In this paper, we introduce a novel tree-based architecture which allows the implementation of Ultra-Low-Voltage (ULV) amplifiers. The architecture exploits a body-driven input stage to guarantee a rail-to-rail input common mode range and body-diode loading to avoid Miller compensation, thanks to the absence of high-impedance internal nodes. The tree-based structure improves the CMRR of the proposed amplifier with respect to the conventional OTA architectures and allows achievement of a reasonable CMRR even at supply voltages as low as 0.3 V and without tail current generators which cannot be used in ULV circuits. The bias currents and the static output voltages of all the stages implementing the architecture are accurately set through the gate terminals of biasing transistors in order to guarantee good robustness against PVT variations. The proposed architecture and the implementing stages are investigated from an analytical point of view and design equations for the main performance metrics are presented to provide insight into circuit behavior. A 0.3 V supply voltage, subthreshold, ultra-low-power (ULP) OTA, based on the proposed tree-based architecture, was designed in a commercial 130 nm CMOS process. Simulation results show a dc gain higher than 52 dB with a gain-bandwidth product of about 35 kHz and reasonable values of CMRR and PSRR, even at such low supply voltages and considering mismatches. The power consumption is as low as 21.89 nW and state-of-the-art small-signal and large-signal FoMs are achieved. Extensive parametric and Monte Carlo simulations show the robustness of the proposed circuit to PVT variations and mismatch. These results confirm that the proposed OTA is a good candidate to implement ULV, ULP, high performance analog building blocks for directly harvested IoT nodes. Full article
(This article belongs to the Special Issue Ultra-Low-Power ICs for the Internet of Things)
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10 pages, 5108 KiB  
Article
A Novel Standard-Cell-Based Implementation of the Digital OTA Suitable for Automatic Place and Route
by Gaetano Palumbo and Giuseppe Scotti
J. Low Power Electron. Appl. 2021, 11(4), 42; https://doi.org/10.3390/jlpea11040042 - 28 Oct 2021
Cited by 14 | Viewed by 3350
Abstract
This paper presents a novel implementation of a digital-based Operational Transconductance Amplifier (OTA) which has been recently introduced in the technical literature as a fully digital alternative to the conventional differential pair to implement low voltage analog amplifiers and comparators. The proposed implementation [...] Read more.
This paper presents a novel implementation of a digital-based Operational Transconductance Amplifier (OTA) which has been recently introduced in the technical literature as a fully digital alternative to the conventional differential pair to implement low voltage analog amplifiers and comparators. The proposed implementation does not make use of resistors, floating gate resistors nor C-Muller elements and is made up of only digital gates usually available in the standard cell libraries. The resulting analog circuit schematic can be described using structural VHDL or Verilog languages and is suitable to be integrated in an automatic synthesis and place and route flow for digital circuits. The proposed digital-based amplifier has been implemented in a commercial 130 nm CMOS process by using an automatic place and route flow for layout generation starting from the Verilog netlist. Post layout simulations are presented to show the performance of the proposed circuit and compare it against the state of the art. Full article
(This article belongs to the Special Issue Ultra-Low-Power ICs for the Internet of Things)
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18 pages, 2018 KiB  
Article
A 1.9 nW, Sub-1 V, 542 pA/V Linear Bulk-Driven OTA with 154 dB CMRR for Bio-Sensing Applications
by Rafael Sanchotene Silva, Luis Henrique Rodovalho, Orazio Aiello and Cesar Ramos Rodrigues
J. Low Power Electron. Appl. 2021, 11(4), 40; https://doi.org/10.3390/jlpea11040040 - 20 Oct 2021
Cited by 10 | Viewed by 3005
Abstract
In this paper, a new technique for improvement on the DC voltage gain, while keeping the high-linearity in symmetrical operational transconductance amplifier (OTA) bulk-driven (BD) topology is proposed. These features are achieved by allying two topological solutions: enhanced forward-body-biasing self-cascode current mirror, and [...] Read more.
In this paper, a new technique for improvement on the DC voltage gain, while keeping the high-linearity in symmetrical operational transconductance amplifier (OTA) bulk-driven (BD) topology is proposed. These features are achieved by allying two topological solutions: enhanced forward-body-biasing self-cascode current mirror, and source degeneration. The proposed concept is demonstrated through simulations with typical process parameters and Monte Carlo analysis on nominal transistors of the CMOS TSMC 180 nm node. Results indicate that the proposed OTA can achieve a very small transconductance, only 542 pA/V while keeping a voltage gain higher than 60 dB, 150 dB CMRR, and high linearity of 475 mVpp (1% THD), consuming only 1.9 nW for a supply voltage of 0.6 V. This set of features allows the proposed OTA to be an attractive solution for implementing OTA-C filters for the analog front-ends in wearable devices and bio-sensing. Full article
(This article belongs to the Special Issue Ultra-Low-Power ICs for the Internet of Things)
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9 pages, 2162 KiB  
Article
0.5 V CMOS Inverter-Based Transconductance Amplifier with Quiescent Current Control
by Andrea Ballo, Salvatore Pennisi and Giuseppe Scotti
J. Low Power Electron. Appl. 2021, 11(4), 37; https://doi.org/10.3390/jlpea11040037 - 28 Sep 2021
Cited by 11 | Viewed by 3595
Abstract
A two-stage CMOS transconductance amplifier based on the inverter topology, suitable for very low supply voltages and exhibiting rail-to-rail output capability is presented. The solution consists of the cascade of a noninverting and an inverting stage, both characterized by having only two complementary [...] Read more.
A two-stage CMOS transconductance amplifier based on the inverter topology, suitable for very low supply voltages and exhibiting rail-to-rail output capability is presented. The solution consists of the cascade of a noninverting and an inverting stage, both characterized by having only two complementary transistors between the supply rails. The amplifier provides class-AB operation with quiescent current control obtained through an auxiliary loop that utilizes the MOSFETs body terminals. Simulation results, referring to a commercial 28 nm bulk technology, show that the quiescent current of the amplifier can be controlled quite effectively, even adopting a supply voltage as low as 0.5 V. The designed solution consumes around 500 nA of quiescent current in typical conditions and provides a DC gain of around 51 dB, with a unity gain frequency of 1 MHz and phase margin of 70 degrees, for a parallel load of 1 pF and 1.5 MΩ. Settling time at 1% is 6.6 μs, and white noise is 125 nV/Hz. Full article
(This article belongs to the Special Issue Ultra-Low-Power ICs for the Internet of Things)
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17 pages, 3244 KiB  
Article
A New VCII Application: Sinusoidal Oscillators
by Vincenzo Stornelli, Gianluca Barile, Leonardo Pantoli, Massimo Scarsella, Giuseppe Ferri, Francesco Centurelli, Pasquale Tommasino and Alessandro Trifiletti
J. Low Power Electron. Appl. 2021, 11(3), 30; https://doi.org/10.3390/jlpea11030030 - 08 Jul 2021
Cited by 15 | Viewed by 3865
Abstract
The aim of this paper is to prove that, through a canonic approach, sinusoidal oscillators based on second-generation voltage conveyor (VCII) can be implemented. The investigation demonstrates the feasibility of the design results in a pair of new canonic oscillators based on negative [...] Read more.
The aim of this paper is to prove that, through a canonic approach, sinusoidal oscillators based on second-generation voltage conveyor (VCII) can be implemented. The investigation demonstrates the feasibility of the design results in a pair of new canonic oscillators based on negative type VCII (VCII). Interestingly, the same analysis shows that no canonic oscillator configuration can be achieved using positive type VCII (VCII+), since a single VCII+ does not present the correct port conditions to implement such a device. From this analysis, it comes about that, for 5-node networks, the two presented oscillator configurations are the only possible ones and make use of two resistors, two capacitors and a single VCII. Notably, the produced sinusoidal output signal is easily available through the low output impedance Z port of VCII, removing the need for additional voltage buffer for practical use, which is one of the main limitations of the current mode (CM) approach. The presented theory is substantiated by both LTSpice simulations and measurement results using the commercially available AD844 from Analog Devices, the latter being in a close agreement with the theory. Moreover, low values of THD are given for a wide frequency range. Full article
(This article belongs to the Special Issue Ultra-Low-Power ICs for the Internet of Things)
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