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3 pages, 178 KiB

Open AccessEditorial

Editorial for the Special Issue on Network on Chip (NoC) and Reconfigurable Systems

by Abdelkrim Zitouni

Micromachines 2023, 14(9), 1780; https://doi.org/10.3390/mi14091780 - 17 Sep 2023

Viewed by 753

Abstract

In a multiprocessor System-on-Chip (SoC), efficient communication between the associated processors has to be addressed at all levels of the system design to guarantee global interconnection [...] Full article

(This article belongs to the Special Issue Network on Chip (NoC) and Reconfigurable Systems)

Research

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17 pages, 2563 KiB

Open AccessArticle

Hybrid Optimization Algorithm Based on Double Particle Swarm in 3D NoC Mapping

by Juan Fang, Huayi Cai and Xin Lv

Micromachines 2023, 14(3), 628; https://doi.org/10.3390/mi14030628 - 09 Mar 2023

Cited by 4 | Viewed by 1237

Abstract

Increasing the number of cores on a chip is one way to solve the bottleneck of exponential growth but an excessive number of cores can lead to problems such as communication blockage and overheating of the chip. Currently, networks-on-chip (NoC) can offer an [...] Read more.

Increasing the number of cores on a chip is one way to solve the bottleneck of exponential growth but an excessive number of cores can lead to problems such as communication blockage and overheating of the chip. Currently, networks-on-chip (NoC) can offer an effective solution to the problem of the communication bottleneck within the chip. With current advancements in IC manufacturing technology, chips can now be 3D-stacked in order to increase chip throughput as well as reduce power consumption while reducing the area of the chip. Automating the mapping of applications into 3D NoC topologies is an important new direction for research in the field of 3D NoC. In this paper, a 3D NoC partitioning algorithm is proposed, which can delineate the 3D NoC region to be mapped. Additionally, a double particle swarm optimization (DPSO) based heuristic algorithm is proposed, which can integrate the characteristics of neighborhood search and genetic algorithms, and thus solve the problem of a particle swarm algorithm falling into local optimal solutions. It is experimentally demonstrated that this DPSO-based hybrid optimization algorithm has a higher throughput rate and lower energy loss than the traditional heuristic algorithm. Full article

(This article belongs to the Special Issue Network on Chip (NoC) and Reconfigurable Systems)

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21 pages, 798 KiB

Open AccessArticle

PCCNoC: Packet Connected Circuit as Network on Chip for High Throughput and Low Latency SoCs

by Xinbing Zhou, Peng Hao and Dake Liu

Micromachines 2023, 14(3), 501; https://doi.org/10.3390/mi14030501 - 21 Feb 2023

Cited by 2 | Viewed by 1996

Abstract

Hundreds of processor cores or modules are integrated into a single chip. The traditional bus or crossbar is challenged by bandwidth, scalability, and silicon area, and cannot meet the requirements of high end applications. Network-on-chip (NoC) has become a very promising interconnection structure [...] Read more.

Hundreds of processor cores or modules are integrated into a single chip. The traditional bus or crossbar is challenged by bandwidth, scalability, and silicon area, and cannot meet the requirements of high end applications. Network-on-chip (NoC) has become a very promising interconnection structure because of its good scalability, predictable interconnect length and delay, high bandwidth, and reusability. However, the most available packet routing NoC may not be the perfect solution for high-end heterogeneous multi-core real-time systems-on-chip (SoC) because of the excessive latency and cache cost overhead. Moreover, circuit switching is limited by the scale, connectivity flexibility, and excessive overhead of fully connected systems. To solve the above problems and to meet the need for low latency, high throughput, and flexibility, this paper proposes PCCNoC (Packet Connected Circuit NoC), a low-latency and low-overhead NoC based on both packet switching (setting-up circuit) and circuit switching (data transmission on circuit), which offers flexible routing and zero overhead of data transmission latency, making it suitable for high-end heterogeneous multi-core real-time SoC at various system scales. Compared with typically available packet switched NoC, our PCCoC sees 242% improved performance and 97% latency reduction while keeping the silicon cost relatively low. Full article

(This article belongs to the Special Issue Network on Chip (NoC) and Reconfigurable Systems)

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24 pages, 6492 KiB

Open AccessArticle

A Model-Driven Platform for Dynamic Partially Reconfigurable Architectures: A Case Study of a Watermarking System

by Roukaya Dalbouchi, Chiraz Trabelsi, Majdi Elhajji and Abdelkrim Zitouni

Micromachines 2023, 14(2), 481; https://doi.org/10.3390/mi14020481 - 19 Feb 2023

Cited by 1 | Viewed by 1450

Abstract

The reconfigurable feature of FPGAs (Field-Programmable Gate Arrays) has made them a very attractive solution for implementing adaptive systems-on-chip. However, this implies additional design tasks to handle system reconfiguration and control, which increases design complexity. To address this issue, this paper proposes a [...] Read more.

The reconfigurable feature of FPGAs (Field-Programmable Gate Arrays) has made them a very attractive solution for implementing adaptive systems-on-chip. However, this implies additional design tasks to handle system reconfiguration and control, which increases design complexity. To address this issue, this paper proposes a model-driven design flow that guides the designer through the description of the different elements of a reconfigurable system. It is based on high-level modeling using an extended version of the MARTE (Modeling and Analysis of Real-Time and Embedded systems) UML (Unified Modeling Language) profile. Both centralized and decentralized reconfiguration decision-making solutions are possible with the proposed flow, allowing it to adapt to various reconfigurable systems constraints. It also integrates the IP-XACT standard (standard for the description of electronic Intellectual Properties), allowing the designer to easily target different technologies and commercial FPGAs by reusing both high-level models and actual IP-XACT hardware components. At the end of the flow, the implementation code is generated automatically from the high-level models. The proposed design flow was validated through a reconfigurable video watermarking application as a case study. Experimental results showed that the generated system allowed a good trade-off between resource usage, power consumption, execution time, and image quality compared to static implementations. This hardware efficiency was achieved in a very short time thanks to the design acceleration and automation offered by model-driven engineering. Full article

(This article belongs to the Special Issue Network on Chip (NoC) and Reconfigurable Systems)

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14 pages, 909 KiB

Open AccessArticle

Hotspots Reduction for GALS NoC Using a Low-Latency Multistage Packet Reordering Approach

by Zhenmin Li, Ruimin Shen, Maoxiang Yi, Yukun Song, Xiaolei Wang, Gaoming Du and Zhengfeng Huang

Micromachines 2023, 14(2), 444; https://doi.org/10.3390/mi14020444 - 14 Feb 2023

Cited by 3 | Viewed by 1335

Abstract

Traffic splitting enabled by Globally Asynchronous Locally Synchronous (GALS) Network-on-chip (NoC) brings multipath routing capability, which significantly increases link bandwidth at the cost of out-of-order packet delivery. Solving the packet reordering problem is one of the keys to ensure the quality of service [...] Read more.

Traffic splitting enabled by Globally Asynchronous Locally Synchronous (GALS) Network-on-chip (NoC) brings multipath routing capability, which significantly increases link bandwidth at the cost of out-of-order packet delivery. Solving the packet reordering problem is one of the keys to ensure the quality of service (QoS) for NoC. However, traditional packet reordering approaches rely on local reorder buffer, causing on-chip hotspots, which aggravates chip aging and even leads to interconnection failures. In this paper, we present a multistage packet reordering (MPR) approach, which cannot only reduce the transmission latency but also effectively reduces hotspots caused by local reordering. Specifically, we propose multistage reordering buffer (MRB) by reusing channel buffers for implementing MPR. Experimental results show that our proposed approach achieved improved thermal efficiency with reduced hardware resource consumption. Full article

(This article belongs to the Special Issue Network on Chip (NoC) and Reconfigurable Systems)

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22 pages, 6006 KiB

Open AccessArticle

Approximate Priority Hybrid 3DNoC Buffered-Bufferless Router

by Savvas Savva, Konstantinos Tatas and Costas Kyriacou

Micromachines 2023, 14(2), 335; https://doi.org/10.3390/mi14020335 - 28 Jan 2023

Cited by 1 | Viewed by 1125

Abstract

This paper introduces a novel 3D NoC router that combines buffered and bufferless routing with approximate priority comparison when deflecting flits. Our proposal is a modification of an asymmetrical router that is buffered in the z dimension ports and bufferless in the x [...] Read more.

This paper introduces a novel 3D NoC router that combines buffered and bufferless routing with approximate priority comparison when deflecting flits. Our proposal is a modification of an asymmetrical router that is buffered in the z dimension ports and bufferless in the x and y dimension ports. Flits that request output ports in the x and y dimensions are granted or deflected based on approximate, instead of accurate, priority comparison. Experimental results show that the proposed router, in addition to effectively combining the advantages of both buffered and bufferless routers, achieves additional performance and area gains due to the reduced logic required for approximate priority comparison in flit deflections. Experimental results using synthetic and realistic traffic show that the proposed router begins to saturate at a significantly higher injection rate than a bufferless router, but at a slightly lower injection rate than when using accurate priority comparison. Furthermore, the proposed router achieves higher clock frequencies and a reduced area compared to bufferles routers due to the simpler permutation network. The increased routing efficiency is shown to also translate to energy gains. Full article

(This article belongs to the Special Issue Network on Chip (NoC) and Reconfigurable Systems)

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12 pages, 2426 KiB

Open AccessArticle

Ring-Split: Deadlock-Free Routing Algorithm for Circulant Networks-on-Chip

by Aleksandr Y. Romanov, Nikolay M. Myachin, Evgenii V. Lezhnev, Alexander D. Ivannikov and Ahmed El-Mesady

Micromachines 2023, 14(1), 141; https://doi.org/10.3390/mi14010141 - 05 Jan 2023

Cited by 8 | Viewed by 1448

Abstract

This article considers the usage of circulant topologies as a promising deadlock-free topology for networks-on-chip (NoCs). A new high-level model, Newxim, for the exploration of NoCs with any topology is presented. Two methods for solving the problem of cyclic dependencies in circulant topologies, [...] Read more.

This article considers the usage of circulant topologies as a promising deadlock-free topology for networks-on-chip (NoCs). A new high-level model, Newxim, for the exploration of NoCs with any topology is presented. Two methods for solving the problem of cyclic dependencies in circulant topologies, which limit their applications for NoCs due to the increased possibility of deadlocks, are proposed. The first method of dealing with deadlocks is universal and applicable to any topology; it is based on the idea of bypassing blocked sections of the network on an acyclic subnetwork. The second method—Ring-Split—takes into account the features of circulant topologies. The results of high-level modeling and comparison of the peak throughput of NoCs for circulant and mesh topologies using deadlock-free routing algorithms are presented. It was shown that a new approach for routing in circulants (compared to mesh topology) shows up to 59% better network throughput with a uniform distribution of network load. Full article

(This article belongs to the Special Issue Network on Chip (NoC) and Reconfigurable Systems)

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26 pages, 1107 KiB

Open AccessArticle

Combined Distributed Shared-Buffered and Diagonally-Linked Mesh Topology for High-Performance Interconnect

by Charles Effiong, Gilles Sassatelli and Abdoulaye Gamatié

Micromachines 2022, 13(12), 2246; https://doi.org/10.3390/mi13122246 - 17 Dec 2022

Cited by 3 | Viewed by 1932

Abstract

Networks-on-Chip (NoCs) have become the de-facto on-chip interconnect for multi/manycore systems. A typical NoC router is made up of buffers used to store packets that are unable to advance to their desired destination. However, buffers consume significant power/area and are often underutilized, especially [...] Read more.

Networks-on-Chip (NoCs) have become the de-facto on-chip interconnect for multi/manycore systems. A typical NoC router is made up of buffers used to store packets that are unable to advance to their desired destination. However, buffers consume significant power/area and are often underutilized, especially in cases of applications with non-uniform traffic patterns thus leading to performance degradation for such applications. To improve network performance, the Roundabout NoC (R-NoC) concept is considered. R-NoC is inspired by real-life multi-lane traffic roundabouts and consists of lanes that are shared by multiple input/output ports to maximize buffering resource utilization. R-NoC relies on router-internal adaptive routing that decides the lane path based on back pressure. Back pressure makes it possible to assess lane utilization and route packets accordingly. This is made possible thanks to the use of elastic buffers for control flow, a clever type of handshaking in a way similar to asynchronous circuits. Another prominent feature of R-NoC is that internal routing and arbitration are completely distributed which allows for significant freedom in deciding internal router topology and parameters. This work leverages this property and proposes novel yet unexplored configurations for which an in-depth evaluation of corresponding implementations on 45 nm CMOS technology is given. Each configuration is evaluated performance and power-wise on both synthetic and real application traffic. Several R-NoC configurations are identified and demonstrated to provide very significant performance improvements over standard mesh configurations and a typical input-buffered router, without compromising area and power consumption. Exploiting the distributed nature of R-NoC routers, a diagonally-linked configuration is then proposed which incurs moderate area overhead and features yet better performance and energy efficiency. Full article

(This article belongs to the Special Issue Network on Chip (NoC) and Reconfigurable Systems)

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14 pages, 8271 KiB

Open AccessArticle

Synchronization of Chaotic Systems and Its Application in Security Terminal Sensing Node of Internet of Things

by Yi-You Hou

Micromachines 2022, 13(11), 1993; https://doi.org/10.3390/mi13111993 - 17 Nov 2022

Cited by 7 | Viewed by 1513

Abstract

Recently, with the rapid development of data and information, it has become necessary to establish secure communications and appropriate security services to ensure a secure information exchange process. Therefore, to protect the privacy and confidentiality of private data, in this research, we use [...] Read more.

Recently, with the rapid development of data and information, it has become necessary to establish secure communications and appropriate security services to ensure a secure information exchange process. Therefore, to protect the privacy and confidentiality of private data, in this research, we use the Lorenz chaotic system to generate chaotic signals and apply them to the encryption of the communication of the Internet of Things (IoT) terminal sensor nodes. In addition, we design a simple proportional–integral–derivative (PID) controller and a quasi-sliding mode controller (QSMC) to synchronize the master-slave chaotic systems for decrypting the signals. Then, we encrypt the environmental signals measured from the IoT node at the transmitting side (master) and send them to the receiving side (slave). After the receiving side receives the encrypted signals, it decrypts them with the PID controller. Thus, the security of IoT information can be assured and realized. Full article

(This article belongs to the Special Issue Network on Chip (NoC) and Reconfigurable Systems)

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