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9 pages, 4157 KiB

Open AccessCommunication

Investigation of Erase Cycling Induced Joint Dummy Cell Disturbance in Dual-Deck 3D NAND Flash Memory

by Kaikai You, Lei Jin, Jianquan Jia and Zongliang Huo

Micromachines 2023, 14(10), 1916; https://doi.org/10.3390/mi14101916 - 09 Oct 2023

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To satisfy the increasing demands for more word-line (WL) layers, the dual-deck even triple-deck architecture has emerged in 3D NAND Flash. However, the new reliability issues that occurred at the joint region of two decks became a severe challenge for developing multiple-deck technology. [...] Read more.

To satisfy the increasing demands for more word-line (WL) layers, the dual-deck even triple-deck architecture has emerged in 3D NAND Flash. However, the new reliability issues that occurred at the joint region of two decks became a severe challenge for developing multiple-deck technology. This work reported an abnormal reliability issue introduced by erasing disturbance of the dummy WLs at the joint region (Joint-DMYs) under multiple cycling. More specifically, after several erase cycling stresses, the increasing joint-DMY’s threshold voltage (Vt) due to the operational stress will finally result in additional disturbance to the adjacent data WLs. In this paper, we proposed this disturbance during erase originates from the backward injected electrons through FN tunneling based on our TCAD simulation result. Moreover, we also proposed an optimal erase scheme to reduce the backward electron injection and suppress the abnormal joint-DMY disturbance during the erase cycling. Full article

(This article belongs to the Special Issue Advances in Emerging Nonvolatile Memory, Volume II)

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8 pages, 3488 KiB

Open AccessCommunication

Investigation of the Connection Schemes between Decks in 3D NAND Flash

by Jianquan Jia, Lei Jin, Kaikai You and Anyi Zhu

Micromachines 2023, 14(9), 1779; https://doi.org/10.3390/mi14091779 - 17 Sep 2023

Viewed by 1097

Abstract

Dual-deck stacking technology is an effective solution for solving the contradiction between the demand for increasing storage layers and the challenge of the deep hole etching process in 3D NAND flash. The connection scheme between decks is a key technology for the dual-deck [...] Read more.

Dual-deck stacking technology is an effective solution for solving the contradiction between the demand for increasing storage layers and the challenge of the deep hole etching process in 3D NAND flash. The connection scheme between decks is a key technology for the dual-deck structure. It has become one of the necessary techniques for 3D NAND flash storage density improvement. This article mainly studies the impact of connection schemes between decks on cell reliability. Based on experimental data and simulation analysis, unfavorable effects were found as the gate channeling the breakdown and data retention characteristics of the top cells in the lower deck deteriorated due to the local electric field enhancement in the connection scheme without a poly-plug. This mainly contributed to the structural change of these cells within process impact. They will suffer secondary etching during the upper deck channel etching process due to alignment issues between the upper and lower decks. In another scheme with a poly-plug connection between decks, the saturation current of the channel decreased and the current variation increased. The fundamental cause of the current anomaly is that the Poly-plug has a certain shielding effect on channel inversion and the weak inversion region becomes a bottleneck for the channel current. The increase in variation is due to the shielding effect differences in the different structures of the poly-plug. Therefore, for the connection scheme without a poly-plug, the article proposes to improve device reliability by increasing the oxide thickness between decks and setting the top cells of the lower decks to be virtual cells. For the connection scheme with a poly-plug, the plug‘s N-type doping scheme is proposed to avoid the current dropping anomaly. Full article

(This article belongs to the Special Issue Advances in Emerging Nonvolatile Memory, Volume II)

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10 pages, 9790 KiB

Open AccessArticle

Design Strategies of 40 nm Split-Gate NOR Flash Memory Device for Low-Power Compute-in-Memory Applications

by Chan-Gi Yook, Jung Nam Kim, Yoon Kim and Wonbo Shim

Micromachines 2023, 14(9), 1753; https://doi.org/10.3390/mi14091753 - 07 Sep 2023

Viewed by 1397

Abstract

The existing von Neumann architecture for artificial intelligence (AI) computations suffers from excessive power consumption and memory bottlenecks. As an alternative, compute-in-memory (CIM) technology has been emerging. Among various CIM device candidates, split-gate NOR flash offers advantages such as a high density and [...] Read more.

The existing von Neumann architecture for artificial intelligence (AI) computations suffers from excessive power consumption and memory bottlenecks. As an alternative, compute-in-memory (CIM) technology has been emerging. Among various CIM device candidates, split-gate NOR flash offers advantages such as a high density and low on-state current, enabling low-power operation, and benefiting from a high level of technological maturity. To achieve high energy efficiency and high accuracy in CIM inference chips, it is necessary to optimize device design by targeting low power consumption at the device level and surpassing baseline accuracy at the system level. In split-gate NOR flash, significant factors that can cause CIM inference accuracy drop are the device conductance variation, caused by floating gate charge variation, and a low on-off current ratio. Conductance variation generally has a trade-off relationship with the on-current, which greatly affects CIM dynamic power consumption. In this paper, we propose strategies for designing optimal devices by adjusting oxide thickness and other structural parameters. As a result of setting T_ox,FG to 13.4 nm, T_IPO to 4.6 nm and setting other parameters to optimal points, the design achieves erase on-current below 2 μA, program on-current below 10 pA, and off-current below 1 pA, while maintaining an inference accuracy of over 92%. Full article

(This article belongs to the Special Issue Advances in Emerging Nonvolatile Memory, Volume II)

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10 pages, 2605 KiB

Open AccessArticle

Simulation of a Fully Digital Computing-in-Memory for Non-Volatile Memory for Artificial Intelligence Edge Applications

by Hongyang Hu, Chuancai Feng, Haiyang Zhou, Danian Dong, Xiaoshan Pan, Xiwei Wang, Lu Zhang, Shuaiqi Cheng, Wan Pang and Jing Liu

Micromachines 2023, 14(6), 1175; https://doi.org/10.3390/mi14061175 - 31 May 2023

Cited by 1 | Viewed by 1308

Abstract

In recent years, digital computing in memory (CIM) has been an efficient and high-performance solution in artificial intelligence (AI) edge inference. Nevertheless, digital CIM based on non-volatile memory (NVM) is less discussed for the sophisticated intrinsic physical and electrical behavior of non-volatile devices. [...] Read more.

In recent years, digital computing in memory (CIM) has been an efficient and high-performance solution in artificial intelligence (AI) edge inference. Nevertheless, digital CIM based on non-volatile memory (NVM) is less discussed for the sophisticated intrinsic physical and electrical behavior of non-volatile devices. In this paper, we propose a fully digital non-volatile CIM (DNV-CIM) macro with compressed coding look-up table (LUT) multiplier (CCLUTM) using the 40 nm technology, which is highly compatible with the standard commodity NOR Flash memory. We also provide a continuous accumulation scheme for machine learning applications. When applied to a modified ResNet18 network trained under the CIFAR-10 dataset, the simulations indicate that the proposed CCLUTM-based DNV-CIM can achieve a peak energy efficiency of 75.18 TOPS/W with 4-bit multiplication and accumulation (MAC) operations. Full article

(This article belongs to the Special Issue Advances in Emerging Nonvolatile Memory, Volume II)

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10 pages, 2521 KiB

Open AccessCommunication

A Novel Program Scheme for Z-Interference Improvement in 3D NAND Flash Memory

by Jianquan Jia, Lei Jin, Xinlei Jia and Kaikai You

Micromachines 2023, 14(4), 896; https://doi.org/10.3390/mi14040896 - 21 Apr 2023

Cited by 2 | Viewed by 1514

Abstract

With gate length (Lg) and gate spacing length (Ls) shrinkage, the cell-to-cell z-interference phenomenon is increasingly severe in 3D NAND charge-trap memory. It has become one of the key reliability concerns for 3D NAND cell scaling. In this work, z-interference mechanisms were investigated [...] Read more.

With gate length (Lg) and gate spacing length (Ls) shrinkage, the cell-to-cell z-interference phenomenon is increasingly severe in 3D NAND charge-trap memory. It has become one of the key reliability concerns for 3D NAND cell scaling. In this work, z-interference mechanisms were investigated in the programming operation with the aid of Technology Computer-Aided Design (TCAD) and silicon data verification. It was found that the inter-cell trapped charges are one of the factors causing z-interference after cell programming, and these trapped charges can be modulated during programming. Thus, a novel program scheme is proposed to suppress the z-interference by reducing the pass voltage (Vpass) of the adjacent cells during programming. As a result, the proposed scheme suppresses the Vth shift of 40.1% for erased cells with Lg/Ls = 31/20 nm. In addition, this work further analyzes the optimization and balance of program disturbance and z-interference with the scaling of cell Lg-Ls based on the proposed scheme. Full article

(This article belongs to the Special Issue Advances in Emerging Nonvolatile Memory, Volume II)

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16 pages, 4894 KiB

Open AccessArticle

Early Dirty Buffer Flush with Second Chance for SSDs

by Ilhoon Shin

Micromachines 2023, 14(4), 796; https://doi.org/10.3390/mi14040796 - 31 Mar 2023

Cited by 1 | Viewed by 1466

Abstract

As high-performance server-based applications become more prevalent, there is a growing demand for high-performance storage solutions. In response, SSDs that use NAND flash memory as storage media are quickly replacing hard disks in the high-performance storage market. One way to improve SSD performance [...] Read more.

As high-performance server-based applications become more prevalent, there is a growing demand for high-performance storage solutions. In response, SSDs that use NAND flash memory as storage media are quickly replacing hard disks in the high-performance storage market. One way to improve SSD performance is to use an internal large-capacity memory as a buffer cache for NAND. Previous studies have shown that early flushing, which ensures sufficient clean buffers by flushing dirty buffers to NAND in advance when the ratio of dirty buffers exceeds a threshold, significantly reduces the average response time of I/O requests. However, the early flush can also have a negative side effect, namely an increase in NAND write operations. To address this problem, this study proposes a selective early flush policy. This policy evaluates the likelihood of a candidate dirty buffer being rewritten upon the early flush, and delays flushing if the candidate has a high rewrite likelihood. Through this selective early flush, the proposed policy reduces NAND write operations by up to 18.0% compared to the existing early flush policy in the mixed trace. Additionally, the response time of I/O requests is also improved in most of the considered configurations. Full article

(This article belongs to the Special Issue Advances in Emerging Nonvolatile Memory, Volume II)

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8 pages, 2843 KiB

Open AccessArticle

Self-Adaption of the GIDL Erase Promotes Stacking More Layers in 3D NAND Flash

by Tao Yang, Bao Zhang, Qi Wang, Lei Jin and Zhiliang Xia

Micromachines 2023, 14(3), 686; https://doi.org/10.3390/mi14030686 - 20 Mar 2023

Cited by 1 | Viewed by 1897

Abstract

The bit density is generally increased by stacking more layers in 3D NAND Flash. Gate-induced drain leakage (GIDL) erase is a critical enabler in the future development of 3D NAND Flash. The relationship between the drain-to-body potential (V_db) of GIDL [...] Read more.

The bit density is generally increased by stacking more layers in 3D NAND Flash. Gate-induced drain leakage (GIDL) erase is a critical enabler in the future development of 3D NAND Flash. The relationship between the drain-to-body potential (V_db) of GIDL transistors and the increasing number of layers was studied to explain the reason for the self-adaption of the GIDL erase. The dynamics controlled by the drain-to-body and drain-to-gate potential contribute to the self-adaption of the GIDL erase. Increasing the number of layers leads to a longer duration of the maximum value of V_db (V_{db_max}), combined with the increased drain-to-gate potential, which enhances the GIDL current and further boosts channel potential to reach the same value at different positions of the NAND string. We proposed a method based on the correlation between the duration of V_{db_max} and the number of layers to obtain the limited layers of the GIDL erase. The limited layers allowed are more than four times the number of layers used in the current simulation. Combining the novel method of dividing the channel into multi-regions with the asynchronous GIDL erase method will be useful for further stacking more layers in 3D NAND Flash. Full article

(This article belongs to the Special Issue Advances in Emerging Nonvolatile Memory, Volume II)

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11 pages, 2185 KiB

Open AccessArticle

Thermal Characterization of Conductive Filaments in Unipolar Resistive Memories

by Cristina Aguilera-Pedregosa, David Maldonado, Mireia B. González, Enrique Moreno, Francisco Jiménez-Molinos, Francesca Campabadal and Juan B. Roldán

Micromachines 2023, 14(3), 630; https://doi.org/10.3390/mi14030630 - 10 Mar 2023

Cited by 2 | Viewed by 1364

Abstract

A methodology to estimate the device temperature in resistive random access memories (RRAMs) is presented. Unipolar devices, which are known to be highly influenced by thermal effects in their resistive switching operation, are employed to develop the technique. A 3D RRAM simulator is [...] Read more.

A methodology to estimate the device temperature in resistive random access memories (RRAMs) is presented. Unipolar devices, which are known to be highly influenced by thermal effects in their resistive switching operation, are employed to develop the technique. A 3D RRAM simulator is used to fit experimental data and obtain the maximum and average temperatures of the conductive filaments (CFs) that are responsible for the switching behavior. It is found that the experimental CFs temperature corresponds to the maximum simulated temperatures obtained at the narrowest sections of the CFs. These temperature values can be used to improve compact models for circuit simulation purposes. Full article

(This article belongs to the Special Issue Advances in Emerging Nonvolatile Memory, Volume II)

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8 pages, 2292 KiB

Open AccessArticle

Activation Enhancement and Grain Size Improvement for Poly-Si Channel Vertical Transistor by Laser Thermal Annealing in 3D NAND Flash

by Tao Yang, Zhiliang Xia, Dongyu Fan, Dongxue Zhao, Wei Xie, Yuancheng Yang, Lei Liu, Wenxi Zhou and Zongliang Huo

Micromachines 2023, 14(1), 230; https://doi.org/10.3390/mi14010230 - 16 Jan 2023

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Abstract

The bit density is generally increased by stacking more layers in 3D NAND Flash. Lowering dopant activation of select transistors results from complex integrated processes. To improve channel dopant activation, the test structure of vertical channel transistors was used to investigate the influence [...] Read more.

The bit density is generally increased by stacking more layers in 3D NAND Flash. Lowering dopant activation of select transistors results from complex integrated processes. To improve channel dopant activation, the test structure of vertical channel transistors was used to investigate the influence of laser thermal annealing on dopant activation. The activation of channel doping by different thermal annealing methods was compared. The laser thermal annealing enhanced the channel activation rate by at least 23% more than limited temperature rapid thermal annealing. We then comprehensively explore the laser thermal annealing energy density on the influence of Poly-Si grain size and device performance. A clear correlation between grain size mean and grain size sigma, large grain size mean and sigma with large laser thermal annealing energy density. Large laser thermal annealing energy density leads to tightening threshold voltage and subthreshold swing distribution since Poly-Si grain size regrows for better grain size distribution with local grains optimization. As an enabler for next-generation technologies, laser thermal annealing will be highly applied in 3D NAND Flash for better device performance with stacking more layers, and opening new opportunities of novel 3D architectures in the semiconductor industry. Full article

(This article belongs to the Special Issue Advances in Emerging Nonvolatile Memory, Volume II)

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13 pages, 4413 KiB

Open AccessArticle

On-Chip Photonic Synapses with All-Optical Memory and Neural Network Computation

by Lulu Zhang, Yongzhi Zhang, Furong Liu, Qingyuan Chen, Yangbo Lian and Quanlong Ma

Micromachines 2023, 14(1), 74; https://doi.org/10.3390/mi14010074 - 27 Dec 2022

Viewed by 1496

Abstract

Inspired by the human brain, neural network computing was expected to break the bottleneck of traditional computing, but the integrated design still faces great challenges. Here, a readily integrated membrane-system photonic synapse was demonstrated. By pre-pulse training at 1064 nm (cutoff wavelength), the [...] Read more.

Inspired by the human brain, neural network computing was expected to break the bottleneck of traditional computing, but the integrated design still faces great challenges. Here, a readily integrated membrane-system photonic synapse was demonstrated. By pre-pulse training at 1064 nm (cutoff wavelength), the photonic synapse can be regulated both excitatory and inhibitory at tunable wavelengths (1200–2000 nm). Furthermore, more weights and memory functions were shown through the photonic synapse integrated network. Additionally, the digital recognition function of the single-layer perceptron neural network constructed by photonic synapses has been successfully demonstrated. Most of the biological synaptic functions were realized by the photonic synaptic network, and it had the advantages of compact structure, scalable, adjustable wavelength, and so on, which opens up a new idea for the study of the neural synaptic network. Full article

(This article belongs to the Special Issue Advances in Emerging Nonvolatile Memory, Volume II)

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14 pages, 3144 KiB

Open AccessArticle

Resistance Switching in Polycrystalline C12A7 Electride

by Ivan D. Yushkov, Gennadiy N. Kamaev, Vladimir A. Volodin, Pavel V. Geydt, Aleksandr V. Kapishnikov and Alexander M. Volodin

Micromachines 2022, 13(11), 1917; https://doi.org/10.3390/mi13111917 - 06 Nov 2022

Cited by 1 | Viewed by 1304

Abstract

The memory (memristive) properties of an electride material based on polycrystalline mayenite (C12A7:e⁻) were studied. The phase composition of the material has been confirmed by such methods as XRD, TEM, Raman, and infrared spectroscopy. The electride state was confirmed by conductivity [...] Read more.

The memory (memristive) properties of an electride material based on polycrystalline mayenite (C12A7:e⁻) were studied. The phase composition of the material has been confirmed by such methods as XRD, TEM, Raman, and infrared spectroscopy. The electride state was confirmed by conductivity measurements and EPR using a characteristic signal from F⁺—like centers, but the peak at 186 cm⁻¹, corresponding to an electride with free electrons, was not observed explicitly in the Raman spectra. The temperature dependence of current–voltage characteristics in states with low and high resistance (LRS and HRS) has been studied. In the LRS state, the temperature dependence of the current has a non-Arrhenius character and is described by the Hurd quantum tunnelling model with a Berthelot temperature of 262 K, while in the HRS state, it can be described in terms of the Arrhenius model. In the latter case, the existence of two conduction regions, “impurity” and “intrinsic”, with corresponding activation energies of 25.5 and 40.6 meV, was assumed. The difference in conduction mechanisms is most likely associated with a change in the concentration of free electrons. Full article

(This article belongs to the Special Issue Advances in Emerging Nonvolatile Memory, Volume II)

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7 pages, 2353 KiB

Open AccessArticle

A Novel Capacitorless 1T DRAM with Embedded Oxide Layer

by Dongxue Zhao, Zhiliang Xia, Tao Yang, Yuancheng Yang, Wenxi Zhou and Zongliang Huo

Micromachines 2022, 13(10), 1772; https://doi.org/10.3390/mi13101772 - 19 Oct 2022

Viewed by 2677

Abstract

A novel vertical dual surrounding gate transistor with embedded oxide layer is proposed for capacitorless single transistor DRAM (1T DRAM). The embedded oxide layer is innovatively used to improve the retention time by reducing the recombination rate of stored holes and sensing electrons. [...] Read more.

A novel vertical dual surrounding gate transistor with embedded oxide layer is proposed for capacitorless single transistor DRAM (1T DRAM). The embedded oxide layer is innovatively used to improve the retention time by reducing the recombination rate of stored holes and sensing electrons. Based on TCAD simulations, the new structure is predicted to not only have the characteristics of fast access, random read and integration of 4F² cell, but also to realize good retention and deep scaling. At the same time, the new structure has the potential of scaling compared with the conventional capacitorless 1T DRAM. Full article

(This article belongs to the Special Issue Advances in Emerging Nonvolatile Memory, Volume II)

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Other

Jump to: Research

7 pages, 2371 KiB

Open AccessBrief Report

Systematical Investigation of Flicker Noise in 14 nm FinFET Devices towards Stochastic Computing Application

by Danian Dong, Jinru Lai, Yan Yang, Tiancheng Gong, Xu Zheng, Wenxuan Sun, Jie Yu, Shaoyang Fan and Xiaoxin Xu

Micromachines 2023, 14(11), 2098; https://doi.org/10.3390/mi14112098 - 14 Nov 2023

Viewed by 873

Abstract

Stochastic computing (SC) is widely known for its high error tolerance and efficient computing ability of complex functions with remarkably simple logic gates. The noise of electronic devices is widely used to be the entropy source due to its randomness. Compared with thermal [...] Read more.

Stochastic computing (SC) is widely known for its high error tolerance and efficient computing ability of complex functions with remarkably simple logic gates. The noise of electronic devices is widely used to be the entropy source due to its randomness. Compared with thermal noise and random telegraph noise (RTN), flicker noise is favored by researchers because of its high noise density. Meanwhile, unlike using RRAM, PCRAM and other emerging memory devices as the entropy source, using logic devices does not require any additional process steps, which is significant for industrialization. In this work, we systematically and statistically studied the 1/f noise characteristics of 14 nm FinFET, and found that miniaturizing the channel area of the device or lowering the ambient temperature can effectively increase the 1/f noise density of the device. This is of great importance to improve the accuracy of the SC system and simplify the complexity of the stochastic number generator (SNG) circuit. At the same time, these rules of 1/f noise characteristics in FinFET devices can provide good guidance for our device selection in circuit design. Full article

(This article belongs to the Special Issue Advances in Emerging Nonvolatile Memory, Volume II)

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