Advances in RF, Analog, and Mixed Signal Circuits

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Circuit and Signal Processing".

Deadline for manuscript submissions: 15 July 2024 | Viewed by 7631

Special Issue Editors


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Guest Editor
Department of Electrical and Computer Engineering, University of Thessaly, 38334 Volos, Greece
Interests: CMOS analog integrated circuits, including fractional-order circuits and systems; continuous and discrete-time analog filters; amplifiers; low voltage/low power building blocks for analog signal processing

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Guest Editor
Electronics Laboratory, Department of Physics, University of Patras, 26504 Patras, Greece
Interests: fractional-order circuits and systems; analog integrated circuits; fractional-order biomedical circuits; fractional-order filters
Special Issues, Collections and Topics in MDPI journals

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Guest Editor
Department of Electronics and Telecommunications, Politecnico di Torino, 10129 Turin, Italy
Interests: digital-based analog processing for IoT applications; low thermal sensitivity analog applications based on ZTC and GZTC MOSFET bias point modeling and SERDES design

Special Issue Information

Dear Colleagues,

Rapid developments in communications, signal processing, control, microelectronics, and computer systems give rise to different challenges involving complex design trade-offs. Several emerging applications are demanding more bandwidth, energy-efficient solutions, and intelligence based on smart technology while being small in size and low cost. The need to establish an appropriate balance between these contradictory requirements is driving the evolution of integrated circuits and systems. Therefore, the main objective of this Special Issue is to host new works, recent developments, reviews, and results in the field of analog, mixed signal, RF, and mmWave circuits and systems. Relevant topics include but are not limited to:

  • RF and mmWave circuits
  • RF active and passive component design
  • RX front-end circuits
  • Power amplifiers
  • Transceiver designs
  • High-speed I/O circuits
  • Clocking circuits
  • Data converters: ADCs and DACs
  • Low-power and low-voltage circuits
  • Power management circuits
  • Digital-based analog processing
  • CMOS and beyond circuit design
  • Machine learning techniques in analog/RF integrated circuit design
  • Mixed signal circuits/systems
  • Application of artificial intelligence in integrated circuits

Dr. Fotis Plessas
Prof. Dr. Costas Psychalinos
Dr. Pedro Toledo
Guest Editors

Manuscript Submission Information

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Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • integrated circuits and systems
  • mixed analog/digital circuit design
  • RF design
  • mmWave design
  • transceivers
  • power management
  • artificial intelligence applications

Published Papers (5 papers)

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Research

22 pages, 15981 KiB  
Article
Digital Calibration of Input Offset Voltage and Its Implementation in FDDA Circuits
by David Maljar, Michal Sovcik, Miroslav Potocny, Robert Ondica, Daniel Arbet and Viera Stopjakova
Electronics 2023, 12(22), 4615; https://doi.org/10.3390/electronics12224615 - 11 Nov 2023
Viewed by 681
Abstract
This article deals with the calibration method of analog integrated circuits (ICs) designed in CMOS nanotechnology. A brief analysis of various methods and techniques (e.g., fuse trimming, chopper stabilization, auto-zero technique, etc.) for calibration of a specific IC’s parameter is given, leading to [...] Read more.
This article deals with the calibration method of analog integrated circuits (ICs) designed in CMOS nanotechnology. A brief analysis of various methods and techniques (e.g., fuse trimming, chopper stabilization, auto-zero technique, etc.) for calibration of a specific IC’s parameter is given, leading to motivation for this research that is focused on the digital calibration. Then, the principle and overall design of the calibration subcircuit, which was generally used to calibrate the input offset voltage VIN_OFF of the operational amplifier (OPAMP). The essence of this work is verification of the proposed digital calibration algorithm for minimization the VIN_OFF of a bulk-driven fully differential difference amplifier (FDDA) with the power supply voltage VDD = 0.4 V. Evaluation of ASIC prototyped chip samples with silicon-proved results has been done. This evaluation contains comparison of selected parameters and characteristics obtained from both simulations and measurements of non-calibrated and calibrated FDDA configurations. Full article
(This article belongs to the Special Issue Advances in RF, Analog, and Mixed Signal Circuits)
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11 pages, 5410 KiB  
Communication
Design of a Clock Doubler Based on Delay-Locked Loop in a 55 nm RF CMOS Process
by Ho-Won Kim, Sungjin Kim and Kang-Yoon Lee
Electronics 2023, 12(13), 2830; https://doi.org/10.3390/electronics12132830 - 26 Jun 2023
Viewed by 1574
Abstract
In this paper, for the wireless network, wearable device, and Internet of Things (IoT) markets, a delay-locked loop (DLL) is used to implement accurate multiplication for a reference clock and the frequency of various applications through an edge combiner (EC). A simpler structure [...] Read more.
In this paper, for the wireless network, wearable device, and Internet of Things (IoT) markets, a delay-locked loop (DLL) is used to implement accurate multiplication for a reference clock and the frequency of various applications through an edge combiner (EC). A simpler structure is more sensitive to process, voltage, and temperature (PVT), so DLL complements itself quickly in the feedback system and improves the stability of the final output. The proposed DLL-based multiplier can prevent harmonic lock generation using a first phase canceller (FPC), thus compensating for faster lock time. The circuit is built with a 55 nm CMOS process and has a chip area of 0.0225 mm2. The proposed design achieves a total power consumption of 0.48 mW at the 30.72 MHz operating clock frequency, and the clock duty can also operate stably from 15 to 75%. Full article
(This article belongs to the Special Issue Advances in RF, Analog, and Mixed Signal Circuits)
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27 pages, 1999 KiB  
Article
A Hybrid GA/ML-Based End-to-End Automated Methodology for Design Acceleration of Wireless Communications CMOS LNAs
by Christos Sad, Anastasios Michailidis, Thomas Noulis and Kostas Siozios
Electronics 2023, 12(11), 2428; https://doi.org/10.3390/electronics12112428 - 27 May 2023
Viewed by 877
Abstract
A new methodology for the RF/mmWave analog design process, automation and acceleration, is presented in this work. The proposed framework was implemented so as to accelerate the design cycle of analog/RF circuits by creating a dataset in a fully automated manner and training [...] Read more.
A new methodology for the RF/mmWave analog design process, automation and acceleration, is presented in this work. The proposed framework was implemented so as to accelerate the design cycle of analog/RF circuits by creating a dataset in a fully automated manner and training a combination of machine learning models for the optimal design parameters’ prediction. machine learning polynomial regression was adopted to accelerate the design process, predicting the optimal design parameters’ values while genetic algorithm optimization was exploited for the dataset creation automation. To evaluate the efficiency of the proposed methodology, the framework was implemented for the design of a common source Low-Noise-Amplifier, using a 65 nm CMOS process node. The proposed methodology successfully tackles the design cycle speed-up, automation, and acceleration, utilizing machine learning prediction for the design parameters and genetic algorithm for the dataset creation automation instead of the classical, simulation-based, standard design methodology. The provided experimental results have shown the effectiveness of the proposed hybrid approach, creating very precise RF matching networks for LNA designs and achieving >99.9% wave transmission efficiency while reaching >99% accuracy on the parameters’ prediction task. Full article
(This article belongs to the Special Issue Advances in RF, Analog, and Mixed Signal Circuits)
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16 pages, 5406 KiB  
Article
A Wide-Range Four-Phase All-Digital DLL with De-Skew Circuit
by Jing Kang, Fei Liu, Ya Hai and Yongshan Wang
Electronics 2023, 12(7), 1610; https://doi.org/10.3390/electronics12071610 - 29 Mar 2023
Viewed by 1462
Abstract
A four-phase all-digital delay-locked loop (ADDLL) with a de-skew circuit for NAND Flash high-speed interfaces is proposed. The proposed de-skew circuit adopts a fall-edge-judgment phase adjuster and a three-stage digitally controlled delay line to align the system input clock and 0 output [...] Read more.
A four-phase all-digital delay-locked loop (ADDLL) with a de-skew circuit for NAND Flash high-speed interfaces is proposed. The proposed de-skew circuit adopts a fall-edge-judgment phase adjuster and a three-stage digitally controlled delay line to align the system input clock and 0 output clock of the four-phase DLL over a wide frequency range, thus solving the four-phase offset caused by clock skew. A parallel-cascade configuration is proposed to solve the variable phase alignment problem caused by mode switching, thus effectively improving the phase-locked accuracy. The proposed circuit is fabricated in the 0.13 μm CMOS process with a 0.072 mm2 core area. The chip testing results show an operating frequency range from 26 MHz to 1.55 GHz and a typical alignment error of approximately 17 ps. Full article
(This article belongs to the Special Issue Advances in RF, Analog, and Mixed Signal Circuits)
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14 pages, 2088 KiB  
Article
NS-GAAFET Compact Modeling: Technological Challenges in Sub-3-nm Circuit Performance
by Fabrizio Mo, Chiara Elfi Spano, Yuri Ardesi, Massimo Ruo Roch, Gianluca Piccinini and Marco Vacca
Electronics 2023, 12(6), 1487; https://doi.org/10.3390/electronics12061487 - 21 Mar 2023
Cited by 2 | Viewed by 2338
Abstract
NanoSheet-Gate-All-Around-FETs (NS-GAAFETs) are commonly recognized as the future technology to push the digital node scaling into the sub-3 nm range. NS-GAAFETs are expected to replace FinFETs in a few years, as they provide highly electrostatic gate control thanks to the GAA structure, with [...] Read more.
NanoSheet-Gate-All-Around-FETs (NS-GAAFETs) are commonly recognized as the future technology to push the digital node scaling into the sub-3 nm range. NS-GAAFETs are expected to replace FinFETs in a few years, as they provide highly electrostatic gate control thanks to the GAA structure, with four sides of the NS channel entirely enveloped by the gate. At the same time, the NS rectangular cross-section is demonstrated to be effective in its driving strength thanks to its high saturation current, tunable through the NS width used as a design parameter. In this work, we develop a NS-GAAFET compact model and we use it to link peculiar single-device parameters to digital circuit performance. In particular, we use the well-known BSIM-CMG core solver for multigate transistors as a starting point and develop an ad hoc resistive and capacitive network to model the NS-GAAFET geometrical and physical structure. Then, we employ the developed model to design and optimize a digital inverter and a five-stage ring oscillator, which we use as a performance benchmark for the NS-GAAFET technology. Through Cadence Virtuoso SPICE simulations, we investigate the digital NS-GAAFET performance for both high-performance and low-power nodes, according to the average future node present in the International Roadmap for Devices and Systems. We focus our analysis on the main different technological parameters with regard to FinFET, i.e., the inner and outer spacers. Our results highlight that in future technological nodes, the choice of alternative low-K dielectric materials for the NS spacers will assume increasing importance, being as relevant, or even more relevant, than photolithographic alignment and resolution at the sub-nm scale. Full article
(This article belongs to the Special Issue Advances in RF, Analog, and Mixed Signal Circuits)
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