NS-GAAFET Compact Modeling: Technological Challenges in Sub-3-nm Circuit Performance

Abstract

NanoSheet-Gate-All-Around-FETs (NS-GAAFETs) are commonly recognized as the future technology to push the digital node scaling into the sub-3 nm range. NS-GAAFETs are expected to replace FinFETs in a few years, as they provide highly electrostatic gate control thanks to the GAA structure, with four sides of the NS channel entirely enveloped by the gate. At the same time, the NS rectangular cross-section is demonstrated to be effective in its driving strength thanks to its high saturation current, tunable through the NS width used as a design parameter. In this work, we develop a NS-GAAFET compact model and we use it to link peculiar single-device parameters to digital circuit performance. In particular, we use the well-known BSIM-CMG core solver for multigate transistors as a starting point and develop an ad hoc resistive and capacitive network to model the NS-GAAFET geometrical and physical structure. Then, we employ the developed model to design and optimize a digital inverter and a five-stage ring oscillator, which we use as a performance benchmark for the NS-GAAFET technology. Through Cadence Virtuoso SPICE simulations, we investigate the digital NS-GAAFET performance for both high-performance and low-power nodes, according to the average future node present in the International Roadmap for Devices and Systems. We focus our analysis on the main different technological parameters with regard to FinFET, i.e., the inner and outer spacers. Our results highlight that in future technological nodes, the choice of alternative low-K dielectric materials for the NS spacers will assume increasing importance, being as relevant, or even more relevant, than photolithographic alignment and resolution at the sub-nm scale.

1. Introduction

Planar Field-Effect Transistors (FETs) have become obsolete during the last decade, making way for three-dimensional FETs [1]. Fin-shaped FETs (FinFETs) have been developed and successfully commercialized in their multi-gate configuration, pursuing Moore’s law while reducing short-channel effects (SCEs) [2,3,4]. This success allowed FinFET to become the dominant technology until the latest 3-nm node. However, nowadays, FinFET technology is facing many challenges in performance, layout, and cost for further scaling, determining its end in the sub-3-nm technological node [5,6,7,8]. Novel TCAD tools, improving the electronics industry toolchain, are currently being developed to investigate cost-effective solutions to still pursue more-than-Moore integration [5]. Nevertheless, power performance appears often as a limiting factor for FinFET-based ICs at ultra-scaled technological nodes, and optimizations in the energy delay product are difficult and still searched for [6]. In addition, FinFET-based IC reliability is an addressed problem at the current level of scaling, and different solutions, such as SOI devices, are considered despite their increased costs [7].

In this scenario, vertically stacked NanoSheet Gate-All-Around FETs (NS-GAAFETs) have been recognized as the most promising candidates to replace FinFETs at a reduced technology transition cost, since they can be mass-produced using almost the same manufacturing processes and instrumentation [9,10]. Indeed, thanks to their superior electrostatic channel control that minimizes SCEs, larger drive current per layout footprint, low operational voltage and design flexibility, vertically stacked NS-GAAFETs constitute the near-term future of integrated circuits [11]. Furthermore, the increased design flexibility of NSGAAFETs in comparison to FinFETs is proven. Thanks to the fine tuning of the device width and through stacked transistors, NSGAAFETs are good candidates to manage the problematic power–performance optimization [9]. Despite the technological challenges, significant experimental advances show the high competitiveness of NSGAAFETs for future technology nodes. Furthermore, NSGAAFET technology has already been successfully demonstrated with a fully working, high-density SRAM, showing superior performance with regard to the FinFET implementation [10], and demonstrating also that the NSGAAFET technology is close to mass production.

The current literature presents many fabrication processes and device-level studies on NS-GAAFETs [12,13,14,15]. In contrast, only a few studies are carried out at the circuital and application levels, mainly due to the lack of compact models essential for digital design. Moreover, and to the best of our knowledge, there still need to be studies dedicated to linking the system-level performance to technological parameters such as photolithographic process variations and spacer dielectric properties.

The important demand for NSGAAFET investigation as a promising near-term future technology for integrated circuits, and the need for its assessment at the circuital and application levels to be linked to the technological parameters of this emerging technology, motivate the present paper. For these purposes, in this work, we adapt the well-established BSIM Common MultiGate (CMG) SPICE model [16] to the case of the vertically stacked NS-GAAFET technology. In particular, while we keep the efficient surface potential solver for the coupled Poisson’s equation with Boltzmann’s statistics for carriers under the Gradual Channel Approximation, we modify and remap the resistive network and the capacitive network to account for the geometrical differences in the NSGAAFETs with regard to the FinFETs or cylindrical GAAFET currently available in the BSIM CMG model. Furthermore, thanks to our customized compact model, we quantify the impact of device-level parameters and parasitics on the circuital and system-level operating frequency, providing valuable guidelines for future technological considerations and optimizations. In particular, our simulation results show the significant sensitivity of the operating frequency of the analyzed five-stage ring oscillator (RO) on the parasitic capacitances of the inner spacers, demonstrating the more considerable importance of advanced low-k dielectric materials rather than the inner and outer spacers’ alignment for future research investments.

The paper is organized as follows. Section 2 explains the modeling of the vertically stacked NS-GAAFET technology. For clarity, additional details and the equations to be modified or additionally included in the BSIM-CMG model are reported in Section 3. In Section 4, we present the methodology and the design and characterization strategies that we adopt. In Section 5, the model is tested in Cadence Virtuoso^® and the results are presented and discussed.

2. Model

To accurately describe NS-GAAFETs through a compact model, we adapt the well-established BSIM-CMG SPICE model [16] to the case of NS-GAAFETs. The BSIM-CMG 110.0.0 compact model is a surface-potential-based model in which all the physical quantities, including the terminal currents, are calculated from the surface channel potentials at source (S) and drain (D) terminals. It is organized into two main components: a core model that solves Poisson’s equation with Boltzmann’s statistics for carriers and exploits the ideal Gradual Channel Approximation (GCA)—a long channel device—and the set of real-device sub-models that account for all non-idealities, such as quantum mechanical models, and all the SCEs and parasitics affecting the performance of real and short-channel devices. Details can be found in [16].

We use the BSIM-CMG Quadruple-Gate-FET (QG-FET) as a starting point, i.e., a gate-all-around structure. Figure 1a–c report the NS-GAAFET structure, together with the variable names in BSIM-CMG and the corresponding quantities in NS-GAAFET. We use some of the existing BSIM-CMG variables to describe the NanoSheet (NS) geometry. In particular, we remap the fin thickness $T_{fin}$ as the NS width $W_{NS}=T_{fin}$, and the fin height $H_{fin}$ as the NS height $H_{NS}=H_{fin}$. We then characterize the NS-GAAFET through the number of NS per stack $N_{NS}$, the vertical spacing between adjacent NS $T_{sp}$, the total height of the stack $H_{stack}=N_{NS}[H_{NS}+T_{sp}]$, and its effective width $W_{eff}=N_{NS}[2W_{NS}+2H_{NS}]$. We also account for the different geometrical structures of NS-GAAFETs with regard to FinFETs in the device’s parasitic resistance and capacitive networks, as described in the following.

While many non-ideality effects, such as quantum confinement and tunnelling, velocity saturation, high-mobility fields, or doping degradation, are automatically accounted for in BSIM-CMG for NS-GAAFETs once the model is remapped and modified as described above, the parasitic resistance and capacitance contributions are not. We thus focus on modeling and correcting the existing parasitic resistive and capacitive networks for the case of NS-GAAFETs.

The contact resistance $R_{con}$ and the spreading resistance $R_{sp}$ account for the S/D resistances—including the silicon–silicide interface—and for the S/D resistances due to the current spreading from the S/D thin extension to the large S/D regions (and vice versa)—see Figure 1d. In the case of NS-GAAFETs, the penetration length of the carrier’s fluxes into the S/D epitaxial regions depends on the specific NS position with regard to the substrate. It will be the longest for the NS at the bottom of the stack and the shortest for the one at the top. We thus correct the $R_{con}$ and $R_{sp}$ considering in their explicit expressions an average carrier path in the S/D regions—see Equations (1) and (2)—corresponding to half of the total stack height ($H_{stack}/2$). As in FinFETs, also in NS-GAAFETs, extensions are needed to avoid short circuits of the gate with the S/D—see Figure 1a, inner spacers. In the case of stacked NS, we model the total $R_{ext,tot}$ as the parallel of the single NS extension resistances—see Equation (3). Figure 1e summarizes the parasitics resistive network of NS-GAAFETs.

For the capacitive network, we use the most accurate modeling approach in BSIM-CMG, namely the physically based one. The fringe capacitance represents the total capacitive coupling among the gate, extensions, and S/D regions. In NS-GAAFETs, $N_{NS}$ channels are present. The side component is thus modified to account for the effect of the $N_{NS}$ parallel channels—see Equation (4)—while the top and corner fringe capacitance are unchanged in the NS configuration. The S/D-to-gate overlap capacitances are modified to account for the NS effective width $W_{eff}$ as in Equation (5). Furthermore, in the NS-GAAFET structure, inner spacers are aimed at separating the gate from the S/D regions, avoiding short circuits. Nevertheless, spacers give rise to additional capacitive contributions between the S/D regions and the inter-channel metal gates through the spacers themselves. Thanks to the planar geometry arising from the NS structure, we calculate the additional spacer capacitance through the parallel plate model, and then we sum the single contributions since capacitances are in parallel—see Equation (6). Such contributions are formally included in the fringe capacitive network. Finally, the capacitance contribution toward the substrate through the Bottom Dielectric Insulator (BDI) is unchanged for the NS-GAAFET. The modified capacitances are highlighted in Figure 1e.

Finally, we refer to our modified version of the BSIM-CMG model as BSIM-CMG-NS.

3. Model Equations

In this section, we report the model equations that we modify to account for the differences in NS-GAAFETs with regard to FinFETs.

Contact resistance:

We use the oiginal BSIM-CMG expression for the contact resistance [16]:

$$R_{con}=L_T·\frac{{\rho }_{S/D}}{A_{rsd}}·\frac{cosh\left({\alpha }_{av}\right)+\eta sinh\left({\alpha }_{av}\right)}{sinh\left({\alpha }_{av}\right)+\eta cosh\left({\alpha }_{av}\right)}$$

(1)

where ${\rho }_{S/D}=\frac{1}{qNSD\mu }$ is the S/D resistivity, q is the elementary charge, $NSD$ the S/D doping, and $\mu$ the mobility. We modify the geometrical factors $A_{rsd}$ and $P_{rsd}$ to account for the different NS-GAAFET geometry—see Figure 1—and we consequently modify $L_T$, ${\alpha }_{av}$, and $\eta$:

$$\begin{array}{cc}\hfill & A_{rsd}=FP·\frac{H_{stack}}{2}+W_{NS}·H_{epi}+C_r·(FP-W_{NS})·H_{epi}\hfill \\ \hfill & P_{rsd}=\left(H_{stack}+2·FP\right)+\left(FP+2·\sqrt{H_{epi}^2+\frac{{(FP-W_{NS})}^2}{4}}\right)\hfill \\ \hfill & L_T=\sqrt{\frac{{\rho }_{con,sili}{A}_{rsd}}{{\rho }_{S/D}{P}_{rsd}}}\hfill \\ \hfill & {\alpha }_{av}=\frac{LRSD}{L_T}\hfill \\ \hfill & \eta =\frac{{\rho }_{S/D}{L}_T}{{\rho }_{con,sili}}\hfill \end{array}$$

where ${\rho }_{con,sili}$ is the contact resistivity at the silicide/silicon interface, $P_{rsd}$ is the transverse perimeter of S/D regions, $A_{rsd}$ is the S/D transverse cross-section area, $LRSD$ is the S/D region longitudinal length, $FP$ is the Fin Pitch, and $C_r$ is the ratio of the S/D epitaxial region corner area filled with silicon to the total corner area.

Spreading resistance:

We modify the spreading resistance expression according to the NS-GAAFET S/D region geometry and extension presence. Only the contribution $\mathsf{\Theta }$ is unaltered from the BSIM-CMG original model (i.e., we consider the same geometrical dispersion of current density to access the channel from S/D):

$$\begin{array}{cc}\hfill & R_{sp}=\mathsf{\Theta }·\left(\frac{1}{\sqrt{W_{NS}{H}_{stack}/2}}-\frac{2}{\sqrt{A_{rsd}}}+\frac{\sqrt{W_{NS}{H}_{stack}/2}}{A_{rsd}}\right)\hfill \\ \hfill & \mathsf{\Theta }=\frac{{\rho }_{S/D}cot\left(\theta \right)}{\sqrt{\pi }}\hfill \end{array}$$

(2)

where $\theta$ is the spreading angle at which the current spreads in the raised S/D (usually around 55°).

Extension resistance:

We modify the extension resistance $R_{ext,tot}$ to account for the $N_{NS}$ number of parallel channels:

$$R_{ext,tot}=R_{ext,1}\left|\right|R_{ext,2}\left|\right|...\left|\right|R_{ext,i}\left|\right|...\left|\right|R_{ext,N_{NS}}$$

(3)

where $R_{ext,i}$ corresponds to the default BSIM-CMG extension resistance [16], which, in NS-GAAFETs, corresponds to the single-NS extension resistance.

Fringe Capacitance:

Thanks to the names given to NS dimensions—see Figure 1b—the only fringe capacitance component to be modified with respect to the original expression present in BSIM-CMG is the side one, which we calculate as follows:

$$\begin{array}{cc}\hfill & C_{FR,sidest}=C_{FR,side}·\left(N_{NS}{H}_{NS}\right)+C_{cg1,side}·H_{stack}+\hfill \\ \hfill & C_{cg2,side}·H_{stack}\hfill \end{array}$$

(4)

where $C_{FR,side}$, $C_{cg1,side}$, and $C_{cg2,side}$ are left unchanged as defined in BSIM-CMG [16].

Overlap capacitance:

Once the effective width is redefined for the NS geometry, the overlap capacitance is automatically updated to the correct value. They are still evaluated as the numerical derivatives with respect to $V_{GS}$ and $V_{DS}$ of the charge due to the lateral diffusion of dopants, as in the original BSIM-CMG model [16]:

$$\begin{array}{cc}\hfill & Q_{gs,ovst}\left(W_{eff}\right),Q_{gd,ovst}\left(W_{eff}\right)\hfill \\ \hfill & with:W_{eff}=N_{NS}[2W_{NS}+2H_{NS}]\hfill \\ \hfill & overlapcapacitances⟷\frac{\partial Q_{gs,ovst}}{\partial V_{GS}},\frac{\partial Q_{gd,ovst}}{\partial V_{DS}}\hfill \end{array}$$

(5)

Inner spacer capacitance:

We calculate the additional inner spacer capacitances (not present in BSIM-CMG) at one S/D side as

$$\begin{array}{cc}\hfill & C_{inner,sp}=\frac{{ϵ}_{inn,sp}}{L_{inn,sp}}·T_{sp}·FP+\frac{{ϵ}_{inn,sp}}{L_{inn,sp}}·H_{NS}·(FP-W_{NS})\hfill \\ \hfill & C_{inner,sp,TOT}=N_{NS}·C_{inner,sp}\hfill \end{array}$$

(6)

where ${ϵ}_{inn,sp}$ is the dielectric constant of the inner spacer material, $L_{inn,sp}$ is the inner spacer length (longitudinal to transport direction), and $T_{sp}$ is the inner spacer height (spacing between adjacent NS).

4. Methodology, Figures of Merit, and Characterization

We use the developed model to understand how the device parameters affect the system-level performance in sub-3-nm nodes. Thus, we resolve to link the digital circuit performance to technological and device-level parameters. For the sake of generality and to understand the eventual differences, we address both high-performance (HP) processes and low-power (LP) processes [11]. The latter also corresponds to memory applications [11]. We choose the typical geometrical and physical parameters from the average ones reported in [11], for generic sub-3-nm nodes.

Table 1. Geometrical and physical parameters for the simulated n-type NS-GAAFET.

${\mathit{N}}_{\mathit{N}\mathit{S}}$	3	${\mathit{t}}_{\mathit{O}\mathit{X}}$	3.2 nm
$W_{NS}$	20 nm (HP); 30 nm (LP/Memory)	${ϵ}_{OX}$	25
$H_{NS}$	7 nm	${ϵ}_{inn,sp}$	3.9
$L_{ch}$	14 nm	${ϵ}_{out,sp}$	3.9
FP	49 nm	$N_{body}$	${10}^{17}$ cm−3
$H_{epi}$	10 nm	$N_{SD}$	${10}^{21}$ cm−3
$T_{sp}$	10 nm	$N_{SDE}$	${10}^{19}$ cm−3

reports our choices. The only difference between HP and LP devices is the NS width $W_{sh}$, which corresponds to different driving currents. The quantities $t_{OX}$ and ${ϵ}_{OX}$ are the thickness and the relative dielectric constant of the gate oxide, whereas ${ϵ}_{inn,sp}$ and ${ϵ}_{out,sp}$ are the relative dielectric constant of the inner and outer spacer materials, and $N_{body}$, $N_{SD}$, $N_{SDE}$ are the typical doping values for the channel, S/D regions, and S/D extensions, respectively. According to [11], we consider a supply voltage $V_{DD}$ = 0.7 V. In addition, we consider various low-K materials to be used as spacer dielectrics. In particular, we consider values of ${ϵ}_{inn,sp}$ and ${ϵ}_{out,sp}$ of the most promising low-K materials for electronic devices, also considering their mechanical properties, according to [17,18,19]. The considered values are reported in

Table 2. Low-K materials considered in this work.

Material	Relative Dielectric Constant
vacuum (air)	1
porous SiO2 and/or polymeric materials	2
carbon-doped oxide	2.8
SiO2	3.9
SiOCN	5.2
Si3N4	7.5

with the corresponding low-K materials.

We investigate the impact of technological parameters on digital circuits’ performance in Cadence Virtuoso. First, we use the developed VerilogA model BSIM-CMG-NS to simulate and optimize the n-NS-GAAFET device in Cadence Virtuoso—refer to Section 5.1. Then, we design the p-NS-GAAFET to have a symmetric transcharacteristic with respect to the n-type device, and we design and optimize the digital inverter—see Section 5.2. To address the performance study, we exploit the de facto standard ring oscillator (RO) with five stages (five cascaded inverters) [20,21]. Then, to link the digital circuit performance and device-level parameters, we calculate and extract the RO oscillating frequency sensitivity to device technological parameters—see Section 5.3. Finally, we simulate and measure the oscillating frequency in Cadence Virtuoso for different technological parameters. In particular, we investigate the inner and outer spacer dielectric constants and length and the NS spacing since they are not present in conventional FinFETs and significant outcomes may arise from this analysis. In order to identify which parameter more strongly influences the RO oscillating frequency and digital circuit performance, we vary one parameter at a time while the others are fixed to the nominal values in Table 1. To generalize the obtained results, we repeat the previous steps for the 30 nm (HP) n-NS-GAAFET and for the 20 nm (LP) one and compare the results.

We characterize the considered devices through the following Figures of Merit (FoM):

• Drain-Induced Barrier Lowering (DIBL): We calculate this from its definition as

  $$DIBL=-\frac{{\left.V_{TH}\right|}_{V_{DD}}-{\left.V_{TH}\right|}_{V_{low}}}{V_{DD}-V_{low}}$$

  (7)

  where $V_{DD}$ is the supply voltage, $V_{low}$ is a low voltage value that we fix to 50 mV, and ${\left.V_{TH}\right|}_{V_i}$ is the obtained threshold voltage with the voltage $V_i$, where $V_i=V_{DD},V_{low}$. We calculate $V_{TH}$ through the second-order derivative of the transcharacteristic, i.e., the maximum transconductance method [22,23].
• Subthreshold Slope (SS): This is defined as

  $$SS={\left[\frac{\partial lo{g}_{10}\left(I_{DS}\right)}{\partial V_{GS}}\right]}^{-1}$$

  (8)
  For simplicity, we calulate it as $SS={\left[\Delta lo{g}_{10}\left(I_{DS}\right)/\Delta V_{GS}\right]}^{-1}$, where $\Delta$ indicates an interval (i.e., a difference), and considering an $I_{DS}$ excursion $\Delta lo{g}_{10}\left(I_{DS}\right)$ of one decade.
• $I_{ON}$: Driving ON current, obtained with $V_{DS}=V_{GS}=V_{DD}$;
• $I_{OFF}$: subthreshold leakage OFF current, obtained with $V_{DS}=V_{DD}$ and $V_{GS}$ = 0 V;
• $I_{ON}/I_{OFF}$ ratio.

We characterize our design through the sensitivity to technological parameters. We calculate the sensitivity S and the percentage sensitivity $S_{\%}$ of the quantity Q with regard to the parameter p as

$$S=\frac{\partial Q}{\partial p}\approx \frac{\Delta Q}{\Delta p},S_{\%}=\frac{\partial Q}{\partial p}·\frac{\overline{p}}{\overline{Q}}·100\approx \frac{\Delta Q}{\Delta p}·\frac{\overline{p}}{\overline{Q}}·100,$$

(9)

where the operator ∂ represents the partial derivative, $\Delta$ is the difference operator, and $\overline{p}$ and $\overline{Q}$ are the nominal parameter value and nominal quantity value, respectively.

5. Design, Simulations, and Results

5.1. n-Type NS-GAAFET

Figure 2 shows the simulated transcharacteristics $I_{DS}\left(V_{GS}\right)$ in a semi-logarithmic scale as a function of the NS width $W_{NS}$. The inset of Figure 2 shows the $I_{ON}/I_{OFF}$ ratio by varying $W_{sh}$.

Table 3. Calculated FoM for each considered NS width $W_{sh}$.

${\mathit{W}}_{\mathit{s}\mathit{h}}$ (nm)	20	30	40	50
DIBL (mV/V)	12.3	30.8	43.1	52.3
SS (mV/dec)	67	69	72	73
$I_{ON}/I_{OFF}$ (a.u.)	1.18·10${}^6$	2.19·10${}^5$	8.02·10${}^4$	4.12·10${}^4$
$I_{ON}$ (µA)	87	148	202.5	263

reports the extracted FoM for the curves in Figure 2.

An abrupt performance variation occurs when passing from $W_{sh}$ = 20 nm to $W_{sh}$ 30 nm. The corresponding transcharacteristics in Figure 2 are more spaced than the ones corresponding to 40 and 50 nm, and the $I_{ON}/I_{OFF}$ deterioration is more marked with regard to a successive $W_{sh}$ increase. The same trend is present in Table 3. A significant DIBL deterioration occurs when $W_{sh}$ is increased from 20 nm to 30 nm. For successive increases, the DIBL presents less worsening. The same applies to $I_{ON}/I_{OFF}$—as mentioned above—which decreases by one order of magnitude from 20 to 30 nm of $W_{sh}$, while a minor deterioration is present for a successive increase in $W_{sh}$. In contrast, SS is the only FoM presenting a linear deterioration passing gradually from $W_{sh}$ = 20 nm to $W_{sh}$ = 50 nm. The $I_{ON}$ is almost doubled passing from $W_{sh}$ = 20 nm to $W_{sh}$ = 30 nm, whereas, for a successive increase in $W_{sh}$, it increases.

For an HP node, the $I_{ON}$ with $W_{sh}$ = 20 nm is too low, so an n-NS-GAAFET width of 30 nm is the optimal compromise between a high driving current $I_{ON}$ and good device performance in terms of DIBL, SS, $I_{ON}/I_{OFF}$. This agrees with the device design guidelines in [11]. For an LP node, $W_{sh}$ = 20 nm is a good compromise between low $I_{OFF}$ leakages and optimal device FoM in terms of DIBL, SS, $I_{ON}/I_{OFF}$.

Furthermore, our results match the literature’s theoretical and experimental results for the different target applications [5,10,12,14]. Thus, we consider the developed model reliable since it correctly predicts the experimental results in [5,10,12].

5.2. Digital Inverter

We design the logic inverter by finding the width $W_p$ of the p-type NS-GAAFET that leads to the most symmetric inverter transcharacteristic. We start from $W_p=W_n$, where $W_n$ is $W_{NS}$ for the n-type device, as discussed previously. Then, we decrease $W_p$ until the optimum is found, which corresponds to fully symmetric n-type and p-type transcharacteristics.

Notice that we decrease $W_p$ with regard to $W_n$ since we suppose the silicon NS growth direction to be [110] and thus to obtain the largest faces of the NS with hole mobility greater than electron one and smallest faces with hole mobility lower than electron one, leading to a total effective hole mobility larger than electron one. This choice is also typical in FinFETs, due to typical technological situations. In general, the choice to have the NS growth direction parallel to [100] is also possible, leading to electron mobility larger than hole one and therefore a $W_p>W_n$. These features can be selected through a flag in the original BSIM-CMG model [16] and also in the proposed BSIM-CMG-NS one.

5.2.1. HP Node

For the HP process, we find the optimum $W_p$ to be 22 nm. The inverter transcharacteristics obtained by varying $W_p$ are reported in Figure 3, and the inset shows an enlargement of the dashed box region. We find the most symmetric inverter transcharacteristic for a p-type width $W_p$ = 22 nm, and thus we choose it to implement the inverter logic gate. A ratio ${\beta }_p=W_p/W_n$ = 0.767 is thus assumed. The relative n-type and p-type NS-GAAFET single device transcharacteristics with $W_n$ = 30 nm and $W_p$ = 22 nm are reported in Figure 4 in logarithmic scale. Good symmetry is present for the chosen transistor widths. The inset of Figure 4 shows the same transcharacteristics in linear scale, highlighting a good match also for ON currents, with n-type $I_{ON,n}$ = 148 µA and p-type $I_{ON,p}$ = 147.4 µA.

Notice that the effective drive current of the inverter [24], calculated with the three-point method [25], for the HP node is $I_{eff}$ = 28.7 µA.

5.2.2. LP Node

We repeat the same for the LP process and we find an optimum $W_p$ of 14 nm. The inverter transcharacteristics obtained by varying $W_p$ are reported in Figure 5; the inset shows an enlargement of the dashed box region. The ratio ${\beta }_p=W_p/W_n$ is 0.7. The relative n-type and p-type NS-GAAFET transcharacteristics with $W_n$ = 20 nm and $W_p$ = 14 nm are reported in Figure 6 in logarithmic scale. Again, good symmetry is present for the chosen transistor widths.

The effective drive current of the inverter [24], calculated with the three-point method [25], for the LP node is $I_{eff}$ = 17.1 µA.

5.3. Five-Stage Ring Oscillator

We use the designed digital inverter to implement a five-stage RO—i.e., 5 cascaded inverters—and then we use the RO to extract the digital circuit performance, according to what commonly is done in the literature [20,21].

5.3.1. LP Node ($W_n$ = 20 nm)

Figure 7a reports the RO oscillating frequency $f_{osc}$ as a function of both ${ϵ}_{inn,sp}$ and ${ϵ}_{out,sp}$. We consider the (relative) dielectric constants in Table 2. An increase in the spacer dielectric constant leads to an increase in inner and outer spacer capacitance. Therefore, a frequency reduction occurs. There is no compromise with other NS-GAAFET parameters and the only upper limit to $f_{osc}$ is dictated by the lowest possible dielectric constant, theoretically equal to 1 vacuum. Nevertheless, the structural and mechanical properties make it difficult to build suspended NS, and dielectric materials are used to guarantee structural stability and prevent the gate and S/D short circuits.

Figure 7b reports the RO oscillating frequency $f_{osc}$ as a function of both $L_{inn,sp}$ and $L_{out,sp}$. The blue curve is related to a variation in both $L_{inn,sp}$ and $L_{out,sp}$, which are assumed to be equal. This case represents different photolithographic processes with different spacing between the channels and the S/D regions. The orange curve is related to a variation in $L_{inn,sp}$ when the $L_{out,sp}$ is fixed. This case may happen due to photolithographic process variations and NS misalignment. A longitudinal trapezoidal device cross-section would appear in case of misalignment, as experimentally verified in some cases [5,10,12]. A larger $f_{osc}$ excursion is present when both $L_{inn,sp}$ and $L_{out,sp}$ are varied. Nevertheless, a significant $f_{osc}$ excursion is also present in the case of misalignment. In particular, being the spacer capacitance inversely proportional to the S/D and channel spacing, i.e., to $L_{inn,sp}$ and $L_{out,sp}$, the longer are the inner/outer spacers, the lower are the relative capacitances and the higher is $f_{osc}$. For the considered generic sub-3-nm node, the nominal $L_{inn,sp}$ and $L_{out,sp}$ value is 6 nm, for which the blue and orange curves are overlapped. Although the longer the spacers are, the better the performance is, a trade-off is present with the channel access resistances that are inversely proportional to the spacer length, corresponding also to the NS portion between the S/D and the region underneath the gate. Longer spacers and NS access regions decrease the ON current and increase the OFF leakage since the portion of the NS that is not under gate control is lengthened.

5.3.2. HP Node and Comparison with LP Node

We repeat the RO design and $f_{osc}$ extraction for the HP node ($W_n$ = 30 nm). Similar trends and considerations hold for the HP node case when $f_{osc}$ is considered for ${ϵ}_{inn,sp}$, ${ϵ}_{out,sp}$, $L_{inn,sp}$, and $L_{out,sp}$ variations. Then, we calculate the $f_{osc}$ sensitivity to ${ϵ}_{inn,sp}$, ${ϵ}_{out,sp}$, $L_{inn,sp}$, $L_{out,sp}$, and also to $T_{sp}$ (i.e., the vertical NS spacing)—see Equation (9). To understand when $f_{osc}$ variations become significant, we compare the obtained sensitivities, with HP and LP nodes, in

Table 4. Calculated percentage sensitivity values for oscillating frequency.

	${\mathit{ϵ}}_{\mathit{inn},\mathit{sp}}$	${\mathit{ϵ}}_{\mathit{out},\mathit{sp}}$	${\mathit{L}}_{\mathit{inn},\mathit{sp}}={\mathit{L}}_{\mathit{out},\mathit{sp}}$	${\mathit{L}}_{\mathit{inn},\mathit{sp}}$	${\mathit{T}}_{\mathit{sp}}$
20 nm	19.9%	24.8%	20.22%	10.51%	2.44%
30 nm	11.39%	13.34%	14.89%	5.31%	3.83%

.

Interestingly, the $f_{osc}$ sensitivity to all considered parameters but $T_{sp}$ is greater for the LP node than for the HP node. For $T_{sp}$, the two sensitivities are comparable, with the HP one greater than the LP one. We suppose that the larger $W_{NS}$ in the HP node mitigates and reduces the $f_{osc}$ sensitivity to ${ϵ}_{inn,sp}$, ${ϵ}_{out,sp}$, $L_{inn,sp}$, and $L_{out,sp}$. Indeed, the difference between HP and LP sensitivity is marked for $L_{inn,sp}$, meaning that a geometrical factor is the main cause of the sensitivity differences.

Furthermore, considering that power dissipation is the driving force toward the next technological node design, and considering that the future scaling of digital nodes is approaching the LP/memory nodes, we expect the future technological nodes to resemble the average LP one considered in this work more than the HP one. Thus, Table 4 shows that process control at the nano-scale strongly impacts the expected digital circuit performance, with a 10 to 20% performance variation possible due to different fabrication strategies or process variations. Again, the $f_{osc}$ sensitivity to the spacer dielectric constant is comparable or even greater than the one to the spacer length and alignment. Therefore, in future technological nodes, to address performance deterioration, the choice of alternative low-K materials to conventional SiO₂ or Si₃N₄ might become more important than controlling the photolithographic patterning at the sub-nm scale.

6. Conclusions

We adapted the well-established BSIM-CMG model for the NS-GAAFETs case by developing an ad hoc NS-GAAFET SPICE compact model. In particular, we preserved the efficient core solver of the BSIM-CMG compact model, and, by considering the different vertically stacked, rectangular section NS-GAAFET structure with respect to the FinFET one, we modified the resistive and capacitive networks of the model to account for the differences. Then, we employed the developed compact model to design the basic logic gate, i.e., the digital inverter, and to implement a five-stage RO to test the digital performance of the future sub-3-nm nodes in a standard framework. We focused our attention on the NS spacers, which are not present in conventional FinFETs, to understand their impact on digital circuit performance and to understand whether different design and fabrication strategies should be adopted in the near future.

Our results show that the spacer dielectric material choice is increasingly crucial for future digital nodes. The performance sensitivity to low-K dielectric materials is comparable to (HP nodes) or even greater (LP/memory nodes) than the performance sensitivity to photolithographic alignment and resolution at the sub-nm scale.

Our results motivate future research efforts and investments in alternative dielectric materials, rather than overcoming the photolithography approach’s intrinsic limits.