Research

13 pages, 4494 KiB

Open AccessArticle

A 1.25 MHz, 108 dB Chopped Sampling-Mixer-Based Impedance Spectroscopy SoC in 0.18-

μ m

CMOS

by Hyeonsik Kim, Heejune Lee and Jintae Kim

Electronics 2022, 11(24), 4130; https://doi.org/10.3390/electronics11244130 - 11 Dec 2022

Viewed by 1117

Abstract

This paper presents an electrochemical impedance spectroscopy (EIS) system-on-chip in 0.18-

μ m

CMOS, achieving a wide scan frequency range of 1.25 MHz. An on-chip direct digital frequency synthesizer generates a digital sine wave as well as in-phase and quadrature-phase clocks that are [...] Read more.

This paper presents an electrochemical impedance spectroscopy (EIS) system-on-chip in 0.18-

μ m

CMOS, achieving a wide scan frequency range of 1.25 MHz. An on-chip direct digital frequency synthesizer generates a digital sine wave as well as in-phase and quadrature-phase clocks that are synchronized to the sinewave. A chopped sampling mixer realizes lock-in detection without requiring quadrature sinewaves while suppressing low-frequency noise and offset. The receive utilizes a 12-bit pipelined SAR ADC operating in 5 MS/s in combination with a digital averaging filter to maximize the dynamic range. The measured performance shows that the prototype EIS chip achieves the highest frequency scan range with a comparable dynamic range of 108 dB and power consumption of 14 mW when compared with the previous state-of-the-art prototypes. Full article

(This article belongs to the Special Issue Mixed Signal Circuit Design)

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10 pages, 7774 KiB

Open AccessArticle

An 11-Bit 10 MS/s SAR ADC with C–R DAC Calibration and Comparator Offset Calibration

by Hoyong Jung, Eunji Youn and Young-Chan Jang

Electronics 2022, 11(22), 3654; https://doi.org/10.3390/electronics11223654 - 09 Nov 2022

Cited by 1 | Viewed by 1908

Abstract

An 11-bit 10 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) is proposed for low-power and small-area applications. A 10-bit differential capacitor–resistor (C–R) digital-to-analog converter (DAC) is used to minimize the area of a DAC. The use of a C–R DAC reduces the [...] Read more.

An 11-bit 10 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) is proposed for low-power and small-area applications. A 10-bit differential capacitor–resistor (C–R) digital-to-analog converter (DAC) is used to minimize the area of a DAC. The use of a C–R DAC reduces the capacitor area of a SAR ADC used CDAC by 75%. A capacitor calibration for the upper 5-bit capacitors of the C–R DAC is proposed to increase the linearity of the C–R DAC. To evaluate the proposed SAR ADC, an 11-bit 10 MS/s SAR ADC is implemented using a 180 nm 1-poly six-metal CMOS process with a supply of 1.8 V. The proposed SAR ADC has an effective number of bits (ENOBs) of 10.3 bits at a sampling rate of 10 MS/s for a 3.6-V_PP differential sinusoidal analog input with a frequency of 4.789 MHz. The measured ENOBs is 10.45 bits when the frequency of the analog input signal is 42.39 kHz. The proposed C–R DAC calibration including comparator offset calibration improves the performances of differential nonlinearity (DNL) and integral nonlinearity (INL) from −1/+1.26 LSBs and −1.98/+1.96 LSBs to −0.97/+0.85 LSBs and −0.79/+0.83 LSBs, respectively. Full article

(This article belongs to the Special Issue Mixed Signal Circuit Design)

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12 pages, 5637 KiB

Open AccessArticle

A Cost-Effective and Compact All-Digital Dual-Loop Jitter Attenuator for Built-Off-Test Applications

by Seungjun Kim, Junghoon Jin and Jongsun Kim

Electronics 2022, 11(21), 3630; https://doi.org/10.3390/electronics11213630 - 07 Nov 2022

Viewed by 1584

Abstract

A compact and low-power all-digital CMOS dual-loop jitter attenuator (DJA) for low-cost built-off-test (BOT) applications such as parallel multi-DUT testing is presented. The proposed DJA adopts a new digital phase interpolator (PI)-based clock recovery (CR) loop with an adaptive decimation filter (ADF) function [...] Read more.

A compact and low-power all-digital CMOS dual-loop jitter attenuator (DJA) for low-cost built-off-test (BOT) applications such as parallel multi-DUT testing is presented. The proposed DJA adopts a new digital phase interpolator (PI)-based clock recovery (CR) loop with an adaptive decimation filter (ADF) function to remove the jitter and phase noise of the input clock, and generate a phase-aligned clean output clock. In addition, by adopting an all-digital multi-phase multiplying delay-locked loop (MDLL), eight low-jitter evenly spaced reference clocks that are required for the PI are generated. In the proposed DJA, both the MDLL and PI-based CR are first-order systems, and so this DJA has the advantage of high system stability. In addition, the proposed DJA has the benefit of a wide operating frequency range, unlike general PLL-based jitter attenuators that have a narrow frequency range and a jitter peaking problem. Implemented in a 40 nm 0.9 V CMOS process, the proposed DJA generates cleaned programmable output clock frequencies from 2.4 to 4.7 GHz. Furthermore, it achieves a peak-to-peak and RMS jitter attenuation of –25.6 dB and –32.6 dB, respectively, at 2.4 GHz. In addition, it occupies an active area of only 0.0257 mm² and consumes a power of 7.41 mW at 2.4 GHz. Full article

(This article belongs to the Special Issue Mixed Signal Circuit Design)

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12 pages, 5469 KiB

Open AccessArticle

2nd-Order Pipelined Noise-Shaping SAR ADC Using Error-Feedback Structure

by Jihyun Baek, Juyong Lee, Jintae Kim and Hyungil Chae

Electronics 2022, 11(19), 3072; https://doi.org/10.3390/electronics11193072 - 26 Sep 2022

Cited by 2 | Viewed by 1659

Abstract

This paper presents a pipelined noise-shaping SAR (PLNS-SAR) ADC for high SNDR, wide bandwidth, and low power consumption. The proposed design achieves a sharp second-order NTF of an error feedback structure, without a multi-input comparator and additional residue amplifier. Additionally, the SNDR is [...] Read more.

This paper presents a pipelined noise-shaping SAR (PLNS-SAR) ADC for high SNDR, wide bandwidth, and low power consumption. The proposed design achieves a sharp second-order NTF of an error feedback structure, without a multi-input comparator and additional residue amplifier. Additionally, the SNDR is improved via zero optimization. Additionally, the speed is enhanced via prediction logic and alternately using the passive switched capacitor FIR filter. This consequently achieves the high-power efficiency of the ADC. The simulated SNDR is 79.97 dB; it achieves a 12.5-MHz BW at a 175-MHz sampling rate, with OSR of 7. The total power consumption of the ADC is 4.27 mW at a 1.1-V supply. The

{FoM}_{S, SNDR}

is 174.6 dB. The proposed structure achieves high resolution and wide bandwidth with good energy efficiency. Full article

(This article belongs to the Special Issue Mixed Signal Circuit Design)

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12 pages, 4530 KiB

Open AccessArticle

A 5.67 ENOB Vector Matrix Multiplier with Charge Storage FET Cells and Non-Linearity Compensation Techniques

by Jin-Young Hwang, Young-Taek Ryu and Kee-Won Kwon

Electronics 2022, 11(18), 2911; https://doi.org/10.3390/electronics11182911 - 14 Sep 2022

Viewed by 1096

Abstract

In this paper, we provide a thorough analysis and enhancement techniques of the linearity between the input voltage and output current in charge storage field effect transistor (FET) cells for a vector–matrix multiplier array in neural networks. A planar floating gate FET cell [...] Read more.

In this paper, we provide a thorough analysis and enhancement techniques of the linearity between the input voltage and output current in charge storage field effect transistor (FET) cells for a vector–matrix multiplier array in neural networks. A planar floating gate FET cell revealed superior linearity, because of boosting the floating gate using a drain voltage through capacitive coupling. If the coupling capacitance is extended by up to half of the gate capacitance, the coefficient of determination for linear regression is easily greater than 99.5%. However, the linearity of the charge trap FET, which keeps electrons in the insulating gate dielectric, must be compensated by either boosting the drain voltage, using a non-linear input driver, or supplying a quadratic current through an auxiliary path in the cell. Drain voltage boosting is limitedly effective over a small input range, while the auxiliary current path shows a coefficient of determination greater than 99.5% over a 500 mV input range. If the cell area matters, the charge trap FET with a diode connected FET as an auxiliary current path revealed the best performance, with an effective number of bits of 5.67, in a 21.3 F² cell area. Full article

(This article belongs to the Special Issue Mixed Signal Circuit Design)

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8 pages, 2250 KiB

Open AccessArticle

A 0.17 pJ/bit 28 Gb/s/pin Single-Ended PAM-4 Transmitter for On-Chip Short-Reach Unterminated Channels

by Soyeon Park and Jintae Kim

Electronics 2022, 11(16), 2525; https://doi.org/10.3390/electronics11162525 - 12 Aug 2022

Viewed by 2082

Abstract

This paper presents the design of a single-ended four-level pulse-amplitude modulation (PAM-4) transmitter for an on-chip short-reach unterminated channel. To achieve multi-output generation, a local voltage buffer consisting of a diode-connected device and a leaker transistor is introduced. By charge-sharing between a local [...] Read more.

This paper presents the design of a single-ended four-level pulse-amplitude modulation (PAM-4) transmitter for an on-chip short-reach unterminated channel. To achieve multi-output generation, a local voltage buffer consisting of a diode-connected device and a leaker transistor is introduced. By charge-sharing between a local reservoir capacitor and an unterminated channel, the proposed transmitter generates mid-level output voltages without using the DC current, thereby realizing multi-level signaling without significantly increasing the static current. A prototype chip was fabricated by 28 nm CMOS process, and the transmitter exhibits an energy efficiency of 0.17 pJ/bit at 28 Gb/s/pin, which is state-of-the-art energy efficiency as a multi-level transmitter having a data rate beyond 20 Gb/s. Full article

(This article belongs to the Special Issue Mixed Signal Circuit Design)

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12 pages, 1289 KiB

Open AccessArticle

A PVT-Insensitive Optimal Phase Noise Point Tracking Bias Calibration in Class-C VCO

by Gaim Jung, Siheon Seong and Minjae Lee

Electronics 2022, 11(4), 629; https://doi.org/10.3390/electronics11040629 - 17 Feb 2022

Cited by 1 | Viewed by 1820

Abstract

This paper presents a Class-C voltage-controlled oscillator (VCO) with bias voltage calibration that automatically finds the low-phase noise point and achieves robust start-up regardless of PVT variation. This VCO structure also has the bias circuit that compensates for temperature changes even when calibration [...] Read more.

This paper presents a Class-C voltage-controlled oscillator (VCO) with bias voltage calibration that automatically finds the low-phase noise point and achieves robust start-up regardless of PVT variation. This VCO structure also has the bias circuit that compensates for temperature changes even when calibration is not applied. Through these techniques, the problems of robust start-up and vulnerability to PVT variation, which are chronic problems of Class-C VCO, are overcome. The proposed VCO was designed in a 28 nm CMOS process. Simulation results show that this VCO has an operating range from 3.717 to 4.675 GHz, resulting in a frequency tuning range (FTR) of 22.8%. In addition, power consumption was 2.135 mW, phase noise at 1 MHz was −124.1 dBc/Hz, and the figure of merit (FoM) was −192.2 dBc/Hz. The chip area was very small at 0.196 mm

^{2}

. Full article

(This article belongs to the Special Issue Mixed Signal Circuit Design)

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15 pages, 7153 KiB

Open AccessArticle

Content-Addressable Memory System Using a Nanoelectromechanical Memory Switch

by Hyunju Kim, Mannhee Cho, Sanghyun Lee, Hyug Su Kwon, Woo Young Choi and Youngmin Kim

Electronics 2022, 11(3), 481; https://doi.org/10.3390/electronics11030481 - 07 Feb 2022

Cited by 3 | Viewed by 3445

Abstract

Content-addressable memory (CAM) performs a parallel search operation by comparing the search data with all content stored in memory during a single cycle, instead of finding the data using an address. Conventional CAM designs use a dynamic CMOS architecture for high matching speed [...] Read more.

Content-addressable memory (CAM) performs a parallel search operation by comparing the search data with all content stored in memory during a single cycle, instead of finding the data using an address. Conventional CAM designs use a dynamic CMOS architecture for high matching speed and high density; however, such implementations require the use of system clocks, and thus, suffer from timing violations and design limitations, such as charge sharing. In this paper, we propose a static-based architecture for a low-power, high-speed binary CAM (BCAM) and ternary CAM (TCAM), using a nanoelectromechanical (NEM) memory switch for nonvolatile data storage. We designed the proposed CAM architectures on a 65 nm process node with a 1.2 V operating voltage. The results of the layout simulation show that the proposed design has up to 23% less propagation delay, three times less matching power, and 9.4 times less area than a conventional design. Full article

(This article belongs to the Special Issue Mixed Signal Circuit Design)

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12 pages, 7328 KiB

Open AccessArticle

An N/M-Ratio All-Digital Clock Generator with a Pseudo-NMOS Comparator-Based Programmable Divider

by Jongsun Kim

Electronics 2022, 11(2), 261; https://doi.org/10.3390/electronics11020261 - 14 Jan 2022

Cited by 2 | Viewed by 2264

Abstract

A multiplying delay-locked loop (MDLL)-based all-digital clock generator with a programmable N/M-ratio frequency multiplication capability for digital SoC is presented. The proposed digital MDLL provides programmable N/M-ratio frequency multiplication using a new high-speed Pseudo-NMOS comparator-based programmable divider with small area and low power [...] Read more.

A multiplying delay-locked loop (MDLL)-based all-digital clock generator with a programmable N/M-ratio frequency multiplication capability for digital SoC is presented. The proposed digital MDLL provides programmable N/M-ratio frequency multiplication using a new high-speed Pseudo-NMOS comparator-based programmable divider with small area and low power consumption. The proposed MDLL clock generator can also provide a de-skew function by eliminating the phase offset problem caused by the propagation delay of the front divider in conventional N/M MDLL architectures. Fabricated in a 0.13-µm 1.2-V CMOS process, the proposed digital MDLL clock generates fully de-skewed output clock frequencies from 0.3 to 1.137 GHz with programmable N/M ratios of N = 1~32 and M = 1~16. It achieves a measured effective peak-to-peak jitter of 12 ps at 1.0 GHz when N/M = 8/1. It occupies an active area of only 0.034 mm² and consumes a power of 10.3 mW at 1.0 GHz. Full article

(This article belongs to the Special Issue Mixed Signal Circuit Design)

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