Search for Articles:
Title / Keyword
Author / Affiliation / Email
Journal
Article Type
 
 
Advanced Search
 
Section
Special Issue
Volume
Issue
Number
Page
 
4.7
2.9
Journals
Electronics
Special Issues
Mixed Signal Circuit Design, Volume II
share announcement

Mixed Signal Circuit Design, Volume II

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Circuit and Signal Processing".

Deadline for manuscript submissions: closed (30 January 2024) | Viewed by 3446

Special Issue Editor

Prof. Dr. Jongsun Kim

E-Mail Website
Guest Editor
School of Electronic & Electrical Engineering, Hongik University, Seoul 121-791, Republic of Korea
Interests: RFIC; MMIC; mmWave; CMOS; analog IC; 5G
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

Dear Colleagues,

Today, high-performance and energy-efficient electronic devices are mainly based on mixed-signal integrated circuits (ICs) that handle both analog and digital signal processing. Mixed-signal ICs containing both analog circuits and digital circuits are typically cost-effective solutions for building high-speed and low-power electronic systems. Recently, the complexity of mixed-signal design has been further exacerbated in heterogeneous integration of different dies for three-dimensional (3D) ICs. The importance of mixed-signal design in next-generation system-on-chip (SoC) systems is ever increasing.

This Special Issue focuses on advance analog, RF, and mixed-signal circuit designs. The topics of primary research include but are not limited to the following:

  • High-speed I/O circuits;
  • Advanced clocking circuits;
  • Data converters: ADCs and DACs;
  • Integrated sensor ICs;
  • Internet of Things (IoT) applications;
  • Low-power and low-voltage circuits;
  • RF circuits and building blocks;
  • Heterogeneous integration circuits and systems;
  • Power management integrated circuits (PMICs);
  • Signal integrity and power integrity techniques.

Prof. Dr. Jongsun Kim
Guest Editor

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • analog and mixed-signal circuits
  • wireline circuits
  • wireless circuits
  • data converters
  • memory circuits

Published Papers (4 papers)

Download All Papers
Order results
Result details
Show export options expand_more Show export options expand_less
Select all
Export citation of selected articles as:

Research

14 pages, 6888 KiB  
Article
A Quadrature Oscillator with a Frequency-Tuned Distributed RC Network Analysis
by Jahyun Koo and Cheonhoo Jeon
Electronics 2024, 13(5), 878; https://doi.org/10.3390/electronics13050878 - 25 Feb 2024
Viewed by 599
Abstract
This paper introduces an innovative two-stage distributed RC oscillator design, enhancing the noise performance and frequency stability for compact electronic devices. This work significantly reduces the comparator noise and improves system reliability by implementing a novel approach to increase the signal transition slope, [...] Read more.
This paper introduces an innovative two-stage distributed RC oscillator design, enhancing the noise performance and frequency stability for compact electronic devices. This work significantly reduces the comparator noise and improves system reliability by implementing a novel approach to increase the signal transition slope, coupled with optimized resistor and capacitor configurations. The study employs a quadrature oscillator topology and a precise reference voltage generation method, effectively addressing the challenges of mismatch and noise performance. A 469.2 kHz quadrature oscillator with two-stage distributed RC is implemented with a 0.18 μm CMOS process, achieving a FoM of −160 dBc/Hz at 100 Hz with a stable −20 dB roll-off in the phase noise and an Allan deviation floor of less than 0.7 ppm. Full article
(This article belongs to the Special Issue Mixed Signal Circuit Design, Volume II)
►▼ Show Figures

Figure 1

14 pages, 5443 KiB  
Article
Charge-Domain Static Random Access Memory-Based In-Memory Computing with Low-Cost Multiply-and-Accumulate Operation and Energy-Efficient 7-Bit Hybrid Analog-to-Digital Converter
by Sanghyun Lee and Youngmin Kim
Electronics 2024, 13(3), 666; https://doi.org/10.3390/electronics13030666 - 5 Feb 2024
Viewed by 867
Abstract
This study presents a charge-domain SRAM-based in-memory computing (IMC) architecture. The multiply-and-accumulate (MAC) operation in the IMC structure is divided into current- and charge-domain methods. Current-domain IMC has high-power consumption and poor linearity. Charge-domain IMC has reduced variability compared with current-domain IMCs, achieving [...] Read more.
This study presents a charge-domain SRAM-based in-memory computing (IMC) architecture. The multiply-and-accumulate (MAC) operation in the IMC structure is divided into current- and charge-domain methods. Current-domain IMC has high-power consumption and poor linearity. Charge-domain IMC has reduced variability compared with current-domain IMCs, achieving higher linearity and enabling energy-efficient operation with fewer dynamic current paths. The proposed IMC structure uses a 9T1C bitcell considering the trade-off between the bitcell area and the threshold voltage drop by an NMOS access transistor. We propose an energy-efficient summation mechanism for 4-bit weight rows to perform energy-efficient MAC operations. The generated MAC value is finally returned as a digital value through an analog-to-digital converter (ADC), whose performance is one of the critical components in the overall system. The proposed flash-successive approximation register (SAR) ADC is designed by combining the advantages of flash ADC and SAR ADC and outputs digital values at approximately half the cycle of SAR ADC. The proposed charge-domain IMC is designed and simulated in a 65 nm CMOS process. It achieves 102.4 GOPS throughput and 33.6 TOPS/W energy efficiency at array size of 1 Kb. Full article
(This article belongs to the Special Issue Mixed Signal Circuit Design, Volume II)
►▼ Show Figures

Figure 1

13 pages, 4268 KiB  
Article
A Fast-Lock Variable-Gain TDC-Based N/M-Ratio MDLL Clock Multiplier
by Chaeyoung Jang and Jongsun Kim
Electronics 2023, 12(19), 4136; https://doi.org/10.3390/electronics12194136 - 4 Oct 2023
Viewed by 815
Abstract
A variable-gain time-to-digital converter (TDC)-based multiplying delay-locked loop (MDLL) clock multiplier featuring fast-locking and programmable N/M-ratio frequency multiplication capability is presented in this paper. The proposed all-digital programmable N/M-ratio MDLL achieves fast-locking capability by adopting a new variable-gain TDC. In conventional fixed-gain TDC-based [...] Read more.
A variable-gain time-to-digital converter (TDC)-based multiplying delay-locked loop (MDLL) clock multiplier featuring fast-locking and programmable N/M-ratio frequency multiplication capability is presented in this paper. The proposed all-digital programmable N/M-ratio MDLL achieves fast-locking capability by adopting a new variable-gain TDC. In conventional fixed-gain TDC-based MDLLs, the lock time increases as the value of the multiplication factor N decreases. However, the proposed variable-gain TDC can minimize the MDLL lock time by adjusting the TDC gain according to the change in N value. Implemented in a 40 nm 1.1-V CMOS process, the proposed all-digital MDLL clock multiplier generates output clock frequencies ranging from 0.65 to 3.2 GHz, with programmable N/M ratios of N = 5 to 16 and M = 1 to 8. It achieves a fast lock time of only 3 × M (=9) reference clock cycles when N/M = 10/3 at 2.0 GHz and demonstrates a simulated peak-to-peak jitter of 3.16 ps at 3.2 GHz when N/M = 16/3. Additionally, it occupies an active area of only 0.02 mm2 (=200 μm × 100 μm) and consumes a power of 2.3 mW at 1.0 GHz. Full article
(This article belongs to the Special Issue Mixed Signal Circuit Design, Volume II)
►▼ Show Figures

Figure 1

13 pages, 2907 KiB  
Article
Dynamic Power Reduction in TCAM Using Advanced Selective Pre-Charging of Match Lines
by Su-Yeon Doo and Kee-Won Kwon
Electronics 2023, 12(17), 3691; https://doi.org/10.3390/electronics12173691 - 31 Aug 2023
Viewed by 755
Abstract
In this paper, we propose a power-efficient memory operation, selective match line precharge, based on an analysis of power consumption in ternary content-addressable memory (TCAM). A statistical study reveals that, on average, 58% of power dissipation related to the match line operation is [...] Read more.
In this paper, we propose a power-efficient memory operation, selective match line precharge, based on an analysis of power consumption in ternary content-addressable memory (TCAM). A statistical study reveals that, on average, 58% of power dissipation related to the match line operation is saved by deactivating the unnecessary swing of match lines. The improvement has been simulated and proved using 180 nm CMOS technology. Full article
(This article belongs to the Special Issue Mixed Signal Circuit Design, Volume II)
►▼ Show Figures

Figure 1

Show export options expand_more Show export options expand_less
Select all
Export citation of selected articles as:
 
Displaying articles 1-4
Back to TopTop