A Fast-Lock Variable-Gain TDC-Based N/M-Ratio MDLL Clock Multiplier

Abstract

A variable-gain time-to-digital converter (TDC)-based multiplying delay-locked loop (MDLL) clock multiplier featuring fast-locking and programmable N/M-ratio frequency multiplication capability is presented in this paper. The proposed all-digital programmable N/M-ratio MDLL achieves fast-locking capability by adopting a new variable-gain TDC. In conventional fixed-gain TDC-based MDLLs, the lock time increases as the value of the multiplication factor N decreases. However, the proposed variable-gain TDC can minimize the MDLL lock time by adjusting the TDC gain according to the change in N value. Implemented in a 40 nm 1.1-V CMOS process, the proposed all-digital MDLL clock multiplier generates output clock frequencies ranging from 0.65 to 3.2 GHz, with programmable N/M ratios of N = 5 to 16 and M = 1 to 8. It achieves a fast lock time of only 3 × M (=9) reference clock cycles when N/M = 10/3 at 2.0 GHz and demonstrates a simulated peak-to-peak jitter of 3.16 ps at 3.2 GHz when N/M = 16/3. Additionally, it occupies an active area of only 0.02 mm² (=200 μm × 100 μm) and consumes a power of 2.3 mW at 1.0 GHz.

1. Introduction

Multiplying delay-locked loops (MDLLs) [1,2,3,4,5,6,7,8,9,10] have addressed the stability issues of traditional phase-locked loops (PLLs) [11,12,13] and are emerging as a new low-jitter on-chip clock multiplier due to their periodic jitter reduction characteristics. Most ring-oscillator (RO)-based on-chip clock multipliers require a wide frequency range, fast locking, and rapid power-on time features for dynamic frequency scaling (DFS) and power reduction. Consequently, fast-locking (or fast-settling) PLL/MDLL-based clocking circuits have played a key role in reducing system power consumption across various system clocking and I/O interface applications for system-on-chip (SoC), processors and memory designs [4,6,14,15,16,17].

Several fast-lock all-digital PLLs have been introduced [16,17,18,19], but many of them exhibit long lock times of tens or hundreds of reference clock cycles or more. In the realm of MDLLs, fast-lock techniques utilizing a successive approximation register (SAR)-based binary search [4,20] or time-to-digital converter (TDC) [5,6] have been proposed. [4] achieved a lock time of 40 reference cycles and [6] reduced the lock time to 6 reference cycles using a gain-matched TDC architecture. Nonetheless, [6] has the disadvantage of a fixed multiplication factor N of only 16, thus lacking programmable N/M-ratio multiplication. Additionally, when the fixed N value is utilized in this gain-matched TDC architecture, the TDC gain remains fixed. In such instances, altering N arbitrarily could potentially increase the MDLL lock time.

In this paper, we present a variable-gain TDC-based programmable MDLL clock multiplier with a fast-locking and de-skewed N/M-ratio frequency multiplication capability. The proposed variable-gain TDC is employed to measure the initial phase error of the N/M-ratio MDLL, minimizing MDLL lock time by adjusting the TDC gain according to the changes in the multiplication factor N. The proposed MDLL clock multiplier is implemented in a 40 nm 1.1-V CMOS process. It generates output clock frequencies ranging from 0.65 to 3.2 GHz, with programmable N/M ratios of N = 5 to 16 and M = 1 to 8. Achieving a fast-lock time of only 9 reference clock cycles when N/M = 10/3 at 2.0 GHz, this marks the first TDC-based N/M-ratio MDLL utilizing a variable-gain TDC to achieve fast-locking time regardless of changes in the multiplication and division factors (N or M value).

This paper is organized as follows: Section 2 introduces the architecture of conventional fast-lock digital MDLLs. Section 3 presents the architecture and circuit design of the proposed variable-gain TDC-based all-digital MDLL clock multiplier. Section 4 shows the experimental results, and Section 5 presents the conclusion.

2. Traditional Fast-Lock Digital MDLL Clock Multipliers

Figure 1a illustrates a simplified block diagram of a traditional phase detector (PD)-based digital MDLL clock multiplier [1,2,3,7,8], comprising a PD, a digital loop filter (DLF), a digitally controlled oscillator (DCO), a feedback divider (N = multiplication factor), and a select logic. The DCO includes a 2-to-1 multiplexer (MUX) and a total of K delay cells. The PD provides the phase comparison information of the input signal (CLK_IN) and output signal (CLK_OUT) to the DLF. As depicted in Figure 1b, the MDLL operates at the maximum frequency in the initial state and possesses the largest initial phase error (=∆t). As the MDLL operates, the digital code word (DCW) signal of the DLF adjusts the propagation delay, t_dco, of the delay cells. This adjustment eliminates the initial phase error ∆t, causing the output frequency to become N times the input frequency (f_out = N × f_ref). The select logic generates the sel signal, controlling the MUX. This action causes the DCO to alternate between an open loop (=reference injection mode) and a closed loop (=ring oscillator mode), facilitating entry into a lock state [4].

When the propagation delay for traversing the Mux and K delay cells within the DCO is t_dco, the output frequency of this MDLL can be approximated as 1/(2 × t_dco). The change in t_dco due to variations in the DCW value can be defined as the DCO gain (K_DCO). In digital MDLLs with a fixed multiplication factor N, a constant DCO gain value is employed. However, to achieve fast-lock characteristics with programmable N and adjustable output frequency, the DCO gain should not remain fixed; rather, it should be variable in accordance with N. This adaptability is crucial because the initial phase error ∆t, as shown in Figure 1b, fluctuates based on the value of the multiplication factor N in MDLL clock multipliers.

To further enhance the lock time of MDLL clock multipliers, a time-to-digital converter (TDC) was introduced [5,6]. Figure 2 shows a simplified block diagram of a conventional TDC-based MDLL clock multiplier [6]. During the initial operation of this TDC-based MDLL, the TDC detects the initial phase error (∆t shown in Figure 1b), rapidly adjusts t_dco to the lock position, and then deactivates the TDC to reduce power while maintaining the phase lock condition using the PD [6]. In TDC-based MDLLs, it is established that a fast lock is feasible when the DCO gain (K_DCO) and the TDC gain (K_TDC) align as follows [6]:

K_TDC = 1/K_DCO (or K_TDC · K_DCO = 1)

(1)

However, conventional TDC-based MDLLs with a fixed multiplication factor N encounter an issue in that both the K_DCO and K_TDC values remain constant. Consequently, the lock time will increase if N is altered arbitrarily within the existing fixed-gain TDC-based MDLL structure.

3. Proposed Variable-Gain TDC-Based All-Digital N/M-Ratio MDLL Clock Multiplier

3.1. Proposed All-Digital N/M-Ratio MDLL Architecture

In this paper, we present a fast-lock all-digital programmable N/M ratio MDLL clock multiplier. The proposed MDLL employs a new variable-gain TDC to measure the initial phase error of the N/M-ratio MDLL [21]. A technique to achieve fast-lock time using TDC when the frequency multiplication factor N is fixed was introduced in [5] and [6]. However, this method becomes inapplicable when the frequency multiplication factor N is variable. To tackle this challenge, the proposed variable-gain TDC generates the TDC output code by adjusting the TDC resolution based on the multiplication factor N.

Figure 3a illustrates the proposed TDC-based all-digital N/M-ratio MDLL clock multiplier. It consists of a DCO, two programmable dividers (front divider /M and feedback divider /N), a select logic, a variable-gain TDC, a bang-bang phase detector (BBPD), two digital loop filters (11-bit DLF#1 and DLF#2), a second-order delta-sigma modulator (DSM), two binary-to-thermometer decoders (4-to-15 coarse decoder, a 2-to-3 DSM decoder), a harmonic lock detector, and an enable controller. The DCO consists of a 3-to-1 MUX, a coarse delay line, and a Fine + DSM delay line. The coarse delay line comprises sixteen serial delay cells, each NAND-based delay cell [4] exhibiting a propagation delay of t_coarse. The variable delay value of the Fine + DSM delay line corresponds to one t_coarse. The Fine + DSM delay line utilizes a 7-bit digital feedback delay element (DFE) [4]. The proposed MDLL operates at the maximum frequency with a minimum DCO delay at the outset of operation.

The proposed variable-gain TDC boasts an extensive detection range and high resolution, adopting a Cyclic Vernier TDC [5,6] structure. The TDC’s resolution is adapted according to the value of the frequency multiplication factor N. As the N value decreases, the TDC’s delay resolution diminishes, increasing both the K_TDC and output TDC code value. By using external inputs N [3:0] and M [1:0], the programmable output clock frequency can be tuned via f_out = (N/M)f_ref, where the integer multiplication factor N ranges from 5 to 16, and the division factor M spans from 1 to 8.

The proposed TDC-based all-digital N/M-ratio MDLL clock multiplier operates in two modes: TDC mode and BBPD mode. Upon MDLL activation, the TDC generates the TDC [10:0] signal, detecting the time difference between the N + 1st rising edge of CLK_OUT and the M + 1st rising edge of CLK_IN, as depicted in Figure 3b, where N/M = 7/3 for illustrative purposes. This TDC measurement operates at most twice, reducing the initial phase error to approximately 20 ps, subsequently generating the TDC_Lock signal to conclude the TDC mode and commence the BBPD mode. The 11-bit DLF#1 produces the DLF [10:0] signal, necessary for controlling the coarse delay line and Fine + DSM delay line of the DCO. The coarse 4-to-15 thermometer decoder takes the 4-bit most significant bits (MSBs), DLF [10:7], of DLF#1 as input and produces the thermometer codes DCW [14:0] for coarse delay line control. The Fine + DSM delay line adjustment is governed by DLF [6:0], the least-significant bits (LSBs) of the 11-bit DLF#1, with a resolution of t_coarse/128.

In BBPD mode, if the phase error drops below 1 LSB of the DCO resolution, the Lock Detector triggers the DSM_ON signal to activate the second-order DSM. The DSM receives the output DCWF [2:0] signal of DLF#2 and converts the Dither [2:0] signal through the 2-to-3 DSM thermometer decoder. The high-speed Dither [2:0] signal controls the dithering capacitors inside the Fine + DSM delay line to mitigate MDLL’s dithering jitter component and enhance jitter performance.

The proposed MDLL achieves anti-harmonic lock capability using the harmonic lock detector shown in Figure 3b. At the beginning of operation, a situation where K_DCO > K_TDC may occur due to issues such as process, voltage, and temperature (PVT) variations or non-linearity between the TDC and DCO. During this time, if there is a sudden and significant increase in DCO delay, the MDLL may become locked to the harmonic reference edges of the input clock (CLK_IN) [4]. In the proposed MDLL, the harmonic lock condition is detected using the harmonic lock detector, and the DCO delay is intentionally reduced by decreasing the DLF#1 code value to achieve proper phase and frequency tracking.

3.2. Proposed Variable-Gain TDC

Figure 4a depicts the block diagram of the proposed variable-gain TDC. The TDC incorporates a Reset generator, an EN_slow generator, an EN_fast generator, a TDC lock detector, a slow oscillator, a fast oscillator, a comparator, two multiplexers, a 6-bit coarse counter, a 5-bit fine counter, and a 11-bit up/down counter. The slow oscillator and fast oscillator contain programmable capacitor arrays #1 and #2, respectively. The multiplication factor N (N [3:0], Nb [3:0]) is used to control the capacitor arrays of the two oscillators according to the N value. In this way, the periods of the two oscillator outputs, sosc and fosc, can be changed; therefore, the gain of the TDC can be adjusted variably according to the value of N. The EN_slow generator detects the (N + 1)st rising edge of the output clock (CLK_OUT) and generates the EN_slow signal to enable the slow oscillator, while the EN_fast generator detects the (M + 1)st rising edge of the input clock (CLK_IN) to generate the EN_fast signal that enables the fast oscillator. The number of sosc signals is counted from the rising edge of the EN_slow signal to the rising edge of the EN_fast signal and is stored in the 6-bit coarse counter. Additionally, the fosc signal is counted from the rising edge of the EN_fast signal to the rising edge of the Detect signal, and the value is stored in the 5-bit fine counter. The comparator is used to detect the moment when the rising edge of the fosc signal becomes faster in phase than the rising edge of the sosc signal. The 11-bit counter combines the values of the coarse counter and fine counter to generate the final TDC output, TDC [10:0]. The proposed TDC is based on a Cyclic Vernier structure [5,6] and offers high resolution while retaining the advantage of a wide detection range.

Figure 4b shows the operational process of the proposed variable-gain TDC, featuring multiplication and division factors N = 11 and M = 5, respectively. Upon MDLL activation, the proposed TDC measures the initial phase error during the first M cycle. It evaluates the initial phase error (=∆t) between the (N + 1)st rising edge of CLK_OUT and the (M + 1)st rising edge of CLK_IN. The N<3:0>/Nb<3:0> signals, used to program the multiplication factor N, also serve to adjust the TDC’ gain, K_TDC. These signals control the capacitive loads (capacitor array #1 and #2) of the fast and slow oscillators within the TDC, altering the period of the two oscillators. Consequently, a TDC with variable K_TDC can be realized based on the value of N. It is apparent that the TDC code measured in the first M cycle is applied to the DCO in the second M cycle. Consequently, the output CLK_OUT signal in the third M cycle is precisely synchronized in its frequency and phase with the input CLK_IN, yielding a frequency of 11/5 times. It takes two M cycles to generate TDC [10:0], and in the subsequent M cycle, the TDC [10:0] signal is applied to the DCO, requiring a total of three M cycles for phase locking this MDLL.

Figure 5a provides a more detailed view of the operation of the proposed variable-gain TDC-based MDLL when N is adjusted from 8 to 4 for simplicity. Here, for the sake of simplicity, we assume M = 1 and the maximum N value is 8. As previously mentioned, this MDLL begins operation at the highest frequency. Additionally, the TDC gain (=K_{TDC_Fixed}) must be designed to ensure that the (N + 1)st rising edge of CLK_OUT precedes the (M + 1)st rising edge of CLK_IN, especially at the maximum N (=8 in this case), to avoid harmonic lock issues. Consequently, as shown in Figure 5a, the initial phase error ∆t corresponds to t_A when N = 8. Moreover, as N decreases from 8 to 4, the initial phase error increases to t_B, where t_A < t_B.

In the left side of Figure 5b, if a fixed-gain TDC, maintaining an unvarying TDC gain (=K_{TDC_Fixed}) regardless of N, is employed, the output TDC code (TDC [10:0]) undergoes a slight change from Code A to Code B as N transitions from 8 to 4. In this scenario, Coad A < Coad B. Should the TDC code necessary to lock the MDLL with a single TDC measurement for rapid locking be Code C, then the Code B value significantly deviates from Code C. Consequently, this necessitates repeated TDC measurement, resulting in an extended MDLL lock time.

To overcome the issue of increased lock time in conventional fixed-gain TDC-based MDLLs, this paper introduces a novel variable-gain TDC-based MDLL. As illustrated in the right portion of Figure 5b, the proposed variable-gain TDC employs a K_{TDC_V8} gain when N is 8. When N transitions from 8 to 4, the TDC gain elevates by K_{TDC_V4}, enabling the generation of the Code C value essential for fast locking in a single TDC measurement.

4. Experimental Results

The proposed variable-gain TDC-based N/M-ratio MDLL clock multiplier was implemented in a 40 nm 1.1-V CMOS process. Figure 6 illustrates the chip layout of the proposed MDLL clock multiplier, showcasing an active core area of only 0.02 mm² (=200 μm × 100 μm). The proposed MDLL provides an output clock frequency range of 0.65-to-3.2 GHz with programmable N/M multiplication ratios, where the multiplication factor N spans from 5 to 16, and the division factor M ranges from 1 to 8.

Figure 7 displays the post-layout simulated locking process of the proposed variable-gain TDC-based MDLL, operating at 2.0 GHz with a multiplication ratio of N/M = 10/3. Following the MDLL’s activation at 5 ns, the TDC begins operation, measuring the initial phase error (∆t = 2.11 ns) during the first M cycle. It is evident that the generated TDC code is applied to the DCO in the second M cycle and achieves phase locked in the third M cycle. In summary, the lock time of the proposed MDLL is 3 × M reference clock cycles, and the phase error between the input and output clocks at that moment is less than 20 ps.

Once the TDC_Lock signal emerges in the fourth M cycle, the TDC deactivates, initiating the BBPD mode. Subsequently, the DSM_ON signal is enabled to further diminish the dithering jitter component.

Figure 8 presents a post-layout simulation result that clearly illustrates the initial locking process of the proposed MDLL including the operation of the front (M = 5) and feedback (N = 14) dividers. The proposed MDLL achieves phase lock in a single TDC measurement, resulting in a lock time of 3 × M = 15 reference clock cycles when M = 5. If the phase error is not reduced to less than 20 ps in the first TDC measurement, an additional TDC measurement is performed, leading to a lock time of 2 × 3 × M cycles in this case.

Figure 9 presents post-layout simulation results showing the period and frequency ranges of the proposed DCO corresponding to the DLF [10:0] code. The clock period of the DCO, as depicted in Figure 3, spans from 283.5 ps to 1.529 ns, corresponding to a frequency range of 646 MHz to 3.52 GHz. In a digital DCO design, non-linear behavior may arise due to the different circuit configurations of the coarse delay cell and the Fine + DSM delay cell. While the proposed DCO predominantly exhibits linear characteristics, moments of non-linearity occur when the DCW code value changes. If TDC measurement is performed during this non-linear period at the beginning of the operation, achieving phase lock with just one TDC measurement may not be possible, leading to the need for an additional TDC measurement and resulting in an increase in lock time. To mitigate this issue, it is advisable to design the DCO with linear characteristics across the entire period range as much as possible.

Figure 10 demonstrates simulation results regarding the number of TDC measurements for two types of TDC-based MDLLs (variable-gain TDC and fixed-gain TDC) when N changes from 16 to 9. Here, an initial maximum N value of 16 is assumed. In the fixed-gain TDC-based MDL, an N transitions from 16 to 9; it can be seen that the fixed-gain TDC-based MDLL achieves target frequency lock through 5 TDC measurements. On the contrary, for the variable-gain TDC-based MDLL, even with N changing from 16 to 9, the MDLL attains target frequency lock with just a single TDC measurement.

Figure 11a,b show the simulated 3.2 GHz peak-to-peak (p–p)/root-mean-square (RMS) jitter and reference spur performance of the proposed MDLL clock multiplier, employing a multiplication ratio of N/M = 16/3 and f_ref = 600 MHz. It accomplishes a p–p output clock jitter of 3.16 ps and an RMS jitter of 601 fs. It also achieves a reference spur of −44 dBc. The proposed MDLL consumes 2.3 mW at 1 GHz.

Table 1. Fast-lock MDLL performance summary and comparisons.

Reference	[4] TCAS-II 18	[5] * Electronics 21	[6] Access 22	[20] TCAS-I 08	This Work *
Process and Supply	65 nm/1.0 V	65 nm/1.0 V	40 nm/1.1 V	350 nm/3.3 V	40 nm /1.1 V
Output Freq. range [GHz]	0.7–2.4	2.0–3.0	1.6–3.2	0.06–0.45	0.65–3.2
Search algorithm	SAR	TDC	TDC	Modified SAR
Fractional-ratio (N/M) multiplication capability	Yes	No	No	No	Yes
Multiplication factor (N only or N/M)	N = 1, 4, 5, 8, 10 M = 1, 2, 3	N = 32 (N only)	N = 16 (N only)	N = 2~15 (N only)	N = 5~16 M = 1~8
p–p jitter [ps]	22 @ 2 GHz, N/M = 8/2	17.46 @ 2.4 GHz, N = 32	28.01 @ 3.2 GHz, N = 16	37.8 @ 0.45 GHz,	3.16 @ 3.2 GHz, N/M = 16/3
Power [mW]	3.31 @1 GHz	3.3 @2.4 GHz	3.56 @1.6 GHz	17 @0.45 GHz	2.3 @1 GHz
Active area [mm2]	0.019	0.043	0.024	0.216	0.02
Lock time [Ref. clock cycles]	40 (@ M = 1)	15	6	16	9 (=3 × M, @ M = 3)

* Simulation results.

outlines the performance summary and comparisons with previous fast-lock MDLL clock multipliers [4,5,6,20] featuring programmable N or N/M frequency multiplication ratios. In comparison to the fast-lock MDLLs in Table 1, the proposed variable-gain TDC-based MDLL achieves a rapid lock time of 3 × M (=9 at M = 3) cycles for different N/M ratios, showcasing a distinctive capability absent in other MDLLs.

5. Conclusions

In this paper, we introduce a novel variable-gain TDC-based N/M-ratio MDLL clock multiplier equipped with fast-lock capabilities. By incorporating the new variable-gain TDC, the proposed all-digital MDLL clock multiplier adheres to the K_TDC = 1/K_DCO relationship, regardless of changes in N value. As a result, it gains the advantages of a rapidly achieving phase and frequency lock through a single TDC measurement. Implemented in a 40 nm 1.1-V CMOS process, the proposed all-digital MDLL operates within a frequency range of 0.65 to 3.2 GHz. Occupying an active area of only 0.02 mm² and consuming only 2.3 mW at 1.0 GHz, it provides programmable N/M multiplication ratios of N = 5~16 and M = 1~8. Additionally, it achieves fast-lock time of just 3 × M (=9 at M = 3) reference clock cycles at 2 GHz with N/M = 10/3. The simulated p–p jitter is 3.16 ps when N/M = 16/3 at 3.2 GHz.