Advanced Integrated Circuit Technology and Application

A special issue of Applied Sciences (ISSN 2076-3417). This special issue belongs to the section "Electrical, Electronics and Communications Engineering".

Deadline for manuscript submissions: closed (20 February 2023) | Viewed by 5465

Special Issue Editor

Electrical and Computer Engineering Department, California State University, Fullerton, CA 92831, USA
Interests: analog/power/mixed-signal integrated circuit design; VLSI design; current-mode analog signal processing

Special Issue Information

Dear Colleagues,

This Special Issue offers scientists, engineers and researchers an excellent opportunity to present the latest research results, ideas, developments and applications. We are inviting contributions to a Special Issue of papers related to integrated circuit design, including theory, methods and applications in computing, consumers and control.

The success and popularity of integrated circuits (ICs) is related to the constant improvement of chip performance by IC manufacturers. With the continuous improvement of the complementary metal oxide semiconductor (CMOS) technology library and wafer fabrication technology, the CMOS process has reached its theoretical, practical and economic limits. Therefore, on the basis of maintaining the original chip functions, reducing the cost of integrated circuits has become an inevitable issue. IC designers and IC manufacturers are moving towards shrinking chip size, developing new chip materials, improving transistor structures, migrating integrated circuits to larger diameter silicon wafers, increasing wafer yield, increasing semiconductor factory automation, adopting 3D integrated circuits, using advanced IC packaging and improving system drivers.

In the last five years, IC design has seen exponential improvements in IC productivity and performance. Despite the increasing difficulty of improving chip performance, the IC design industry will continue to overcome the obstacles that lie ahead of it. Reducing chip size, increasing wafer diameter and increasing production yield have physical, statistical or economic constraints. As a result, the IC design industry will continue to advance technological advancements to address these limitations in order to continue to improve the performance and productivity of existing processes.

Potential topics include but are not limited to:

  • Low power analog circuits;
  • Power circuits;
  • Energy harvesting circuits;
  • Automotive integrated circuits;
  • Biomedical integrated circuits;
  • Wireless communication circuits;
  • Sensor applications;
  • AIoT networks;
  • Artificial intelligence circuits;
  • Embedded Systems;

Dr. Yitsen Ku
Guest Editor

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Applied Sciences is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Published Papers (3 papers)

Order results
Result details
Select all
Export citation of selected articles as:

Research

12 pages, 6800 KiB  
Communication
An Equal Precision Programmed Cymometer Design Using Low-Power Technique
by Yuan Liu, Jian Tang, Chen Feng, Chen Zhang, Yuwei Xue, Lei Zhang, Shuxi Xu, Jian Wang, Fang Dai and Ning Wang
Appl. Sci. 2023, 13(8), 5173; https://doi.org/10.3390/app13085173 - 21 Apr 2023
Viewed by 1028
Abstract
Based on equal precision frequency measurement and pulse counting technique, a multi-period synchronous frequency measurement method is proposed in this paper. A programmed cymometer is designed with a full frequency band with equal precision measurement and improved measurement accuracy. In addition to adopting [...] Read more.
Based on equal precision frequency measurement and pulse counting technique, a multi-period synchronous frequency measurement method is proposed in this paper. A programmed cymometer is designed with a full frequency band with equal precision measurement and improved measurement accuracy. In addition to adopting a low-power gate-control clock technique, the strong stability of our design is also carried out through the filtering of interference signals. Finally, the designed circuit is implemented with FPGA. The experimental results show that the static power consumption of the programmable frequency meter testing platform designed after continuous operation for 100 h is only 0.56 W, and the input impedance is 1 M Ω/40 pF. At the same time, the errors of frequency, cycle measurement, duty cycle measurement, and time interval are within a reasonable range. In addition, the measurement accuracy requirements for various indicators can also be met at a maximum frequency of 100 MHz. Therefore, this work can provide a feasible design method for low-power consumption electrical systems that are easy to replicate. Full article
(This article belongs to the Special Issue Advanced Integrated Circuit Technology and Application)
Show Figures

Figure 1

14 pages, 5773 KiB  
Communication
A New Control Scheme for the Buck Converter
by Hsiao-Hsing Chou, Jian-Yu Chen, Tsung-Hu Tseng, Jun-Yi Yang, Xuan Yang and San-Fu Wang
Appl. Sci. 2023, 13(3), 1991; https://doi.org/10.3390/app13031991 - 03 Feb 2023
Cited by 2 | Viewed by 1649
Abstract
In this paper, a new control scheme for buck converters was proposed. The buck converter utilizes the dual control loop to improve transient response and has the constant switching frequency. The control scheme is mainly as follows: (a) The switch-ON time is regulated [...] Read more.
In this paper, a new control scheme for buck converters was proposed. The buck converter utilizes the dual control loop to improve transient response and has the constant switching frequency. The control scheme is mainly as follows: (a) The switch-ON time is regulated by the constant frequency mechanism. (b) The switch-OFF time is regulated by the output voltage. The spec/features of the proposed converter are listed as: (1) The buck converter has an output of 1.0–2.5 V for the input of 3.0–3.6 V. The load current ranges from 100 mA to 500 mA. (2) The actual current sensor is not required. (3) The simulation results show that the recovery time is less than 1.6 μs during load changes. (4) The variation in switching frequency is smaller than 1.05% over the output range of 1.0–2.5 V. (5) This circuit can be fabricated in future by UMC 0.18 μm 1P6M CMOS processes. This paper depicts the control scheme, theoretical analysis, and implementation. Full article
(This article belongs to the Special Issue Advanced Integrated Circuit Technology and Application)
Show Figures

Figure 1

17 pages, 626 KiB  
Article
On Noise Modeling of Capacitive Feedback Transimpedance Amplifiers in CMOS
by Agata Romanova and Vaidotas Barzdenas
Appl. Sci. 2022, 12(19), 10186; https://doi.org/10.3390/app121910186 - 10 Oct 2022
Cited by 1 | Viewed by 1971
Abstract
The work reports on the development of a detailed noise current model for a low-noise capacitive feedback transimpedance amplifier (TIA) in CMOS. The proposed TIA circuit implements the programmable-gain using an array of discretely controlled feedback capacitors and resistances in the biasing circuit [...] Read more.
The work reports on the development of a detailed noise current model for a low-noise capacitive feedback transimpedance amplifier (TIA) in CMOS. The proposed TIA circuit implements the programmable-gain using an array of discretely controlled feedback capacitors and resistances in the biasing circuit and is originally designed bearing in mind low-noise requirements for optical time-domain reflectometer (OTDR) applications with the base gain of 10 kΩ at 1 GHz bandwidth and noise levels below 5.0 pA/Hz. The newly developed model for input-referred noise current spectral density complements the previously suggested transimpedance gain model and takes into account both the primary and secondary noise sources so far ignored in the models known in the literature. The proposed noise model consists of five terms and includes the effects caused by biasing components of the input stage and the noise shaping from the source follower. The performance of the developed noise model is evaluated using the post-layout simulation in 0.18 μm CMOS and 0.25 μm BiCMOS technologies, and a close match of the proposed model is demonstrated in the results of the post-layout simulation with the noise level below 1.8 pA/Hz for the base gain configuration in CMOS. A comparison to available noise models from the literature confirms that previously known noise models for this promising TIA architecture omitted important noise components present in practical and physically realizable circuits and, therefore, resulted in underestimating the base noise level by a factor of two to three, while completely ignoring the flicker noise mapping in the low-frequency range. Full article
(This article belongs to the Special Issue Advanced Integrated Circuit Technology and Application)
Show Figures

Figure 1

Back to TopTop