A Power-Gated 8-Transistor Physically Unclonable Function Accelerates Evaluation Speeds

Round 1

Reviewer 1 Report

In general, I believe that the authors have developed a good work with an adequate level of originality. Unfortunately, to properly assess a PUF, measurements on  fabricated chips would be necessary. Nevertheless, the Monte Carlo simulations presented in the paper help to evaluate the proposal's robustness. I suggest specifying in Table 2 that the data provided for competitor solutions are measurement results, while for the authors' proposal, they are post-layout simulation results. Additionally, some important recent references are missing, such as:

 

J. Liu, et al, "A Weak PUF-Assisted Strong PUF With Inherent Immunity to Modeling Attacks and Ultra-Low BER," in IEEE Transactions on Circuits and Systems I: Regular Papers, 2022

M. Vatalaro, et al. "Static CMOS Physically Unclonable Function Based on 4T Voltage Divider With 0.6%–1.5% Bit Instability at 0.4–1.8 V Operation in 180 nm," in IEEE Journal of Solid-State Circuits, 2022

D. Jeon, et al."A 325F2 Physical Unclonable Function Based on Contact Failure Probability With Bit Error Rate < 0.43 ppm After Preselection With 0.0177% Discard Ratio," in IEEE Journal of Solid-State Circuits, 2023

The paper should be carefully reviewed to eliminate some typos.

Author Response

Dear Reviewer,

Thanks for your kind comments, which help us see the basic flaw of our comparison and also point the direction of the next step of our research.

1. A "Measurement" row is added to Table 2 to distinguish the different data sources. Some of the latest works are added to Table 2 for comparison as well. However, there are only a few previous works attaining the same level of results by simulation. For this work, there is a lot of work spent on the methods of simulating, extracting data and analysing extracted data. Moreover, a paragraph of discussion is added for Table 2. 

2. The suggested recent references are added. Based on the latest references, a new section, "State-Of-The-Art and Related PUF Works", is added.

Reviewer 2 Report

In this work it has been presented an innovative 8-Transistor (8T) Physically Unclonable Function (PUF) design combined with a power gating technique to achieve a significant speed boost compared to a 6-Transistor (6T) Static Random-Access Memory (SRAM) PUF. The 8T PUF is designed to rapidly eliminate data remnants and enhance physical mismatch. The implementation includes a two-phase power gating module to control power cycles for specific PUF rows, enabling quick statistical measurements and minimizing in-rush current. The hardware architecture supports fast evaluations of PUF Responses, enabling a novel data processing method involving dark-bit masking and Multiple Temporal Majority Voting (TMV) in different environmental conditions. This approach drastically reduces the Bit Error Rate (BER) to nearly 0% and lessens the hardware impact of error correction. The performance and statistical metrics of the 8T PUF are evaluated through post-layout simulations and processing of PUF Responses, which represents a novel aspect of the approach. The paper holds promise, but there are several concerns that need to be addressed before it can be considered suitable for publication:

 

1. In the introduction, several works are absent, and authors need to provide a well-defined overview of the PUF landscape in the context of Asic (Application-Specific Integrated Circuit) technology. Moreover, there is a requirement to delve deeper into the state of the art concerning metastable-based PUFs. Significant contributions pertaining to both PUFs on ASICs and metastable-based PUFs need to be incorporated into a dedicated State-Of-The-Art section. This is essential to offer readers a clear and comprehensive understanding of the existing literature. The following references should be discussed and presented within this State-Of-The-Art section:"

ASIC

1. Gassend, B.; Clarke, D.; van Dijk, M.; Devadas, S. Silicon physical random functions. In CCS ’02: Proceedings of the 9^th ACM Conference on Computer and Communications Security; Association for Computing Machinery: New York, NY, USA, 2002; pp. 148–160.

2. Lee, J.W.; Lim, D.; Gassend, B.; Suh, G.E.; van Dijk, M.; Devadas, S. A technique to build a secret key in integrated circuits for identification and authentication applications. In Proceedings of the 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525), Honolulu, HI, USA, 17–19 June 2004; pp. 176–179.

3. Sahoo, D.P.; Mukhopadhyay, D.; Chakraborty, R.S.; Nguyen, P.H. A Multiplexer-Based Arbiter PUF Composition with EnhancedReliability and Security. IEEE Trans. Comput. 2017, 67, 403–417.

4. Della Sala, R., Bellizia, D., Centurelli, F., & Scotti, G. (2023). A Monostable Physically Unclonable Function Based on Improved RCCMs with 0–1.56% Native Bit Instability at 0.6–1.2 V and 0–75 °C. Electronics, 12(3), 755.

5. Zhou, C.; Parhi, K.K.; Kim, C.H. Secure and Reliable XOR Arbiter PUF Design: An Experimental Study based on 1 Trillion Challenge Response Pair Measurements. In DAC ’17: Proceedings of the 54th Annual Design Automation Conference 2017; Association for Computing Machinery: New York, NY, USA, 2017; pp. 1–6.

6. Majzoobi, M.; Koushanfar, F.; Devadas, S. FPGA PUF using programmable delay lines. InProceedings of the 2010 IEEE International Workshop on Information Forensics and Security, Seattle, WA, USA, 12–15 December 2010; pp. 12–15.

7. Mathew, S.K.; Satpathy, S.K.; Anders, M.A.; Kaul, H.; Hsu, S.K.; Agarwal, A.; Chen, G.K.; Parker, R.J.; Krishnamurthy, R.K.; De, V. 16.2 A 0.19pJ/b PVT-variation-tolerant hybrid physically unclonable function circuit for 100% stable secure key generation in 22nm CMOS. In Proceedings of the 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), San Francisco, CA, USA, 9–13 February 2014; pp. 278–279.

8. Zhao, X.; Gan, P.; Zhao, Q.; Liang, D.; Cao, Y.; Pan, X.; Bermak, A. A 124 fJ/Bit Cascode Current Mirror Array Based PUF with 1.50% Native Unstable Bit Ratio. IEEE Trans. Circ. Syst. I 2019, 66, 3494–3503.

9. Yang, K.; Dong, Q.; Blaauw, D.; Sylvester, D. 8.3 A 553F2 2-transistor amplifier-based Physically Unclonable Function (PUF) with 1.67% native instability. In Proceedings of the 2017 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 5–9 February 2017; pp. 146–147.

10. Satpathy, S.; Mathew, S.K.; Suresh, V.; Anders, M.A.; Kaul, H.; Agarwal, A.; Hsu, S.K.; Chen, G.; Krishnamurthy, R.K.; De, V.K. A 4-fJ/b Delay-Hardened Physically Unclonable Function Circuit with Selective Bit Destabilization in 14-nm Trigate CMOS. IEEE J. Solid-State Circuits 2017, 52, 940–949.

11. Taneja, S.; Alvarez, A.B.; Alioto, M. Fully Synthesizable PUF Featuring Hysteresis and Temperature Compensation for 3.2% Native BER and 1.02 fJ/b in 40 nm. IEEE J. Solid-State Circuits 2018, 53, 2828–2839.

12. Alvarez, A.B.; Zhao, W.; Alioto, M. Static Physically Unclonable Functions for Secure Chip Identification with 1.9–5.8% Native Bit Instability at 0.6–1 V and 15 fJ/bit in 65 nm. IEEE J. Solid-State Circuits 2016, 51, 763–775.

METASTABLE with a similar startup behavior

13. Yamamoto, D.; Sakiyama, K.; Iwamoto, M.; Ohta, K.; Takenaka, M.; Itoh, K. Variety enhancement of PUF responses using the locations of random outputting RS latches. J. Cryptogr. Eng. 2013, 3, 197–211.

14. Della Sala, R.; Bellizia, D.; Scotti, G. A Lightweight FPGA Compatible Weak-PUF Primitive Based on XOR Gates. IEEE Trans. Circuits Syst. II 2022, 69, 2972–2976.

15. Serrano, R.; Duran, C.; Sarmiento, M.; Dang, T.K.; Hoang, T.T.; Pham, C.K. A Unified PUF and Crypto Core Exploiting the Metastability in Latches. Future Internet 2022, 14, 298.

16. Della Sala, R.; Bellizia, D.; Scotti, G. A Novel Ultra-Compact FPGA PUF: The DD-PUF. Cryptography 2021, 5, 23.

17. Bossuet, L.; Ngo, X.T.; Cherif, Z.; Fischer, V. A PUF Based on a Transient Effect Ring Oscillator and Insensitive to Locking Phenomenon. IEEE Trans. Emerging Top. Comput. 2013, 2, 30–36.

18. Habib, B.; Kaps, J.P.; Gaj, K. Efficient SR-Latch PUF. In Applied Reconfigurable Computing; Springer: Cham, Switzerland, 2015; pp. 205–216.

19. Yamamoto, D.; Sakiyama, K.; Iwamoto, M.; Ohta, K.; Ochiai, T.; Takenaka, M.; Itoh, K. Uniqueness Enhancement of PUF Responses Based on the Locations of Random Outputting RS Latches. In Cryptographic Hardware and Embedded Systems -CHES 2011; Springer: Berlin, Germany, 2011; pp. 390–406.

20. Della Sala, R., & Scotti, G. (2023). A Novel FPGA Implementation of the NAND-PUF with Minimal Resource Usage and High Reliability. Cryptography, 7(2).

 

2. From row 62 to row 63 you should add following relevant works about PUF+TRNG architectures (Indeed PUF + TRNG works are missing):

   1. Y. Wang, H. Liang, Y. Wang, L. Yao, M. Yi, Z. Huang, et al., "A reconfigurable PUF structure with dual working modes based on entropy separation model", Microelectron. J., vol. 124, Jun. 2022.

   2. Della Sala, R. , Scotti, G. (2023). Exploiting the DD-Cell as an Ultra-Compact Entropy Source for an FPGA-Based Re-Configurable PUF-TRNG Architecture. IEEE Access, 11, 86178–86195.

   3. A. Maiti, R. Nagesh, A. Reddy and P. Schaumont, "Physical unclonable function and true random number generator: A compact and scalable implementation", Proc. 19th ACM Great Lakes Symp. VLSI, pp. 425-428, May 2009.

   4. I. Baturone, R. Román and Á. Corbacho, "A unified multibit PUF and TRNG based on ring oscillators for secure IoT devices", IEEE Internet Things J., vol. 10, no. 7, pp. 6182-6192, Apr. 2023.

   5. R. Della Sala and G. Scotti, "The DD-cell: A double side entropic source exploitable as PUF and TRNG", Proc. 17th Conf. Ph.D Res. Microelectron. Electron. (PRIME), pp. 353-356, Jun. 2022.

3. It would be more effective to reformat the text as an itemized list spanning from row 67 to 71.

4. Figure 3 should be the first Figure presented, maybe authors should consider to used Figure 1a and 1b.

5. The reason why this specific post-processing method has not been previously introduced becomes evident from row 204 to 211. This approach necessitates precise Process, Voltage, and Temperature (PVT) characterization, which is challenging to ensure in practical application scenarios. PUF-generated keys are commonly employed for functions like key generation, token IDs, or ID cards. Therefore, since these straightforward devices lack voltage or temperature sensors, the suggested post-processing technique would not be viable in such cases. Authors should consider to explicitly present this issue and should consider to insert references of application scenarios in which this type of post-processing is available.

6. Row 211 has an extra “4”?

7. Figure 5 has a typo “metasstability”→ metastability

8. In Table II Authors have to insert other works, it is not good to present works of just Solid-State-Circuit society. Other works should be considered such as for example:

   1. R. De Rose, F. Crupi, M. Lanuzza, and D. Albano, “A physical unclonable function based on a 2-transistor subthreshold voltage divider,” Int. J. Circuit Theory Appl., vol. 45, no. 2, pp. 260–273, Feb. 2017.

   2. Della Sala, R., Bellizia, D., Centurelli, F., & Scotti, G. (2023). A Monostable Physically Unclonable Function Based on Improved RCCMs with 0–1.56% Native Bit Instability at 0.6–1.2 V and 0–75 °C. Electronics, 12(3), 755.

9. What is the average bias over different golden keys without consider post-processing or dark bits?

10. In Section 3 it is not clear which simulations authors used. Please clarify that point.

11. For the NIST tests, authors should consider to incorporate all the PUF responses taken from different process variations (e.g. the one used for the Uniqueness test) and re-extract the key for a longer and more comprehensive PUF response. As it is, it is difficult to say that this PUF has good statistical performance.

Comments for author File: Comments.pdf

2.  
3. Row 211 has an extra “4”?

4. Figure 5 has a typo “metasstability”→ metastability

Author Response

Dear Reviewer,

Thanks for your very careful review and detailed comments. We really appreciate the time and effort you spent to help with this work. We also respect the deep understanding you have of the related area. These suggestions not only help us see the points we haven't done well enough but also expand our research horizons. It lets us consider adding different types of bistable PUFs to our test chip design for further investigation and comparison.

1. A new section, "State-Of-The-Art and Related PUF Works", is added based on the suggested references.
2. The suggested references for PUF+TRNG are added. They are very helpful for our next step of research.
3. The three stages of two-phase power gating are listed as suggested.
4. Figure 3 and the related description is moved as Figure 1.
5. We did not present clearly enough for the Multiple TMV method, so we rewrote the second paragraph of Section 2.3.
6. Sorry for the mistake. It should be Section 4. 
7. Sorry for the mistake. It has been corrected.

8. A "Measurement" row is added to Table 2 to distinguish the different data sources. The suggested works are added to Table 2 for comparison. Moreover, a paragraph of discussion is added for Table 2.  However, there are only a few previous works attaining the same level of results by simulation. The post-layout simulation is extremely time and resource-consuming. For this work, there is a lot of work spent on the methods of simulating, extracting data and analysing extracted data. 

9. The raw results of stable zeroes are 46.22%, stable ones are 46.06% and 7.71% unstable bits
10. For various evaluation purposes, different simulation methods were executed with corresponding test circuits.
    
    • Section 3.1: DC sweep and post-layout transient simulations were performed.
    • Section 3.2: The post-layout Monte-Carlo simulations with the Gaussian distribution of transistor threshold voltages were carried out under the nominal condition.
    • Section 3.3: Long-duration transient simulations were conducted with intensified noise.
    • Section 4: To assess the PUF performance, 5G transient noise is added to the post-layout Monte Carlo simulations under nominal condition and different PVT corners.  
11. Sorry, we should have done further investigation with PUF randomness. The data value is not large enough to have more meaningful results. 

Reviewer 3 Report

This work shows significant improvements over the 6-Transistor cell version with single-phase ignition control. It is noteworthy that the authors have carried out different test benches to obtain the feasibility of the circuit. Beside this, I have some questions and concerns about this work.

 

1.    When using the single-phase power gating cell only one control signa is required, in the other hand two-phase power gating cell requires two control signals. 

 

·      How are these signals generated?   

·      Are they triggered in sequence?

·      How complex is the circuit to generate these signals?

·      How does clock jitter degrade the performance of the two-phase cell?

·      Signal SUPn2 looks like is connected to a larger parasitic capacitor compared to signal SUPn1. Did you design a driver for SUPn2 signal? Did you include these drivers in your circuit area?

·      Did you estimate the increment of dynamic power due to two-phase cell?

2. In the conclusions, add a discussion about the data in Table 2. What are the most notable improvements of this work compared to other works shown in Table 2?

 

Author Response

Dear Reviewer,

Thanks for your kind comments, which help us see the points we haven't done well enough and also point the direction of the next step of our research.

1. For question 1, the details of the Control block functionality were not described clearly enough.
   • The power-gating control signals are generated in the control block. The sequence of the control signals during a reading process is introduced. We also marked the signal-generating sequence of two-phase power gating in Figure 3. 
   • Sorry, the Control block and the Data Processing block have not been implemented and evaluated yet. Their effect on the PUF performance and the area cost must be considered for our tape-out design.
   • From the signal generation side, we have not added extra capacitors. However, we have designed a buffered power gating cell to improve the driven ability of SUPn signals (not included in the paper). The small dimension of the test PUF array works fine without additional drivers, but any larger dimension PUF arrays need to consider adding drivers to the SUPn signals and its area cost.  
   • The simulated dynamic power of the proposed two-phase power gating cell is added to the paper. It is about 812.5 aJ per cell.
2. A discussion is added for Table 2. It is unfair to claim any improvement compared to the state-of-the-art designs measured on CMOS chip while we evaluated our design by simulation. However, there are only a few previous works attaining the same level of results by simulation. 

Round 2

Reviewer 2 Report

Authors have fully addressed concerns. I encourage authors to consider to extract more bits in future works in order to test the randomness performance also with NIST tests. I also understand that simulations are longer than conventional cadence simulations, but maybe a solution could be to run for days some automatic script on a server, collecting day by day results.