Analysis and Hardening of SEGR in Trench VDMOS with Termination Structure
, Jingyu Tao 1, Zijun Cheng 1 and Shengdong Hu 1,*Round 1
Reviewer 1 Report
This manuscript investigates the single-event gate-rupture (SEGR) and its hardened termination technology in trench vertical double-diffused power MOSFET (VDMOS). However, some issues should be considered as follows:
1. Page1 (Section 1): Please define the “SEB” as “single event burnout” for the first time.
2. Page5 (Section 3): The simulation results come from the trench VDMOS devices irradiated heavy ions with linear energy transfer (LET) of 75 MeV×mg-1×cm-2. How about the LET of 80 MeV×mg-1×cm-2 and VDS of 48V? Is the maximum electric field in the cell larger than critical electric breakdown field? Is it possible to generate hot spot in cell?
3. Page7 (Section 4): The applications of deep space exploration are faced with radiation impact from energetic particles and ultralow temperature induced freeze out effect. Does the SEGR hardened termination with multiple implantation work at cryogenic temperatures? What are the concentrations of the bottom N-well region, p-type sidewall region and p-type extension layer? In addition, there is lack of the discussion about the effect of hardened termination structure on cell region.
4. Page7 (Section 4): How to quantify the resistivity of the holes conductive path? Please compare this resistivity before and after the hardening design.
5. Page8 (Section 4): What is the magnitude of LET in Fig. 12? Is 75 MeV×mg-1×cm-2?
6. Please polish the English and check the usage of blank spaces.
For example:
Page1 (Section 1): The statement of “...reviewed that the mechanism...” could be “...reviewed the mechanism...”; The statement of “...investigated that the impact...” could be “...investigated the impact...” ...
Page2 (Section 1): The “... ions /cm2...” could be “... ions/cm2...”; The “... 48 V...” could be “...48V...” ...
Author Response
Dear Editor and Reviewers:
Thank you for your letter and for the reviewers’ comments concerning our manuscript entitled “Analysis and Hardening of SEGR in Trench VDMOS with Termination Structure” (micromachines-2278236).
Those comments are all valuable and helpful for revising and improving our paper, as well as the important guiding significance to our researches. We have studied comments carefully and have made correction which we hope meet with approval. Revised portion are highlighted in red in the paper. The corrections in the paper and the responds to the reviewer’s comments are as following:
Comments from the editors and reviewers:
Reviewer #1: This manuscript investigates the single-event gate-rupture (SEGR) and its hardened termination technology in trench vertical double-diffused power MOSFET (VDMOS). However, some issues should be considered as follows:
- Page1 (Section 1): Please define the “SEB” as “single event burnout” for the first time.
- Page5 (Section 3): The simulation results come from the trench VDMOS devices irradiated heavy ions with linear energy transfer (LET) of 75 MeV·mg-1·cm-2. How about the LET of 80 MeV·mg-1•cm-2 and VDS of 48V? Is the maximum electric field in the cell larger than critical electric breakdown field? Is it possible to generate hot spot in cell?
- Page7 (Section 4): The applications of deep space exploration are faced with radiation impact from energetic particles and ultralow temperature induced freeze out effect. Does the SEGR hardened termination with multiple implantation work at cryogenic temperatures? What are the concentrations of the bottom N-well region, p-type sidewall region and p-type extension layer? In addition, there is lack of the discussion about the effect of hardened termination structure on cell region.
- Page7 (Section 4): How to quantify the resistivity of the holes conductive path? Please compare this resistivity before and after the hardening design.
- Please polish the English and check the usage of blank spaces.
For example:
Page1 (Section 1): The statement of “...reviewed that the mechanism...” could be “...reviewed the mechanism...”; The statement of “...investigated that the impact...” could be “...investigated the impact...” ...
Page2 (Section 1): The “... ions /cm2...” could be “... ions/cm2...”; The “... 48 V...” could be “...48V...” ...
For question1: Thank you very much for your valuable comments. We have defined the “SEB” as “single event burnout” for the first time.
For question2: We are sorry that this mistake occurred owing to our negligence. The heavy ions with an LET of 80 MeV•mg-1•cm-2 were also used in simulations, and we have removed this mistake in revised manuscript, accordingly.
As shown in Fig. 8, the maximum electric field of gate oxide in the cell was less than the critical electric breakdown field. Thus, the gate oxide in the cell would not suffer damage, and it is not possible to generate hot spot in cell.
For question3: Many thanks for your constructive comments. Firstly, the termination structure only affects the breakdown voltage of the trench VDMOS, therefore when the operating voltage is less than the breakdown voltage, the SEGR hardened trench VDMOS can work at cryogenic temperatures, which is not affected by the SEGR hardened termination.
Secondly, the doping concentration of BNW, SW and EL is 5e16cm-3, 1e18cm-3 and 1e19cm-3, respectively. And we have added this content in the revised manuscript.
Thirdly, according to your comment, more discussions about the effect of hardened termination structure on cell region have been added in the revised manuscript with a clearer way. Its description as following:
The termination structure could affect the breakdown voltage of the trench VDMOS, therefore, the breakdown characteristics for the conventional termination and the SEGR hardened termination are investigated, as is shown in Fig.14. With the introduction of multiple implantation regions for hardening, the BV is slightly decreased from 74V to 63V. However, compared to the low triggering voltage and failure consequences of SEGR, these small impacts of hardening method is still acceptable.
Fig. 14. Simulated breakdown characteristic curves for the conventional termination and the SEGR hardened termination.
For question4: Thank you for your good comments. The resistivity for N-type silicon and P-type silicon can be related to the doping concentration:
where ND is the donor concentration per cubic centimeter and NA is the acceptor concentration per cubic centimeter. The resistivity for N-type silicon and P-type silicon versus the doping concentration are shown in the following figure. It can be seen that the resistivity for N-type silicon and P-type silicon decreases with an increasing of the doping concentration.
Fig. The resistivity for N-type silicon and P-type silicon versus the doping concentration.
For question5: We are sorry and we have removed this mistake in revised manuscript, accordingly.
Author Response File: 
Author Response.docx
Reviewer 2 Report
The manuscript demonstrates a single event test on VDMOS and propose a SEGR hardening method by adding multiple implantation regions. My comments for possible improvement are as flows：
l Fig. 3 shows the single event test data with two Vds values. One value ( 48 V) can cause SEB or SEGR and the other cannot ( 24 V). What is the critical (minimum) voltage that can cause SEB or SEGR event?
l Besides microscopic snapshot, authors should also show and compare some simulated curves with Fig. 3 to demonstrate the improvement of SEGR hardening. e.g., the critical voltage improvement or other reasonable standard.
Author Response
Dear Editor and Reviewers,
On behalf of my co-authors, we thank you very much for giving us an opportunity to revise our manuscript, we appreciate editor and reviewers very much for their positive and constructive comments and suggestions on our manuscript entitled “Analysis and Hardening of SEGR in Trench VDMOS with Termination Structure” (micromachines-2278236).
We have studied reviewer’s comments carefully and have made revision. We have tried our best to revise our manuscript according to the comments. Attached please find the revised version, which we would like to submit for your kind consideration. List of responses to the reviewers’ comments is below.
We would like to express our great appreciation to you and reviewers for comments on our paper. Looking forward to hearing from you.
Thank you and best regards.
Yours sincerely,
Corresponding author: Shengdong Hu
E-mail: hushengdong@hotmail.com
Dear Editor and Reviewers:
Thank you for your letter and for the reviewers’ comments concerning our manuscript entitled “Analysis and Hardening of SEGR in Trench VDMOS with Termination Structure” (micromachines-2278236).
Those comments are all valuable and helpful for revising and improving our paper, as well as the important guiding significance to our researches. We have studied comments carefully and have made correction which we hope meet with approval. Revised portion are highlighted in red in the paper. The corrections in the paper and the responds to the reviewer’s comments are as following:
Comments from the editors and reviewers:
Reviewer #2: The manuscript demonstrates a single event test on VDMOS and propose a SEGR hardening method by adding multiple implantation regions. My comments for possible improvement are as flows：
1. Fig. 3 shows the single event test data with two Vds values. One value (48V) can cause SEB or SEGR and the other cannot (24V). What is the critical (minimum) voltage that can cause SEB or SEGR event?
2. Besides microscopic snapshot, authors should also show and compare some simulated curves with Fig. 3 to demonstrate the improvement of SEGR hardening. e.g., the critical voltage improvement or other reasonable standard.
For question1：Special thanks to you for your good comments. Because of fewer opportunities and times for the single-event test, the single-event test was only carried out under VDS of 24V and 48V. If the chance comes, the critical voltage that can cause SEB or SEGR event would be confirmed by experiment method. However, for this problem, the critical voltage that can cause SEGR event for the conventional termination has been confirmed by simulation method, and which is 28V.
For question2: Many thanks for your positive feedback. Thank you very much for your constructive comments. Thank you very much for your valuable comments. The demonstration for the improvement of SEGR hardening is very essential. More detail description as following:
To further demonstrate the improvement of SEGR hardening, the SEGR triggering criteria for the conventional termination and the SEGR hardened termination are investigated in detail. As shown in fig.13, it is clear seen that when VGS is set as 0V, the conventional termination does not trigger SEGR when VDS is 27V and below, and when VDS is 28V, SEGR occurs. Thus, the SEGR triggering voltage (VSEGR) of the conventional termination is 28V. The SEGR hardened termination does not trigger SEGR when VDS is 60V and below, which can be considered to be a safe operating area (SOA), we believe that the device will not exhibit SEGR at VGS=0V for 60-V trench VDMOS. Compared with the conventional termination, the SEGR triggering critical voltage for the SEGR hardened termination is improved by 114%.
Fig. 13. Comparison of IDS when VDS is 27V and 28V of the conventional termination and when VDS is 60V of the SEGR hardened termination.
Author Response File: Author Response.docx
