Research

13 pages, 6780 KiB

Open AccessArticle

A SiC Planar MOSFET with an Embedded MOS-Channel Diode to Improve Reverse Conduction and Switching

by Ping Li, Jingwei Guo, Shengdong Hu and Zhi Lin

Micromachines 2023, 14(7), 1282; https://doi.org/10.3390/mi14071282 - 22 Jun 2023

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A novel split-gate SiC MOSFET with an embedded MOS-channel diode for enhanced third-quadrant and switching performances is proposed and studied using TCAD simulations in this paper. During the freewheeling period, the MOS-channel diode with a low potential barrier constrains the reverse current flow [...] Read more.

A novel split-gate SiC MOSFET with an embedded MOS-channel diode for enhanced third-quadrant and switching performances is proposed and studied using TCAD simulations in this paper. During the freewheeling period, the MOS-channel diode with a low potential barrier constrains the reverse current flow through it. Therefore, the suggested device not only has a low diode cut-in voltage but also entirely suppresses the intrinsic body diode, which will cause bipolar deterioration. In order to clarify the barrier-lowering effect of the MOS-channel diode, an analytical model is proposed. The calibrated simulation results demonstrate that the diode cut-in voltage of the proposed device is decreased from the conventional voltage of 2.7 V to 1.2 V. In addition, due to the split-gate structure, the gate-to-drain charge (Q_GD) of the proposed device is 20 nC/cm², and the reverse-transfer capacitance (C_GD) is 14 pF/cm², which are lower than the Q_GD of 230 nC/cm² and the C_GD of 105 pF/cm² for the conventional one. Therefore, a better high-frequency figure-of-merit and lower switching loss are obtained. Full article

(This article belongs to the Special Issue Power Semiconductor Devices and Applications)

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20 pages, 2933 KiB

Open AccessArticle

A Comparative Analysis of Doherty and Outphasing MMIC GaN Power Amplifiers for 5G Applications

by Victoria Díez-Acereda, Sunil Lalchand Khemchandani, Javier del Pino and Ayoze Diaz-Carballo

Micromachines 2023, 14(6), 1205; https://doi.org/10.3390/mi14061205 - 07 Jun 2023

Cited by 1 | Viewed by 1318

Abstract

A comparison between a fully integrated Doherty power amplifier (DPA) and outphasing power amplifier (OPA) for fifth Generation (5G) wireless communications is presented in this paper. Both amplifiers are integrated using pHEMT transistors from the OMMIC’s 100 nm GaN-on-Si technology (D01GH). After a [...] Read more.

A comparison between a fully integrated Doherty power amplifier (DPA) and outphasing power amplifier (OPA) for fifth Generation (5G) wireless communications is presented in this paper. Both amplifiers are integrated using pHEMT transistors from the OMMIC’s 100 nm GaN-on-Si technology (D01GH). After a theoretical analysis, the design and layout of both circuits are presented. The DPA uses an asymmetric configuration where the main amplifier is biased in class AB and the auxiliary amplifier is biased in class C, while the OPA uses two amplifiers biased in class B. In the comparative analysis, it has been observed that the OPA presents a better performance in terms of maximum power added efficiency (PAE), while the DPA provides higher linearity and efficiency at 7.5 dB output back-off (OBO). At a 1 dB compression point, the OPA exhibits an output power of 33 dBm with a maximum PAE of 58.3% compared to 44.2% for the DPA for an output power of 35 dBm, and at 7.5 dB OBO, the DPA achieves a PAE of 38.5%, while the OPA achieves 26.1%. The area has been optimized using absorbing adjacent component techniques, resulting in an area of 3.26 mm² for the DPA and 3.18 mm² for the OPA. Full article

(This article belongs to the Special Issue Power Semiconductor Devices and Applications)

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22 pages, 20434 KiB

Open AccessArticle

Simulation Studies on Single-Event Effects and the Mechanisms of SiC VDMOS from a Structural Perspective

by Tao Liu, Yuan Wang, Rongyao Ma, Hao Wu, Jingyu Tao, Yiren Yu, Zijun Cheng and Shengdong Hu

Micromachines 2023, 14(5), 1074; https://doi.org/10.3390/mi14051074 - 18 May 2023

Cited by 1 | Viewed by 1204

Abstract

The single-event effect reliability issue is one of the most critical concerns in the context of space applications for SiC VDMOS. In this paper, the SEE characteristics and mechanisms of the proposed deep trench gate superjunction (DTSJ), conventional trench gate superjunction (CTSJ), conventional [...] Read more.

The single-event effect reliability issue is one of the most critical concerns in the context of space applications for SiC VDMOS. In this paper, the SEE characteristics and mechanisms of the proposed deep trench gate superjunction (DTSJ), conventional trench gate superjunction (CTSJ), conventional trench gate (CT), and conventional planar gate (CT) SiC VDMOS are comprehensively analyzed and simulated. Extensive simulations demonstrate the maximum SET current peaks of DTSJ−, CTSJ−, CT−, and CP SiC VDMOS, which are 188 mA, 218 mA, 242 mA, and 255 mA, with a bias voltage V_DS of 300 V and LET = 120 MeV·cm²/mg, respectively. The total charges of DTSJ−, CTSJ−, CT−, and CP SiC VDMOS collected at the drain are 320 pC, 1100 pC, 885 pC, and 567 pC, respectively. A definition and calculation of the charge enhancement factor (CEF) are proposed. The CEF values of DTSJ−, CTSJ−, CT−, and CP SiC VDMOS are 43, 160, 117, and 55, respectively. Compared with CTSJ−, CT−, and CP SiC VDMOS, the total charge and CEF of the DTSJ SiC VDMOS are reduced by 70.9%, 62.4%, 43.6% and 73.1%, 63.2%, and 21.8%, respectively. The maximum SET lattice temperature of the DTSJ SiC VDMOS is less than 2823 K under the wide operating conditions of a drain bias voltage V_DS ranging from 100 V to 1100 V and a LET value ranging from 1 MeV·cm²/mg to 120 MeV·cm²/mg, while the maximum SET lattice temperatures of the other three SiC VDMOS significantly exceed 3100 K. The SEGR LET thresholds of DTSJ−, CTSJ−, CT−, and CP SiC VDMOS are approximately 100 MeV·cm²/mg, 15 MeV·cm²/mg, 15 MeV·cm²/mg, and 60 MeV·cm²/mg, respectively, while the value of V_DS = 1100 V. Full article

(This article belongs to the Special Issue Power Semiconductor Devices and Applications)

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13 pages, 5105 KiB

Open AccessCommunication

A Low-Loss 1.2 kV SiC MOSFET with Improved UIS Performance

by Lijuan Wu, Mengyuan Zhang, Jiahui Liang, Mengjiao Liu, Tengfei Zhang and Gang Yang

Micromachines 2023, 14(5), 1061; https://doi.org/10.3390/mi14051061 - 17 May 2023

Viewed by 1108

Abstract

In this article, a 1.2-kV-rated double-trench 4H-SiC MOSFET with an integrated low-barrier diode (DT-LBDMOS) is proposed which eliminates the bipolar degradation of the body diode and reduces switching loss while increasing avalanche stability. A numerical simulation verifies that a lower barrier for electrons [...] Read more.

In this article, a 1.2-kV-rated double-trench 4H-SiC MOSFET with an integrated low-barrier diode (DT-LBDMOS) is proposed which eliminates the bipolar degradation of the body diode and reduces switching loss while increasing avalanche stability. A numerical simulation verifies that a lower barrier for electrons appears because of the LBD; thus, a path that makes it easier for electrons to transfer from the N+ source to the drift region is provided, finally eliminating the bipolar degradation of the body diode. At the same time, the LBD integrated in the P-well region weakens the scattering effect of interface states on electrons. Compared with the gate p-shield trench 4H-SiC MOSFET (GPMOS), the reverse on-voltage (V_F) is reduced from 2.46 V to 1.54 V; the reverse recovery charge (Q_rr) and the gate-to-drain capacitance (C_gd) are 28% and 76% lower than those of the GPMOS, respectively. The turn-on and turn-off losses of the DT-LBDMOS are reduced by 52% and 35%. The specific on-resistance (R_ON,sp) of the DT-LBDMOS is reduced by 34% due to the weaker scattering effect of interface states on electrons. The HF-FOM (HF-FOM = R_ON,sp × C_gd) and the P-FOM (P-FOM = BV²/R_ON,sp) of the DT-LBDMOS are both improved. Using the unclamped inductive switching (UIS) test, we evaluate the avalanche energy of devices and the avalanche stability. The improved performances suggest that DT-LBDMOS can be harnessed in practical applications. Full article

(This article belongs to the Special Issue Power Semiconductor Devices and Applications)

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9 pages, 3622 KiB

Open AccessArticle

4H-SiC LDMOS Integrating a Trench MOS Channel Diode for Improved Reverse Recovery Performance

by Yanjuan Liu, Dezhen Jia and Junpeng Fang

Micromachines 2023, 14(5), 950; https://doi.org/10.3390/mi14050950 - 27 Apr 2023

Viewed by 1179

Abstract

In this paper, a 4H-SiC lateral gate MOSFET incorporating a trench MOS channel diode at the source side is explored to improve the reverse recovery characteristics. In addition, a 2D numerical simulator (ATLAS) is used to investigate the electrical characteristics of the devices. [...] Read more.

In this paper, a 4H-SiC lateral gate MOSFET incorporating a trench MOS channel diode at the source side is explored to improve the reverse recovery characteristics. In addition, a 2D numerical simulator (ATLAS) is used to investigate the electrical characteristics of the devices. The investigational results have demonstrated that the peak reverse recovery current is reduced by 63.5%, the reverse recovery charge is reduced by 24.5%, and the reverse recovery energy loss is decreased by 25.8%, with extra complexity in the fabrication process. Full article

(This article belongs to the Special Issue Power Semiconductor Devices and Applications)

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14 pages, 3224 KiB

Open AccessArticle

Numerical Investigation of Transient Breakdown Voltage Enhancement in SOI LDMOS by Using a Step P-Type Doping Buried Layer

by Xiaoming Yang, Taiqiang Cao, Xiaohua Zhang, Tianqian Li and Hang Luo

Micromachines 2023, 14(4), 887; https://doi.org/10.3390/mi14040887 - 20 Apr 2023

Viewed by 1311

Abstract

In this paper, the transient breakdown voltage (TrBV) of a silicon-on-insulator (SOI) laterally diffused metal-oxide-semiconductor (LDMOS) device was increased by introducing a step P-type doping buried layer (SPBL) below the buried oxide (BOX). Device simulation software MEDICI 0.13.2 was used to [...] Read more.

In this paper, the transient breakdown voltage (TrBV) of a silicon-on-insulator (SOI) laterally diffused metal-oxide-semiconductor (LDMOS) device was increased by introducing a step P-type doping buried layer (SPBL) below the buried oxide (BOX). Device simulation software MEDICI 0.13.2 was used to investigate the electrical characteristics of the new devices. When the device was turned off, the SPBL could enhance the reduced surface field (RESURF) effect and modulate the lateral electric field in the drift region to ensure that the surface electric field was evenly distributed, thus increasing the lateral breakdown voltage (BV_lat). The enhancement of the RESURF effect while maintaining a high doping concentration in the drift region (N_d) in the SPBL SOI LDMOS resulted in a reduction in the substrate doping concentration (P_sub) and an expansion of the substrate depletion layer. Therefore, the SPBL both improved the vertical breakdown voltage (BV_ver) and suppressed an increase in the specific on-resistance (R_on,sp). The results of simulations showed a 14.46% higher TrBV and a 46.25% lower R_on,sp for the SPBL SOI LDMOS compared to those of the SOI LDMOS. As the SPBL optimized the vertical electric field at the drain, the turn-off non-breakdown time (T_nonbv) of the SPBL SOI LDMOS was 65.64% longer than that of the SOI LDMOS. The SPBL SOI LDMOS also demonstrated that TrBV was 10% higher, R_on,sp was 37.74% lower, and T_nonbv was 10% longer than those of the double RESURF SOI LDMOS. Full article

(This article belongs to the Special Issue Power Semiconductor Devices and Applications)

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10 pages, 5036 KiB

Open AccessArticle

Low Switching Loss Built-In Diode of High-Voltage RC-IGBT with Shortened P+ Emitter

by Wei Wu, Yansong Li, Mingkang Yu, Chongbing Gao, Yulu Shu and Yong Chen

Micromachines 2023, 14(4), 873; https://doi.org/10.3390/mi14040873 - 19 Apr 2023

Cited by 1 | Viewed by 1505

Abstract

In this paper, a low switching loss built-in diode of a high-voltage reverse-conducting insulated gate bipolar transistor (RC-IGBT) is proposed without deteriorating IGBT characteristics. It features a particular shortened P+ emitter (SE) in the diode part of RC-IGBT. Firstly, the shortened P+ emitter [...] Read more.

In this paper, a low switching loss built-in diode of a high-voltage reverse-conducting insulated gate bipolar transistor (RC-IGBT) is proposed without deteriorating IGBT characteristics. It features a particular shortened P+ emitter (SE) in the diode part of RC-IGBT. Firstly, the shortened P+ emitter in the diode part can suppress the hole injection efficiency resulting in the reduced carriers extracted during the reverse recovery process. The peak of the reverse recovery current and switching loss of the built-in diode during reverse recovery is therefore lowered. Simulation results indicate that the diode’s reverse recovery loss of the proposed RC-IGBT is lowered by 20% compared with that of the conventional RC-IGBT. Secondly, the separate design of the P+ emitter prevents the performance of IGBT from deteriorating. Finally, the wafer process of the proposed RC-IGBT is almost the same as that of conventional RC-IGBT, which makes it a promising candidate for manufacturing. Full article

(This article belongs to the Special Issue Power Semiconductor Devices and Applications)

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11 pages, 3755 KiB

Open AccessCommunication

Automatic Piecewise Extreme Learning Machine-Based Model for S-Parameters of RF Power Amplifier

by Lulu Wang, Shaohua Zhou, Wenrao Fang, Wenhua Huang, Zhiqiang Yang, Chao Fu and Changkun Liu

Micromachines 2023, 14(4), 840; https://doi.org/10.3390/mi14040840 - 13 Apr 2023

Cited by 2 | Viewed by 1122

Abstract

This paper presents an automatic piecewise (Auto-PW) extreme learning machine (ELM) method for S-parameters modeling radio-frequency (RF) power amplifiers (PAs). A strategy based on splitting regions at the changing points of concave-convex characteristics is proposed, where each region adopts a piecewise ELM [...] Read more.

This paper presents an automatic piecewise (Auto-PW) extreme learning machine (ELM) method for S-parameters modeling radio-frequency (RF) power amplifiers (PAs). A strategy based on splitting regions at the changing points of concave-convex characteristics is proposed, where each region adopts a piecewise ELM model. The verification is carried out with S-parameters measured on a 2.2–6.5 GHz complementary metal oxide semiconductor (CMOS) PA. Compared to the long-short term memory (LSTM), support vector regression (SVR), and conventional ELM modeling methods, the proposed method performs excellently. For example, the modeling speed is two orders of magnitude faster than SVR and LSTM, and the modeling accuracy is more than one order of magnitude higher than ELM. Full article

(This article belongs to the Special Issue Power Semiconductor Devices and Applications)

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16 pages, 5255 KiB

Open AccessArticle

Remaining Useful Lifetime Prediction Based on Extended Kalman Particle Filter for Power SiC MOSFETs

by Wei Wu, Yongqian Gu, Mingkang Yu, Chongbing Gao and Yong Chen

Micromachines 2023, 14(4), 836; https://doi.org/10.3390/mi14040836 - 12 Apr 2023

Viewed by 1436

Abstract

Nowadays, the performance of silicon-based devices is almost approaching the physical limit of their materials, which have difficulty meeting the needs of modern high-power applications. The SiC MOSFET, as one of the important third-generation wide bandgap power semiconductor devices, has received extensive attention. [...] Read more.

Nowadays, the performance of silicon-based devices is almost approaching the physical limit of their materials, which have difficulty meeting the needs of modern high-power applications. The SiC MOSFET, as one of the important third-generation wide bandgap power semiconductor devices, has received extensive attention. However, numerous specific reliability issues exist for SiC MOSFETs, such as bias temperature instability, threshold voltage drift, and reduced short-circuit robustness. The remaining useful life (RUL) prediction of SiC MOSFETs has become the focus of device reliability research. In this paper, a RUL estimation method using the Extended Kalman Particle Filter (EPF) based on an on-state voltage degradation model for SiC MOSFETs is proposed. A new power cycling test platform is designed to monitor the on-state voltage of SiC MOSFETs used as the failure precursor. The experimental results show that the RUL prediction error decreases from 20.5% of the traditional Particle Filter algorithm (PF) algorithm to 11.5% of EPF with 40% data input. The life prediction accuracy is therefore improved by about 10%. Full article

(This article belongs to the Special Issue Power Semiconductor Devices and Applications)

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10 pages, 7054 KiB

Open AccessArticle

Analysis and Hardening of SEGR in Trench VDMOS with Termination Structure

by Yuan Wang, Tao Liu, Lingli Qian, Hao Wu, Yiren Yu, Jingyu Tao, Zijun Cheng and Shengdong Hu

Micromachines 2023, 14(3), 688; https://doi.org/10.3390/mi14030688 - 20 Mar 2023

Cited by 1 | Viewed by 1278

Abstract

Single-event gate-rupture (SEGR) in the trench vertical double-diffused power MOSFET (VDMOS) occurs at a critical bias voltage during heavy-ion experiments. Fault analysis demonstrates that the hot spot is located at the termination of the VDMOS, and the gate oxide in the termination region [...] Read more.

Single-event gate-rupture (SEGR) in the trench vertical double-diffused power MOSFET (VDMOS) occurs at a critical bias voltage during heavy-ion experiments. Fault analysis demonstrates that the hot spot is located at the termination of the VDMOS, and the gate oxide in the termination region has been damaged. The SEGR-hardened termination with multiple implantation regions is proposed and simulated using the Sentaurus TCAD. The multiple implantation regions are introduced, leading to an increase in the distance between the gate oxide and the hole accumulation region, as well as a decrease in the resistivity of the hole conductive path. This approach is effective in reducing the electric field of the gate oxide to below the calculated critical field, and results in a lower electric field than the conventional termination. Full article

(This article belongs to the Special Issue Power Semiconductor Devices and Applications)

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13 pages, 5527 KiB

Open AccessArticle

A Novel Concept of Electron–Hole Enhancement for Superjunction Reverse-Conducting Insulated Gate Bipolar Transistor with Electron-Blocking Layer

by Zhigang Wang, Chong Yang and Xiaobing Huang

Micromachines 2023, 14(3), 646; https://doi.org/10.3390/mi14030646 - 12 Mar 2023

Cited by 1 | Viewed by 1612

Abstract

A novel snapback-free superjunction reverse-conducting insulated gate bipolar transistor (SJ-RC-IGBT) is proposed and verified by simulation. In the SJ-RC-IGBT, the parasitic P/N/P/N structure as thyristor or Shockley diode demonstrates large conductivity due to an overabundance of carriers for reverse conduction. By preventing electrons [...] Read more.

A novel snapback-free superjunction reverse-conducting insulated gate bipolar transistor (SJ-RC-IGBT) is proposed and verified by simulation. In the SJ-RC-IGBT, the parasitic P/N/P/N structure as thyristor or Shockley diode demonstrates large conductivity due to an overabundance of carriers for reverse conduction. By preventing electrons from leaking across the N+ region at the collector side, the extra electron-blocking (EB) layer introduced in the SJ-RC-IGBT can dramatically enhance electron–hole pairs in the N/P-pillars. Hence, the SJ-RC-IGBT demonstrates a low on-state voltage (V_on). In addition, snapback-free characteristics and a large safe operating area (SOA) are also achieved in the SJ-RC-IGBT. During the turn-off process, a significant amount of electrons are extracted by parasitic MOS across the EB layer at the collector side to decrease the turn-off loss (E_off). According to the optimized results, the SJ-RC-IGBT with EB layer obtains an ultralow E_off of 3.9 mJ/cm² at V_on = 1.38 V with 88% and 81% decreases, respectively, compared with the conventional reverse-conducting IGBT (CRC-IGBT) and superjunction IGBT (SJ-IGBT). Full article

(This article belongs to the Special Issue Power Semiconductor Devices and Applications)

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10 pages, 3570 KiB

Open AccessArticle

Machine Learning Algorithm for Efficient Design of Separated Buffer Super-Junction IGBT

by Ki Yeong Kim, Tae Hyun Hwang, Young Suh Song, Hyunwoo Kim and Jang Hyun Kim

Micromachines 2023, 14(2), 334; https://doi.org/10.3390/mi14020334 - 28 Jan 2023

Cited by 1 | Viewed by 1439

Abstract

An improved structure for an Insulated Gate Bipolar Transistor (IGBT) with a separated buffer layer is presented in order to improve the trade-off between the turn-off loss (E_off) and on-state voltage (V_on). However, it is difficult to [...] Read more.

An improved structure for an Insulated Gate Bipolar Transistor (IGBT) with a separated buffer layer is presented in order to improve the trade-off between the turn-off loss (E_off) and on-state voltage (V_on). However, it is difficult to set efficient parameters due to the increase in the new buffer doping concentration variable. Therefore, a machine learning (ML) algorithm is proposed as a solution. Compared to the conventional Technology Computer-Aided Design (TCAD) simulation tool, it is demonstrated that incorporating the ML algorithm into the device analysis could make it possible to achieve high accuracy and significantly shorten the simulation time. Specifically, utilizing the ML algorithm could achieve coefficients of determination (R²) of V_on and E_off of 0.995 and 0.968, respectively. In addition, it enables the optimized design to fit the target characteristics. In this study, the structure proposed for the trade-off improvement was targeted to obtain the minimum E_off at the same V_on, especially by adjusting the concentration of the separated buffer. We could improve E_off by 36.2% by optimizing the structure, which was expected to be improved by 24.7% using the ML approach. In another way, it is possible to inversely design four types of structures with characteristics close to the target characteristics (E_off = 1.64 μJ, V_on = 1.38 V). The proposed method of incorporating machine learning into device analysis is expected to be very strategic, especially for power electronics analysis (where the transistor size is comparatively large and requires significant computation). In summary, we improved the trade-off using a separated buffer, and ML enabled optimization and a more precise design, as well as reverse engineering. Full article

(This article belongs to the Special Issue Power Semiconductor Devices and Applications)

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