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Advanced CMOS Integrated Circuit Design and Application

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A special issue of Sensors (ISSN 1424-8220). This special issue belongs to the section "Electronic Sensors".

Deadline for manuscript submissions: closed (31 January 2022) | Viewed by 33140

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Prof. Dr. Jong-Ryul Yang

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Guest Editor

Department of Electrical and Electronics Engineering, Konkuk University, 120, Neungdong-ro, Gwangjin-gu, Seoul 05029, Republic of Korea
Interests: RF/millimeter-wave transceiver front-end IC design for radar systems; terahertz-wave integrated circuits and systems; MMIC design; miniaturized radar sensors; CW/FSK/FMCW radar sensors; remote vital sign detection; HRV analysis using radar sensors
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Dr. Seong-Tae Han

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Guest Editor

Korea Electrotechnology Research Institute, Changwon 51543, Republic of Korea
Interests: microwave systems; millimeter-wave/THz systems; detectors
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

Dear Colleagues,

The recent development of various application systems and platforms, such as 5G, B5G, 6G, and IoT, is based on the advancement of CMOS integrated circuit technology that enables them to implement high-performance chipsets. In addition to development in the traditional fields of analog and digital integrated circuits, the development of CMOS IC design and application in high-power and high-frequency applications, which had been thought to be possible only with compound semiconductor technology, is a core technology that drives rapid industrial development.

This Special Issue aims to highlight advances in all aspects of CMOS integrated circuit design and applications regardless of operating frequencies, output powers, and analog/digital domain. Up-to-date reviews and original works are both accepted in this issue. Topics include but are not limited to:

Next-generation CMOS circuit design and application;
CMOS RF/microwave/millimeter-wave/terahertz-wave integrated circuits and systems;
All kinds of circuits, systems, and applications based on CMOS technology: Analog IC, digital IC, power management IC, driver IC, readout IC, high-powered IC;
CMOS integrated circuits specially used for wireless or wired systems and applications such as converters, controllers, sensors, interfaces, frequency synthesizers/generators, rectennas, rectifiers, and so on;
CMOS design methodology using any up-to-date EDA tools;
Design process to achieve the high-performance CMOS circuits and systems;
Algorithms and signal processing methods to improve the performances of CMOS circuits and systems.

Prof. Dr. Jong-Ryul Yang
Prof. Dr. Seong-Tae Han
Guest Editors

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Keywords

CMOS
integrated circuits and systems
high-powered IC
high-frequency IC
millimeter-wave integrated circuits
terahertz-wave integrated circuits
analog circuits
digital circuits
VLSI
solid-state integrated circuits
power management integrated circuits
drivers
converters
controllers
sensor IC
interface IC
readout circuits and systems
rectennas
rectifiers
frequency synthesizers/generators
CMOS design process and methodology

Published Papers (10 papers)

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Research

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13 pages, 52021 KiB

Open AccessArticle

Concurrent-Mode CMOS Detector IC for Sub-Terahertz Imaging System

by Moon-Jeong Lee, Ha-Neul Lee, Ga-Eun Lee, Seong-Tae Han and Jong-Ryul Yang

Sensors 2022, 22(5), 1753; https://doi.org/10.3390/s22051753 - 23 Feb 2022

Cited by 1 | Viewed by 2040

Abstract

A CMOS detector with a concurrent mode for high-quality images in the sub-terahertz region has been proposed. The detector improves output-signal coupling characteristics at the output node. A cross-coupling capacitor is added to isolate the DC bias between the drain and gate. The detector is designed to combine a 180° phase shift based on common source operation and an in-phase output signal based on the drain input. The circuit layout and phase shift occurring in the cross-coupled capacitor during phase coupling are verified using an EM simulation. The detector is fabricated using the TSMC 0.25-μm mixed-signal 1-poly 5-metal layer CMOS process, where the size, including the pad, is 1.13 mm × 0.74 mm. The detector IC comprises a folded dipole antenna, the proposed detector, a preamplifier, and a voltage buffer. Measurement results using a 200-GHz gyrotron source demonstrate that the proposed detector voltage responsivity is 14.13 MV/W with a noise-equivalent power of 34.42 pW/√Hz. The high detection performance helps resolve the 2-mm line width. The proposed detector exhibits a signal-to-noise ratio of 49 dB with regard to the THz imaging performance, which is 9 dB higher than that of the previous CMOS detector core circuits with gate-drain capacitors. Full article

(This article belongs to the Special Issue Advanced CMOS Integrated Circuit Design and Application)

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37 pages, 10228 KiB

Open AccessArticle

Excel Methods to Design and Validate in Microelectronics (Complementary Metal–Oxide–Semiconductor, CMOS) for Biomedical Instrumentation Application

by Graciano Dieck-Assad, José Manuel Rodríguez-Delgado and Omar Israel González Peña

Sensors 2021, 21(22), 7486; https://doi.org/10.3390/s21227486 - 11 Nov 2021

Cited by 1 | Viewed by 3109

Abstract

CMOS microelectronics design has evolved tremendously during the last two decades. The evolution of CMOS devices to short channel designs where the feature size is below 1000 nm brings a great deal of uncertainty in the way the microelectronics design cycle is completed. After the conceptual idea, developing a thinking model to understand the operation of the device requires a good “ballpark” evaluation of transistor sizes, decision making, and assumptions to fulfill the specifications. This design process has iterations to meet specifications that exceed in number of the available degrees of freedom to maneuver the design. Once the thinking model is developed, the simulation validation follows to test if the design has a good possibility of delivering a successful prototype. If the simulation provides a good match between specifications and results, then the layout is developed. This paper shows a useful open science strategy, using the Excel software, to develop CMOS microelectronics hand calculations to verify a design, before performing the computer simulation and layout of CMOS analog integrated circuits. The full methodology is described to develop designs of passive components, as well as CMOS amplifiers. The methods are used in teaching CMOS microelectronics to students of electronic engineering with industrial partner participation. This paper describes an exhaustive example of a low-voltage operational transconductance amplifier (OTA) design which is used to design an instrumentation amplifier. Finally, a test is performed using this instrumentation amplifier to implement a front-end signal conditioning device for CMOS-MEMS biomedical applications. Full article

(This article belongs to the Special Issue Advanced CMOS Integrated Circuit Design and Application)

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17 pages, 1231 KiB

Open AccessArticle

CMOS Implementation of ANNs Based on Analog Optimization of N-Dimensional Objective Functions

by Alejandro Medina-Santiago, Carlos Arturo Hernández-Gracidas, Luis Alberto Morales-Rosales, Ignacio Algredo-Badillo, Monica Amador García and Jorge Antonio Orozco Torres

Sensors 2021, 21(21), 7071; https://doi.org/10.3390/s21217071 - 25 Oct 2021

Cited by 3 | Viewed by 1737

Abstract

The design of neural network architectures is carried out using methods that optimize a particular objective function, in which a point that minimizes the function is sought. In reported works, they only focused on software simulations or commercial complementary metal-oxide-semiconductor (CMOS), neither of which guarantees the quality of the solution. In this work, we designed a hardware architecture using individual neurons as building blocks based on the optimization of n-dimensional objective functions, such as obtaining the bias and synaptic weight parameters of an artificial neural network (ANN) model using the gradient descent method. The ANN-based architecture has a 5-3-1 configuration and is implemented on a 1.2

μ

m technology integrated circuit, with a total power consumption of 46.08 mW, using nine neurons and 36 CMOS operational amplifiers (op-amps). We show the results obtained from the application of integrated circuits for ANNs simulated in PSpice applied to the classification of digital data, demonstrating that the optimization method successfully obtains the synaptic weights and bias values generated by the learning algorithm (Steepest-Descent), for the design of the neural architecture. Full article

(This article belongs to the Special Issue Advanced CMOS Integrated Circuit Design and Application)

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13 pages, 3020 KiB

Open AccessArticle

A Dynamic Threshold Cancellation Technique for a High-Power Conversion Efficiency CMOS Rectifier

by António Godinho, Zhaochu Yang, Tao Dong, Luís Gonçalves, Paulo Mendes, Yumei Wen, Ping Li and Zhuangde Jiang

Sensors 2021, 21(20), 6883; https://doi.org/10.3390/s21206883 - 17 Oct 2021

Cited by 1 | Viewed by 2430

Abstract

Power conversion efficiency (PCE) has been one of the key concerns for power management circuits (PMC) due to the low output power of the vibrational energy harvesters. This work reports a dynamic threshold cancellation technique for a high-power conversion efficiency CMOS rectifier. The proposed rectifier consists of two stages, one passive stage with a negative voltage converter, and another stage with an active diode controlled by a threshold cancellation circuit. The former stage conducts the signal full-wave rectification with a voltage drop of 1 mV, whereas the latter reduces the reverse leakage current, consequently enhancing the output power delivered to the ohmic load. As a result, the rectifier can achieve a voltage and power conversion efficiency of over 99% and 90%, respectively, for an input voltage of 0.45 V and for low ohmic loads. The proposed circuit is designed in a standard 130 nm CMOS process and works for an operating frequency range from 800 Hz to 51.2 kHz, which is promising for practical applications. Full article

(This article belongs to the Special Issue Advanced CMOS Integrated Circuit Design and Application)

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13 pages, 5915 KiB

Open AccessCommunication

A New Current-Shaping Technique Based on a Feedback Injection Mechanism to Reduce VCO Phase Noise

by Francisco Javier del Pino Suárez and Sunil Lalchand Khemchandani

Sensors 2021, 21(19), 6583; https://doi.org/10.3390/s21196583 - 01 Oct 2021

Cited by 3 | Viewed by 1873

Abstract

Inductor-capacitor voltage controlled oscillators (LC-VCOs) are the most common type of oscillator used in sensors systems, such as transceivers for wireless sensor networks (WSNs), VCO-based reading circuits, VCO-based radar sensors, etc. This work presents a technique to reduce the LC-VCOs phase noise using a new current-shaping method based on a feedback injection mechanism with only two additional transistors. This technique consists of keeping the negative resistance seen from LC tank constant throughout the oscillation cycle, achieving a significant phase noise reduction with a very low area increase. To test this method an LC-VCO was designed, fabricated and measured on a wafer using 90 nm CMOS technology with 1.2 V supply voltage. The oscillator outputs were buffered using source followers to provide additional isolation from load variations and to boost the output power. The tank was tuned to 1.8 GHz, comprising two 1.15 nH with 1.5 turns inductors with a quality factor (Q) of 14, a 3.27 pF metal-oxide-metal capacitor, and two varactors. The measured phase noise was −112 dBc/Hz at 1 MHz offset. Including the pads, the chip area is 750 × 850

μ

^{2}

. Full article

(This article belongs to the Special Issue Advanced CMOS Integrated Circuit Design and Application)

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17 pages, 4156 KiB

Open AccessArticle

A CMOS RF Receiver with Improved Resilience to OFDM-Induced Second-Order Intermodulation Distortion for MedRadio Biomedical Devices and Sensors

by Yongho Lee, Shinil Chang, Jungah Kim and Hyunchol Shin

Sensors 2021, 21(16), 5303; https://doi.org/10.3390/s21165303 - 05 Aug 2021

Cited by 3 | Viewed by 2476

Abstract

A MedRadio RF receiver integrated circuit for implanted and wearable biomedical devices must be resilient to the out-of-band (OOB) orthogonal frequency division modulation (OFDM) blocker. As the OFDM is widely adopted for various broadcasting and communication systems in the ultra-high frequency (UHF) band, the selectivity performance of the MedRadio RF receiver can severely deteriorate by the second-order intermodulation (IM2) distortion induced by the OOB OFDM blocker. An analytical investigation shows how the OFDM-induced IM2 distortion power can be translated to an equivalent two-tone-induced IM2 distortion power. It makes the OFDM-induced IM2 analysis and characterization process for a MedRadio RF receiver much simpler and more straightforward. A MedRadio RF receiver integrated circuit with a significantly improved resilience to the OOB IM2 distortion is designed in 65 nm complementary metal-oxide-semiconductor (CMOS). The designed RF receiver is based on low-IF architecture, comprising a low-noise amplifier, single-to-differential transconductance stage, quadrature passive mixer, trans-impedance amplifier (TIA), image-rejecting complex bandpass filter, and fractional phase-locked loop synthesizer. We describe design techniques for the IM2 calibration through the gate bias tuning at the mixer, and the dc offset calibration that overcomes the conflict with the preceding IM2 calibration through the body bias tuning at the TIA. Measured results show that the OOB carrier-to-interference ratio (CIR) performance is significantly improved by 4–11 dB through the proposed IM2 calibration. The measured maximum tolerable CIR is found to be between −40.2 and −71.2 dBc for the two-tone blocker condition and between −70 and −77 dBc for the single-tone blocker condition. The analytical and experimental results of this work will be essential to improve the selectivity performance of a MedRadio RF receiver against the OOB OFDM-blocker-induced IM2 distortion and, thus, improve the robustness of the biomedical devices in harsh wireless environments in the MedRadio and UHF bands. Full article

(This article belongs to the Special Issue Advanced CMOS Integrated Circuit Design and Application)

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17 pages, 4791 KiB

Open AccessArticle

An 18.8–33.9 GHz, 2.26 mW Current-Reuse Injection-Locked Frequency Divider for Radar Sensor Applications

by Kwang-Il Oh, Goo-Han Ko, Jeong-Geun Kim and Donghyun Baek

Sensors 2021, 21(7), 2551; https://doi.org/10.3390/s21072551 - 06 Apr 2021

Cited by 4 | Viewed by 2373

Abstract

An 18.8–33.9 GHz, 2.26 mW current-reuse (CR) injection-locked frequency divider (ILFD) for radar sensor applications is presented in this paper. A fourth-order resonator is designed using a transformer with a distributed inductor for wideband operating of the ILFD. The CR core is employed to reduce the power consumption compared to conventional cross-coupled pair ILFDs. The targeted input center frequency is 24 GHz for radar application. The self-oscillated frequency of the proposed CR-ILFD is 14.08 GHz. The input frequency locking range is from 18.8 to 33.8 GHz (57%) at an injection power of 0 dBm without a capacitor bank or varactors. The proposed CR-ILFD consumes 2.26 mW of power from a 1 V supply voltage. The entire die size is 0.75 mm × 0.45 mm. This CR-ILFD is implemented in a 65 nm complementary metal-oxide semiconductor (CMOS) technology. Full article

(This article belongs to the Special Issue Advanced CMOS Integrated Circuit Design and Application)

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11 pages, 4759 KiB

Open AccessCommunication

Current Input Pixel-Level ADC with High SNR and Wide Dynamic Range for a Microbolometer

by Jeongho Lee, Ilku Nam and DooHyung Woo

Sensors 2021, 21(7), 2354; https://doi.org/10.3390/s21072354 - 28 Mar 2021

Viewed by 2733

Abstract

A readout circuit incorporating a pixel-level analog-to-digital converter (ADC) is studied for two-dimensional medium wavelength infrared microbolometer arrays. The signal-to-noise ratio (SNR) and charge handling capacity of the unit cell circuit are improved by using the current input pixel-level ADC. The charge handling capacity of the integrator is appropriately extended to maximize the integration time regardless of the magnitude of the input current and low power supply voltage. The readout circuit was fabricated using a 0.35-μm 2-poly 4-metal CMOS process for a 640 × 512 array with a pixel size of 40 μm × 40 μm. The peak SNR and dynamic range are 77.1 and 80.1 dB, respectively, with a power consumption of 0.62 μW per pixel. Full article

(This article belongs to the Special Issue Advanced CMOS Integrated Circuit Design and Application)

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20 pages, 5935 KiB

Open AccessFeature PaperArticle

Convolution Kernel Operations on a Two-Dimensional Spin Memristor Cross Array

by Saike Zhu, Lidan Wang, Zhekang Dong and Shukai Duan

Sensors 2020, 20(21), 6229; https://doi.org/10.3390/s20216229 - 31 Oct 2020

Viewed by 2956

Abstract

In recent years, convolution operations often consume a lot of time and energy in deep learning algorithms, and convolution is usually used to remove noise or extract the edges of an image. However, under data-intensive conditions, frequent operations of the above algorithms will cause a significant memory/communication burden to the computing system. This paper proposes a circuit based on spin memristor cross array to solve the problems mentioned above. First, a logic switch based on spin memristors is proposed, which realizes the control of the memristor cross array. Secondly, a new type of spin memristor cross array and peripheral circuits is proposed, which realizes the multiplication and addition operation in the convolution operation and significantly alleviates the computational memory bottleneck. At last, the color image filtering and edge extraction simulation are carried out. By calculating the peak signal-to-noise ratio (PSNR) and structural similarity (SSIM) of the image result, the processing effects of different operators are compared, and the correctness of the circuit is verified. Full article

(This article belongs to the Special Issue Advanced CMOS Integrated Circuit Design and Application)

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Review

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22 pages, 4562 KiB

Open AccessReview

Switched-Biasing Techniques for CMOS Voltage-Controlled Oscillator

by Cheol-Woo Kang, Hyunwon Moon and Jong-Ryul Yang

Sensors 2021, 21(1), 316; https://doi.org/10.3390/s21010316 - 05 Jan 2021

Cited by 9 | Viewed by 8006

Abstract

A voltage-controlled oscillator (VCO) is a key component to generate high-speed clock of mixed-mode circuits and local oscillation signals of the frequency conversion in wired and wireless application systems. In particular, the recent evolution of new high-speed wireless systems in the millimeter-wave frequency band calls for the implementation of the VCO with high oscillation frequency and low close-in phase noise. The effect of the flicker noise on the phase noise of the VCO should be minimized because the flicker noise dramatically increases as the deep-submicron complementary metal-oxide-semiconductor (CMOS) process is scaled down, and the flicker corner frequency also increases, up to several MHz, in the up-to-date CMOS process. The flicker noise induced by the current source is a major factor affecting the phase noise of the VCO. Switched-biasing techniques have been proposed to minimize the effect of the flicker noise at the output of the VCO with biasing AC-coupled signals at the current source of the VCO. Reviewing the advantages and disadvantages reported in the previous studies, it is analyzed which topology to implement the switched-biasing technique is advantageous for improving the performance of the CMOS VCOs. Full article

(This article belongs to the Special Issue Advanced CMOS Integrated Circuit Design and Application)

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