Research

13 pages, 3475 KiB

Open AccessArticle

Synergistic Radiation Effects in PPD CMOS Image Sensors Induced by Neutron Displacement Damage and Gamma Ionization Damage

by Zu-Jun Wang, Yuan-Yuan Xue, Ning Tang, Gang Huang, Xu Nie, Shan-Kun Lai, Bao-Ping He, Wu-Ying Ma, Jiang-Kun Sheng and Shi-Long Gou

Sensors 2024, 24(5), 1441; https://doi.org/10.3390/s24051441 - 23 Feb 2024

Viewed by 406

Abstract

The synergistic effects on the 0.18 µm PPD CISs induced by neutron displacement damage and gamma ionization damage are investigated. The typical characterizations of the CISs induced by the neutron displacement damage and gamma ionization damage are presented separately. The CISs are irradiated [...] Read more.

The synergistic effects on the 0.18 µm PPD CISs induced by neutron displacement damage and gamma ionization damage are investigated. The typical characterizations of the CISs induced by the neutron displacement damage and gamma ionization damage are presented separately. The CISs are irradiated by reactor neutron beams up to 1 × 10¹¹ n/cm² (1 MeV neutron equivalent fluence) and ⁶⁰Co γ-rays up to the total ionizing dose level of 200 krad(Si) with different sequential order. The experimental results show that the mean dark signal increase in the CISs induced by reactor neutron radiation has not been influenced by previous ⁶⁰Co γ-ray radiation. However, the mean dark signal increase in the CISs induced by ⁶⁰Co γ-ray radiation has been remarkably influenced by previous reactor neutron radiation. The synergistic effects on the PPD CISs are discussed by combining the experimental results and the TCAD simulation results of radiation damage. Full article

(This article belongs to the Special Issue Advanced CMOS Integrated Circuit Design and Application II)

► Show Figures

Figure 1

19 pages, 3026 KiB

Open AccessArticle

A Reformed PSO-Based High Linear Optimized Up-Conversion Mixer for Radar Application

by Tahesin Samira Delwar, Unal Aras, Abrar Siddique, Yangwon Lee and Jee-Youl Ryu

Sensors 2024, 24(3), 879; https://doi.org/10.3390/s24030879 - 29 Jan 2024

Viewed by 460

Abstract

A reformed particle swarm optimization (R_PSO)-based up-conversion mixer circuit is proposed for radar application in this paper. In practice, a non-optimized up-conversion mixer suffers from high power consumption, poor linearity, and conversion gain. Therefore, the R_PSO algorithm is proposed to [...] Read more.

A reformed particle swarm optimization (R_PSO)-based up-conversion mixer circuit is proposed for radar application in this paper. In practice, a non-optimized up-conversion mixer suffers from high power consumption, poor linearity, and conversion gain. Therefore, the R_PSO algorithm is proposed to optimize the up-conversion mixer. The novelty of the proposed R_PSO algorithm is it helps to solve the problem of local optima and premature convergence in traditional particle swarm optimization (T_PSO). Furthermore, in the R_PSO, a velocity position-based convergence (VP_C) and wavelet mutation (W_M) strategy are used to enhance R_PSO’s swarm diversity. Moreover, this work also features novel circuit configurations based on the two-fold transconductance path (T_TP), a technique used to improve linearity. A differential common source (D_CS) amplifier is included in the primary transconductance path (P_TP) of the T_TP. As for the subsidiary transconductance path (S_TP), the enhanced cross-quad transconductor (E_CQT) is implemented within the T_TP. A benchmark function verification is conducted to demonstrate the effectiveness of the R_PSO algorithm. The proposed R_PSO has also been compared with other optimization algorithms such as the genetic algorithm (GA) and the non-dominated sorting genetic algorithm II (NSGA-II). By using R_PSO, the proposed optimized mixer achieves a conversion gain (CG) of 2.5 dB (measured). In this study, the proposed mixer achieves a 1 dB compression point (OP₁dB) of 4.2 dBm with a high linearity. In the proposed mixer, the noise figure (NF) is approximately 3.1 dB. While the power dissipation of the optimized mixer is 3.24 mW. Additionally, the average time for R_PSO to design an up-conversion mixer is 4.535 s. Simulation and measured results demonstrate the excellent performance of the R_PSO optimized up-conversion mixer. Full article

(This article belongs to the Special Issue Advanced CMOS Integrated Circuit Design and Application II)

► Show Figures

Figure 1

17 pages, 5099 KiB

Open AccessArticle

Analog Convolutional Operator Circuit for Low-Power Mixed-Signal CNN Processing Chip

by Malik Summair Asghar, Saad Arslan and HyungWon Kim

Sensors 2023, 23(23), 9612; https://doi.org/10.3390/s23239612 - 04 Dec 2023

Cited by 1 | Viewed by 856

Abstract

In this paper, we propose a compact and low-power mixed-signal approach to implementing convolutional operators that are often responsible for most of the chip area and power consumption of Convolutional Neural Network (CNN) processing chips. The convolutional operators consist of several multiply-and-accumulate (MAC) [...] Read more.

In this paper, we propose a compact and low-power mixed-signal approach to implementing convolutional operators that are often responsible for most of the chip area and power consumption of Convolutional Neural Network (CNN) processing chips. The convolutional operators consist of several multiply-and-accumulate (MAC) units. MAC units are the primary components that process convolutional layers and fully connected layers of CNN models. Analog implementation of MAC units opens a new paradigm for realizing low-power CNN processing chips, benefiting from less power and area consumption. The proposed mixed-signal convolutional operator comprises low-power binary-weighted current steering digital-to-analog conversion (DAC) circuits and accumulation capacitors. Compared with a conventional binary-weighted DAC, the proposed circuit benefits from optimum accuracy, smaller area, and lower power consumption due to its symmetric design. The proposed convolutional operator takes as input a set of 9-bit digital input feature data and weight parameters of the convolutional filter. It then calculates the convolutional filter’s result and accumulates the resulting voltage on capacitors. In addition, the convolutional operator employs a novel charge-sharing technique to process negative MAC results. We propose an analog max-pooling circuit that instantly selects the maximum input voltage. To demonstrate the performance of the proposed mixed-signal convolutional operator, we implemented a CNN processing chip consisting of 3 analog convolutional operators, with each operator processing a 3 × 3 kernel. This chip contains 27 MAC circuits, an analog max-pooling, and an analog-to-digital conversion (ADC) circuit. The mixed-signal CNN processing chip is implemented using a CMOS 55 nm process, which occupies a silicon area of 0.0559 mm² and consumes an average power of 540.6 μW. The proposed mixed-signal CNN processing chip offers an area reduction of 84.21% and an energy reduction of 91.85% compared with a conventional digital CNN processing chip. Moreover, another CNN processing chip is implemented with more analog convolutional operators to demonstrate the operation and structure of an example convolutional layer of a CNN model. Therefore, the proposed analog convolutional operator can be adapted in various CNN models as an alternative to digital counterparts. Full article

(This article belongs to the Special Issue Advanced CMOS Integrated Circuit Design and Application II)

► Show Figures

Figure 1

12 pages, 4227 KiB

Open AccessArticle

The Design of a Low-Noise, High-Speed Readout-Integrated Circuit for Infrared Focal Plane Arrays

by Yusong Mu, Zilong Zhao, Chong Chen, Di Yuan, Jing Wang, Hansong Gao and Yaodan Chi

Sensors 2023, 23(21), 8715; https://doi.org/10.3390/s23218715 - 25 Oct 2023

Cited by 1 | Viewed by 1286

Abstract

This paper describes the design of a low-noise, high-speed readout-integrated circuit for use in InGaAs infrared focal plane arrays, and analyzes the working principle and noise index of the pixel circuit in detail. The design fully considers the dynamic range, noise, and power [...] Read more.

This paper describes the design of a low-noise, high-speed readout-integrated circuit for use in InGaAs infrared focal plane arrays, and analyzes the working principle and noise index of the pixel circuit in detail. The design fully considers the dynamic range, noise, and power consumption of the pixel circuit in which a capacitance transimpedance amplifier structure is adopted as the input stage circuit, and chip fabrication via an XFAB 0.18 µm CMOS process is successfully realized. The ROIC adopts monolithic integration and implements various functions, such as windowing, subsampling, and different integration and readout modes. The ROIC reached an array scale of 32 × 32, a frame rate of 100 Hz, and a readout rate of 20 Mbps with an analog power consumption of less than 52 mW. The measurement results show that the input reference noise can be reduced to 143 e- via the CDS, and the fully customized scheme has certain advantages in the research of high-performance ROICs. Full article

(This article belongs to the Special Issue Advanced CMOS Integrated Circuit Design and Application II)

► Show Figures

Figure 1

17 pages, 1008 KiB

Open AccessArticle

Aging Compensation in a Class-A High-Frequency Amplifier with DC Temperature Measurements

by Josep Altet, Xavier Aragones, Enrique Barajas, Xavier Gisbert, Sergio Martínez and Diego Mateo

Sensors 2023, 23(16), 7069; https://doi.org/10.3390/s23167069 - 10 Aug 2023

Cited by 1 | Viewed by 958

Abstract

One of the threats to nanometric CMOS analog circuit reliability is circuit performance degradation due to transistor aging. To extend circuit operating life, the bias of the main devices within the circuit must be adjusted while the aging degradation process affects them by [...] Read more.

One of the threats to nanometric CMOS analog circuit reliability is circuit performance degradation due to transistor aging. To extend circuit operating life, the bias of the main devices within the circuit must be adjusted while the aging degradation process affects them by using a monitor circuit that tracks the evolution of the circuit performance. In this paper, we propose the use of DC temperature measurements in the proximity of the circuit to perform the monitoring of circuit performance degradation and as an observable variable to adjust the bias of the main devices to restore the degraded performance to the original values. To this end, we present experimental results obtained from nine samples of a standard CMOS integrated circuit containing a high-frequency class-A power amplifier and a differential temperature sensor. After accelerated aging, the gain of the amplifier is degraded up to 50%. We propose two different procedures to perform DC temperature measurements that allow tracking of the amplifier gain degradation due to aging and, by uniquely observing temperature readings, automatically set a new bias for the amplifier devices that restores the original amplifier gain. Whereas one of the procedures is able to restore the gain up to a certain limit, the second allows full gain restoration. Full article

(This article belongs to the Special Issue Advanced CMOS Integrated Circuit Design and Application II)

► Show Figures

Figure 1

13 pages, 4426 KiB

Open AccessArticle

A Compact and Low-Power SoC Design for Spiking Neural Network Based on Current Multiplier Charge Injector Synapse

by Malik Summair Asghar, Saad Arslan, Ali A. Al-Hamid and HyungWon Kim

Sensors 2023, 23(14), 6275; https://doi.org/10.3390/s23146275 - 10 Jul 2023

Cited by 3 | Viewed by 1500

Abstract

This paper presents a compact analog system-on-chip (SoC) implementation of a spiking neural network (SNN) for low-power Internet of Things (IoT) applications. The low-power implementation of an SNN SoC requires the optimization of not only the SNN model but also the architecture and [...] Read more.

This paper presents a compact analog system-on-chip (SoC) implementation of a spiking neural network (SNN) for low-power Internet of Things (IoT) applications. The low-power implementation of an SNN SoC requires the optimization of not only the SNN model but also the architecture and circuit designs. In this work, the SNN has been constituted from the analog neuron and synaptic circuits, which are designed to optimize both the chip area and power consumption. The proposed synapse circuit is based on a current multiplier charge injector (CMCI) circuit, which can significantly reduce power consumption and chip area compared with the previous work while allowing for design scalability for higher resolutions. The proposed neuron circuit employs an asynchronous structure, which makes it highly sensitive to input synaptic currents and enables it to achieve higher energy efficiency. To compare the performance of the proposed SoC in its area and power consumption, we implemented a digital SoC for the same SNN model in FPGA. The proposed SNN chip, when trained using the MNIST dataset, achieves a classification accuracy of 96.56%. The presented SNN chip has been implemented using a 65 nm CMOS process for fabrication. The entire chip occupies 0.96 mm² and consumes an average power of 530 μW, which is 200 times lower than its digital counterpart. Full article

(This article belongs to the Special Issue Advanced CMOS Integrated Circuit Design and Application II)

► Show Figures

Figure 1

17 pages, 9396 KiB

Open AccessArticle

A Multimode 28 GHz CMOS Fully Differential Beamforming IC for Phased Array Transceivers

by Ayush Bhatta, Jeongsoo Park, Donghyun Baek and Jeong-Geun Kim

Sensors 2023, 23(13), 6124; https://doi.org/10.3390/s23136124 - 03 Jul 2023

Cited by 1 | Viewed by 1491

Abstract

A 28 GHz fully differential eight-channel beamforming IC (BFIC) with multimode operations is implemented in 65 nm CMOS technology for use in phased array transceivers. The BFIC has an adjustable gain and phase control on each channel to achieve fine beam steering and [...] Read more.

A 28 GHz fully differential eight-channel beamforming IC (BFIC) with multimode operations is implemented in 65 nm CMOS technology for use in phased array transceivers. The BFIC has an adjustable gain and phase control on each channel to achieve fine beam steering and beam pattern. The BFIC has eight differential beamforming channels each consisting of the two-stage bi-directional amplifier with a precise gain control circuit, a six-bit phase shifter, a three-bit digital step attenuator, and a tuning bit for amplitude and phase variation compensation. The Tx and Rx mode overall gains of the differential eight-channel BFIC are around 11 dB and 9 dB, respectively, at 27.0–29.5 GHz. The return losses of the Tx mode and Rx mode are >10 dB at 27.0–29.5 GHz. The maximum phase of 354° with a phase resolution of 5.6° and the maximum attenuation of 31 dB, including the gain control bits with an attenuation resolution of 1 dB, is achieved at 27.0–29.5 GHz. The root mean square (RMS) phase and amplitude errors are <3.2° and <0.6 dB at 27.0–29.5 GHz, respectively. The chip size is 3.0 × 3.5 mm², including pads, and Tx mode current consumption is 580 mA at 2.5 V supply voltage. Full article

(This article belongs to the Special Issue Advanced CMOS Integrated Circuit Design and Application II)

► Show Figures

Figure 1

13 pages, 1300 KiB

Open AccessCommunication

Self Capacitance Mismatch Calibration Technique for Fully-Differential Touch Screen Panel Self Capacitance Sensing System

by Siheon Seong, Sewon Lee, Sunghyun Bae and Minjae Lee

Sensors 2023, 23(7), 3779; https://doi.org/10.3390/s23073779 - 06 Apr 2023

Viewed by 1570

Abstract

This paper presents a fully-differential touch screen panel (TSP) self-capacitance sensing (SCS) system with a self-capacitance mismatch calibration technique. Due to the self-capacitance mismatch of TSP, the analog front-end (AFE) of the receiver (RX) circuit suffers from dynamic range degradation and gain limitations, [...] Read more.

This paper presents a fully-differential touch screen panel (TSP) self-capacitance sensing (SCS) system with a self-capacitance mismatch calibration technique. Due to the self-capacitance mismatch of TSP, the analog front-end (AFE) of the receiver (RX) circuit suffers from dynamic range degradation and gain limitations, which lead to the signal-to-noise ratio (SNR) loss for the TSP SCS system. The proposed calibration introduces the difference in input resistance and the driving amplifier’s strength between the fully-differential input. Thus, the mismatch effect is efficiently relieved in terms of area and power consumption. The proposed calibration restores the SNR by

19.54

dB even under the worst self-capacitance mismatch case. Full article

(This article belongs to the Special Issue Advanced CMOS Integrated Circuit Design and Application II)

► Show Figures

Figure 1

23 pages, 10805 KiB

Open AccessArticle

3.6 mW Active-Electrode ECG/ETI Sensor System Using Wideband Low-Noise Instrumentation Amplifier and High Impedance Balanced Current Driver

by Xuan Tien Nguyen, Muhammad Ali and Jong-Wook Lee

Sensors 2023, 23(5), 2536; https://doi.org/10.3390/s23052536 - 24 Feb 2023

Viewed by 1622

Abstract

An active electrode (AE) and back-end (BE) integrated system for enhanced electrocardiogram (ECG)/electrode-tissue impedance (ETI) measurement is proposed. The AE consists of a balanced current driver and a preamplifier. To increase the output impedance, the current driver uses a matched current source and [...] Read more.

An active electrode (AE) and back-end (BE) integrated system for enhanced electrocardiogram (ECG)/electrode-tissue impedance (ETI) measurement is proposed. The AE consists of a balanced current driver and a preamplifier. To increase the output impedance, the current driver uses a matched current source and sink, which operates under negative feedback. To increase the linear input range, a new source degeneration method is proposed. The preamplifier is realized using a capacitively-coupled instrumentation amplifier (CCIA) with a ripple-reduction loop (RRL). Compared to the traditional Miller compensation, active frequency feedback compensation (AFFC) achieves bandwidth extension using the reduced size of the compensation capacitor. The BE performs three types of signal sensing: ECG, band power (BP), and impedance (IMP) data. The BP channel is used to detect the Q-, R-, and S-wave (QRS) complex in the ECG signal. The IMP channel measures the resistance and reactance of the electrode-tissue. The integrated circuits for the ECG/ETI system are realized in the 180 nm CMOS process and occupy a 1.26 mm² area. The measured results show that the current driver supplies a relatively high current (>600 μA_pp) and achieves a high output impedance (1 MΩ at 500 kHz). The ETI system can detect resistance and capacitance in the ranges of 10 mΩ–3 kΩ and 100 nF–100 μF, respectively. The ECG/ETI system consumes 3.6 mW using a single 1.8 V supply. Full article

(This article belongs to the Special Issue Advanced CMOS Integrated Circuit Design and Application II)

► Show Figures

Figure 1

15 pages, 13171 KiB

Open AccessArticle

A Direct Feedback FVF LDO for High Precision FMCW Radar Sensors in 65-nm CMOS Technology

by Jun-Hee Lee, Mun-Kyo Lee and Jung-Dong Park

Sensors 2022, 22(24), 9672; https://doi.org/10.3390/s22249672 - 10 Dec 2022

Cited by 1 | Viewed by 1992

Abstract

A direct feedback flipped voltage follower (FVF) LDO for a high-precision frequency-modulated continuous-wave (FMCW) radar is presented. To minimize the effect of the power supply ripple on the FMCW radar sensor’s resolution, a folded cascode error amplifier (EA) was connected to the outer [...] Read more.

A direct feedback flipped voltage follower (FVF) LDO for a high-precision frequency-modulated continuous-wave (FMCW) radar is presented. To minimize the effect of the power supply ripple on the FMCW radar sensor’s resolution, a folded cascode error amplifier (EA) was connected to the outer loop of the FVF to increase the open-loop gain. The direct feedback structure enhances the PSRR while minimizing the power supply ripple path and not compromising a transient response. The flipped voltage follower with a super source follower forms a fast feedback loop. The stability and parameter variation sensitivity of the multi-loop FVF LDO were analyzed through the state matrix decomposition. We implemented the FVF LDO in TSMC 65 nm CMOS technology. The fabricated FVF LDO supplied a maximum load current of 20 mA with a 1.2 V power supply. The proposed FVF LDO achieved a full-spectrum PSR with a low-frequency PSRR of 66 dB, unity-gain bandwidth of 469 MHz, and 20 ns transient settling time with a load current step from 1 mA to 20 mA. Full article

(This article belongs to the Special Issue Advanced CMOS Integrated Circuit Design and Application II)

► Show Figures

Figure 1

17 pages, 7922 KiB

Open AccessArticle

A Fast-Transient-Response NMOS LDO with Wide Load-Capacitance Range for Cross-Point Memory

by Luchang He, Xi Li, Siqiu Xu, Guochang Pan, Chenchen Xie, Houpeng Chen and Zhitang Song

Sensors 2022, 22(23), 9367; https://doi.org/10.3390/s22239367 - 01 Dec 2022

Viewed by 2948

Abstract

In this paper, a fast-transient-response NMOS low-dropout regulator (LDO) with a wide load-capacitance range was presented to provide a V/2 read bias for cross-point memory. To utilize the large dropout voltage in the V/2 bias scheme, a fast loop consisting of NMOS and [...] Read more.

In this paper, a fast-transient-response NMOS low-dropout regulator (LDO) with a wide load-capacitance range was presented to provide a V/2 read bias for cross-point memory. To utilize the large dropout voltage in the V/2 bias scheme, a fast loop consisting of NMOS and flipped voltage amplifier (FVA) topology was adopted with a fast transient response. This design is suitable to provide a V/2 read bias with 3.3 V input voltage and 1.65 V output voltage for different cross-point memories. The FVA-based LDO designed in the 110 nm CMOS process remained stable under a wide range of load capacitances from 0 to 10 nF and equivalent series resistance (ESR) conditions. At the capacitor-less condition, it exhibited a unity-gain bandwidth (UGB) of approximately 400 MHz at full load. For load current changes from 0 to 10 mA within an edge time of 10 ps, the simulated undershoot and settling time were only 144 mV and 50 ns, respectively. The regulator consumed 70 µA quiescent current and achieved a remarkable figure-of-merit (FOM) of 1.01 mV. At the ESR condition of a 1 µF off-chip capacitor, the simulated quiescent current, on-chip capacitor consumption, and current efficiency at full load were 8.5 µA, 2 pF, and 99.992%, respectively. The undershoot voltage was 20 mV with 800 ns settling time for a load step from 0 to 100 mA within the 10 ps edge time. Full article

(This article belongs to the Special Issue Advanced CMOS Integrated Circuit Design and Application II)

► Show Figures

Figure 1

14 pages, 5047 KiB

Open AccessArticle

A 24 GHz CMOS Direct-Conversion RF Receiver with I/Q Mismatch Calibration for Radar Sensor Applications

by Yongho Lee, Soyeon Kim and Hyunchol Shin

Sensors 2022, 22(21), 8246; https://doi.org/10.3390/s22218246 - 27 Oct 2022

Cited by 4 | Viewed by 1962

Abstract

A 24 GHz millimeter-wave direct-conversion radio-frequency (RF) receiver with wide-range and precise I/Q mismatch calibration is designed in 65 nm CMOS technology for radar sensor applications. The CMOS RF receiver is based on a quadrature direct-conversion architecture. Analytic relations are derived to clearly [...] Read more.

A 24 GHz millimeter-wave direct-conversion radio-frequency (RF) receiver with wide-range and precise I/Q mismatch calibration is designed in 65 nm CMOS technology for radar sensor applications. The CMOS RF receiver is based on a quadrature direct-conversion architecture. Analytic relations are derived to clearly exhibit the individual contributions of the I/Q amplitude and phase mismatches to the image-rejection ratio (IRR) degradation, which provides a useful design guide for determining the range and resolution of the I/Q mismatch calibration circuit. The designed CMOS RF receiver comprises a low-noise amplifier, quadrature down-conversion mixer, baseband amplifier, and quadrature LO generator. Controlling the individual gate bias voltages of the switching FETs in the down-conversion mixer having a resistive load is found to induce significant changes at the amplitude and phase of the output signal. In the calibration process, the mixer gate bias tuning is first performed for the amplitude mismatch calibration, and the remaining phase mismatch is then calibrated out by the varactor capacitance tuning at the LO buffer’s LC load. Implemented in 65 nm CMOS process, the RF receiver achieves 31.5 dB power gain, −35.2 dBm input-referred 1 dB compression power, and 4.8–7.1 dB noise figure across 22.5–26.1 GHz band, while dissipating 106.2 mA from a 1.2 V supply. The effectiveness of the proposed I/Q mismatch calibration is successfully verified by observing that the amplitude and phase mismatches are improved from 1.0–1.5 dB to 0.02–0.19 dB, and from 10.8–23.8 to 1.1–3.2 degrees, respectively. Full article

(This article belongs to the Special Issue Advanced CMOS Integrated Circuit Design and Application II)

► Show Figures

Figure 1

16 pages, 2263 KiB

Open AccessArticle

Noninvasive Non-Contact SpO₂ Monitoring Using an Integrated Polarization-Sensing CMOS Imaging Sensor

by Mukul Sarkar and Maher Assaad

Sensors 2022, 22(20), 7796; https://doi.org/10.3390/s22207796 - 14 Oct 2022

Cited by 1 | Viewed by 2392

Abstract

Background:In the diagnosis and primary health care of an individual, estimation of the pulse rate and blood oxygen saturation (SpO

_{2}

) is critical. The pulse rate and SpO

_{2}

are determined by methods including photoplethysmography (iPPG), light spectroscopy, and pulse oximetry. These [...] Read more.

Background:In the diagnosis and primary health care of an individual, estimation of the pulse rate and blood oxygen saturation (SpO

_{2}

) is critical. The pulse rate and SpO

_{2}

are determined by methods including photoplethysmography (iPPG), light spectroscopy, and pulse oximetry. These devices need to be compact, non-contact, and noninvasive for real-time health monitoring. Reflection-based iPPG is becoming popular as it allows non-contact estimation of the heart rate and SpO

_{2}

. Most iPPG methods capture temporal data and form complex computations, and thus real-time measurements and spatial visualization are difficult. Method:In this research work, reflective mode polarized imaging-based iPPG is proposed. For polarization imaging, a custom image sensor with wire grid polarizers on each pixel is designed. Each pixel has a wire grid of varying transmission axes, allowing phase detection of the incoming light. The phase information of the backscattered light from the fingertips of 12 healthy volunteers was recorded in both the resting as well as the excited states. These data were then processed using MATLAB 2021b software. Results: The phase information provides quantitative information on the reflection from the superficial and deep layers of skin. The ratio of deep to superficial layer backscattered phase information is shown to be directly correlated and linearly increasing with an increase in the SpO

_{2}

and heart rate. Conclusions: The phase-based measurements help to monitor the changes in the resting and excited state heart rate and SpO

_{2}

in real time. Furthermore, the use of the ratio of phase information helps to make the measurements independent of the individual skin traits and thus increases the accuracy of the measurements. The proposed iPPG works in ambient light, relaxing the instrumentation requirement and helping the system to be compact and portable. Full article

(This article belongs to the Special Issue Advanced CMOS Integrated Circuit Design and Application II)

► Show Figures

Figure 1

Journal Menu

Journal Browser

Advanced CMOS Integrated Circuit Design and Application II

Share This Special Issue

Special Issue Editors

Special Issue Information

Keywords

Published Papers (13 papers)

Research

Further Information

Guidelines

MDPI Initiatives

Follow MDPI