Nanomaterials

Research

Jump to: Review

16 pages, 4951 KiB

Open AccessArticle

Effects of Charge Trapping on Memory Characteristics for HfO₂-Based Ferroelectric Field Effect Transistors

by Jianjian Wang, Jinshun Bi, Yannan Xu, Gang Niu, Mengxin Liu and Viktor Stempitsky

Nanomaterials 2023, 13(4), 638; https://doi.org/10.3390/nano13040638 - 06 Feb 2023

Cited by 1 | Viewed by 2763

Abstract

A full understanding of the impact of charge trapping on the memory window (MW) of HfO₂-based ferroelectric field effect transistors (FeFETs) will permit the design of program and erase protocols, which will guide the application of these devices and maximize their [...] Read more.

A full understanding of the impact of charge trapping on the memory window (MW) of HfO₂-based ferroelectric field effect transistors (FeFETs) will permit the design of program and erase protocols, which will guide the application of these devices and maximize their useful life. The effects of charge trapping have been studied by changing the parameters of the applied program and erase pulses in a test sequence. With increasing the pulse amplitude and pulse width, the MW increases first and then decreases, a result attributed to the competition between charge trapping (CT) and ferroelectric switching (FS). This interaction between CT and FS is analyzed in detail using a single-pulse technique. In addition, the experimental data show that the conductance modulation characteristics are affected by the CT in the analog synaptic behavior of the FeFET. Finally, a theoretical investigation is performed in Sentaurus TCAD, providing a plausible explanation of the CT effect on the memory characteristics of the FeFET. This work is helpful to the study of the endurance fatigue process caused by the CT effect and to optimizing the analog synaptic behavior of the FeFET. Full article

(This article belongs to the Special Issue Innovative Semiconducting Materials Technology toward New-Generation Hardware Applications)

► Show Figures

Figure 1

14 pages, 4088 KiB

Open AccessArticle

Mechanism of Random Telegraph Noise in 22-nm FDSOI-Based MOSFET at Cryogenic Temperatures

by Yue Ma, Jinshun Bi, Hanbin Wang, Linjie Fan, Biyao Zhao, Lizhi Shen and Mengxin Liu

Nanomaterials 2022, 12(23), 4344; https://doi.org/10.3390/nano12234344 - 06 Dec 2022

Cited by 1 | Viewed by 1899

Abstract

In the emerging process-based transistors, random telegraph noise (RTN) has become a critical reliability problem. However, the conventional method to analyze RTN properties may not be suitable for the advanced silicon-on-insulator (SOI)-based transistors, such as the fully depleted SOI (FDSOI)-based transistors. In this [...] Read more.

In the emerging process-based transistors, random telegraph noise (RTN) has become a critical reliability problem. However, the conventional method to analyze RTN properties may not be suitable for the advanced silicon-on-insulator (SOI)-based transistors, such as the fully depleted SOI (FDSOI)-based transistors. In this paper, the mechanism of RTN in a 22-nm FDSOI-based metal–oxide–semiconductor field-effect transistor (MOSFET) is discussed, and an improved approach to analyzing the relationship between the RTN time constants, the trap energy, and the trap depth of the device at cryogenic temperatures is proposed. The cryogenic measurements of RTN in a 22-nm FDSOI-based MOSFET were carried out and analyzed using the improved approach. In this approach, the quantum mechanical effects and diffuse scattering of electrons at the oxide–silicon interface are considered, and the slope of the trap potential determined by the gate voltage relation is assumed to decrease proportionally with temperature as a result of the electron distribution inside the top silicon, per the technology computer-aided design (TCAD) simulations. The fitted results of the improved approach have good consistency with the measured curves at cryogenic temperatures from 10 K to 100 K. The fitted trap depth was 0.13 nm, and the decrease in the fitted correction coefficient of the electron distribution proportionally with temperature is consistent with the aforementioned assumption. Full article

(This article belongs to the Special Issue Innovative Semiconducting Materials Technology toward New-Generation Hardware Applications)

► Show Figures

Figure 1

12 pages, 4763 KiB

Open AccessArticle

Hyper-FET’s Phase-Transition-Materials Design Guidelines for Ultra-Low Power Applications at 3 nm Technology Node

by Hanggyo Jung, Jeesoo Chang, Changhyun Yoo, Jooyoung Oh, Sumin Choi, Juyeong Song and Jongwook Jeon

Nanomaterials 2022, 12(22), 4096; https://doi.org/10.3390/nano12224096 - 21 Nov 2022

Cited by 4 | Viewed by 1652

Abstract

In this work, a hybrid-phase transition field-effects-transistor (hyper-FET) integrated with phase-transition materials (PTM) and a multi-nanosheet FET (mNS-FET) at the 3 nm technology node were analyzed at the device and circuit level. Through this, a benchmark was performed for presenting device design guidelines [...] Read more.

In this work, a hybrid-phase transition field-effects-transistor (hyper-FET) integrated with phase-transition materials (PTM) and a multi-nanosheet FET (mNS-FET) at the 3 nm technology node were analyzed at the device and circuit level. Through this, a benchmark was performed for presenting device design guidelines and for using ultra-low-power applications. We present an optimization flow considering hyper-FET characteristics at the device and circuit level, and analyze hyper-FET performance according to the phase transition time (TT) and baseline-FET off-leakage current (I_OFF) variations of the PTM. As a result of inverter ring oscillator (INV RO) circuit analysis, the optimized hyper-FET increases speed by +8.74% and reduces power consumption by −16.55%, with I_OFF = 5 nA of baseline-FET and PTM TT = 50 ps compared to the conventional mNS-FET in the ultra-low-power region. As a result of SRAM circuit analysis, the read static noise margin is improved by 43.9%, and static power is reduced by 58.6% in the near-threshold voltage region when the PTM is connected to the pull-down transistor source terminal of 6T SRAM for high density. This is achieved at 41% read current penalty. Full article

(This article belongs to the Special Issue Innovative Semiconducting Materials Technology toward New-Generation Hardware Applications)

► Show Figures

Figure 1

17 pages, 3313 KiB

Open AccessArticle

A Ti₃C₂T_x-Based Composite as Separator Coating for Stable Li-S Batteries

by Ruowei Yi, Yinchao Zhao, Chenguang Liu, Yi Sun, Chun Zhao, Yinqing Li, Li Yang and Cezhou Zhao

Nanomaterials 2022, 12(21), 3770; https://doi.org/10.3390/nano12213770 - 26 Oct 2022

Cited by 5 | Viewed by 1685

Abstract

The nitrogen-doped MXene carbon nanosheet-nickel (N-M@CNi) powder was successfully prepared by a combined process of electrostatic attraction and annealing strategy, and then applied as the separator coating in lithium–sulfur batteries. The morphology and structure of the N-M@CNi were characterized by transmission electron microscopy [...] Read more.

The nitrogen-doped MXene carbon nanosheet-nickel (N-M@CNi) powder was successfully prepared by a combined process of electrostatic attraction and annealing strategy, and then applied as the separator coating in lithium–sulfur batteries. The morphology and structure of the N-M@CNi were characterized by transmission electron microscopy (TEM), scanning electron microscopy (SEM), Raman spectrum, X-ray diffraction (XRD), X-ray photoelectron spectroscopy (XPS), and nitrogen adsorption–desorption method. The strong LiPS adsorption ability and high conductivity are associated with the N-doped carbon nanosheet-Ni modified surface. The modified separator offers the cathode of Li–S cell with greater sulfur utilization, better high-rate adaptability, and more stable cycling performance compared with the pristine separator. At 0.2 C the cell with N-M@CNi separator delivers an initial capacity of 1309 mAh g⁻¹. More importantly, the N-M@CNi separator is able to handle a cathode with 3.18 mg cm⁻² sulfur loading, delivering a capacity decay rate of 0.043% with a high capacity retention of 95.8%. Therefore, this work may provide a feasible approach to separator modification materials towards improved Li-S cells with improved stability. Full article

(This article belongs to the Special Issue Innovative Semiconducting Materials Technology toward New-Generation Hardware Applications)

► Show Figures

Figure 1

8 pages, 1823 KiB

Open AccessArticle

Improved Ferroelectric Properties in Hf_0.5Zr_0.5O₂ Thin Films by Microwave Annealing

by Biyao Zhao, Yunting Yan, Jinshun Bi, Gaobo Xu, Yannan Xu, Xueqin Yang, Linjie Fan and Mengxin Liu

Nanomaterials 2022, 12(17), 3001; https://doi.org/10.3390/nano12173001 - 30 Aug 2022

Cited by 4 | Viewed by 2289

Abstract

In the doped hafnia(HfO₂)-based films, crystallization annealing is indispensable in forming ferroelectric phases. In this paper, we investigate the annealing effects of TiN/Hf_0.5Zr_0.5O₂/TiN metal-ferroelectric-metal (MFM) capacitors by comparing microwave annealing (MWA) and rapid thermal annealing [...] Read more.

In the doped hafnia(HfO₂)-based films, crystallization annealing is indispensable in forming ferroelectric phases. In this paper, we investigate the annealing effects of TiN/Hf_0.5Zr_0.5O₂/TiN metal-ferroelectric-metal (MFM) capacitors by comparing microwave annealing (MWA) and rapid thermal annealing (RTA) at the same wafer temperature of 500 °C. The twofold remanent polarization (2Pr) of the MWA device is 63 µC/cm², surpassing that of the RTA device (40 µC/cm²). Furthermore, the wake-up effect is substantially inhibited in the MWA device. The orthorhombic crystalline phase is observed in the annealed HZO films in the MWA and RTA devices, with a reduced TiN and HZO interdiffusion in MWA devices. Moreover, the MFM capacitors subjected to MWA treatment exhibit a lower leakage current, indicating a decreased defect density. This investigation shows the potential of MWA for application in ferroelectric technology due to the improvement in remanent polarization, wake-up effect, and leakage current. Full article

(This article belongs to the Special Issue Innovative Semiconducting Materials Technology toward New-Generation Hardware Applications)

► Show Figures

Figure 1

11 pages, 4927 KiB

Open AccessArticle

Water-Induced Nanometer-Thin Crystalline Indium-Praseodymium Oxide Channel Layers for Thin-Film Transistors

by Wangying Xu, Chuyu Xu, Zhibo Zhang, Weicheng Huang, Qiubao Lin, Shuangmu Zhuo, Fang Xu, Xinke Liu, Deliang Zhu and Chun Zhao

Nanomaterials 2022, 12(16), 2880; https://doi.org/10.3390/nano12162880 - 22 Aug 2022

Cited by 3 | Viewed by 1347

Abstract

We report water-induced nanometer-thin crystalline indium praseodymium oxide (In-Pr-O) thin-film transistors (TFTs) for the first time. This aqueous route enables the formation of dense ultrathin (~6 nm) In-Pr-O thin films with near-atomic smoothness (~0.2 nm). The role of Pr doping is investigated by [...] Read more.

We report water-induced nanometer-thin crystalline indium praseodymium oxide (In-Pr-O) thin-film transistors (TFTs) for the first time. This aqueous route enables the formation of dense ultrathin (~6 nm) In-Pr-O thin films with near-atomic smoothness (~0.2 nm). The role of Pr doping is investigated by a battery of experimental techniques. It is revealed that as the Pr doping ratio increases from 0 to 10%, the oxygen vacancy-related defects could be greatly suppressed, leading to the improvement of TFT device characteristics and durability. The optimized In-Pr-O TFT demonstrates state-of-the-art electrical performance with mobility of 17.03 ± 1.19 cm²/Vs and on/off current ratio of ~10⁶ based on Si/SiO₂ substrate. This achievement is due to the low electronegativity and standard electrode potential of Pr, the high bond strength of Pr-O, same bixbyite structure of Pr₂O₃ and In₂O₃, and In-Pr-O channel’s nanometer-thin and ultrasmooth nature. Therefore, the designed In-Pr-O channel holds great promise for next-generation transistors. Full article

(This article belongs to the Special Issue Innovative Semiconducting Materials Technology toward New-Generation Hardware Applications)

► Show Figures

Figure 1

Review

Jump to: Research

21 pages, 6067 KiB

Open AccessReview

Memristor-Based Signal Processing for Compressed Sensing

by Rui Wang, Wanlin Zhang, Saisai Wang, Tonglong Zeng, Xiaohua Ma, Hong Wang and Yue Hao

Nanomaterials 2023, 13(8), 1354; https://doi.org/10.3390/nano13081354 - 13 Apr 2023

Cited by 3 | Viewed by 2200

Abstract

With the rapid progress of artificial intelligence, various perception networks were constructed to enable Internet of Things (IoT) applications, thereby imposing formidable challenges to communication bandwidth and information security. Memristors, which exhibit powerful analog computing capabilities, emerged as a promising solution expected to [...] Read more.

With the rapid progress of artificial intelligence, various perception networks were constructed to enable Internet of Things (IoT) applications, thereby imposing formidable challenges to communication bandwidth and information security. Memristors, which exhibit powerful analog computing capabilities, emerged as a promising solution expected to address these challenges by enabling the development of the next-generation high-speed digital compressed sensing (CS) technologies for edge computing. However, the mechanisms and fundamental properties of memristors for achieving CS remain unclear, and the underlying principles for selecting different implementation methods based on various application scenarios have yet to be elucidated. A comprehensive overview of memristor-based CS techniques is currently lacking. In this article, we systematically presented CS requirements on device performance and hardware implementation. The relevant models were analyzed and discussed from the mechanism level to elaborate the memristor CS system scientifically. In addition, the method of deploying CS hardware using the powerful signal processing capabilities and unique performance of memristors was further reviewed. Subsequently, the potential of memristors in all-in-one compression and encryption was anticipated. Finally, existing challenges and future outlooks for memristor-based CS systems were discussed. Full article

(This article belongs to the Special Issue Innovative Semiconducting Materials Technology toward New-Generation Hardware Applications)

► Show Figures

Figure 1

24 pages, 7809 KiB

Open AccessReview

Low-Dimensional-Materials-Based Flexible Artificial Synapse: Materials, Devices, and Systems

by Qifeng Lu, Yinchao Zhao, Long Huang, Jiabao An, Yufan Zheng and Eng Hwa Yap

Nanomaterials 2023, 13(3), 373; https://doi.org/10.3390/nano13030373 - 17 Jan 2023

Cited by 7 | Viewed by 2554

Abstract

With the rapid development of artificial intelligence and the Internet of Things, there is an explosion of available data for processing and analysis in any domain. However, signal processing efficiency is limited by the Von Neumann structure for the conventional computing system. Therefore, [...] Read more.

With the rapid development of artificial intelligence and the Internet of Things, there is an explosion of available data for processing and analysis in any domain. However, signal processing efficiency is limited by the Von Neumann structure for the conventional computing system. Therefore, the design and construction of artificial synapse, which is the basic unit for the hardware-based neural network, by mimicking the structure and working mechanisms of biological synapses, have attracted a great amount of attention to overcome this limitation. In addition, a revolution in healthcare monitoring, neuro-prosthetics, and human–machine interfaces can be further realized with a flexible device integrating sensing, memory, and processing functions by emulating the bionic sensory and perceptual functions of neural systems. Until now, flexible artificial synapses and related neuromorphic systems, which are capable of responding to external environmental stimuli and processing signals efficiently, have been extensively studied from material-selection, structure-design, and system-integration perspectives. Moreover, low-dimensional materials, which show distinct electrical properties and excellent mechanical properties, have been extensively employed in the fabrication of flexible electronics. In this review, recent progress in flexible artificial synapses and neuromorphic systems based on low-dimensional materials is discussed. The potential and the challenges of the devices and systems in the application of neuromorphic computing and sensory systems are also explored. Full article

(This article belongs to the Special Issue Innovative Semiconducting Materials Technology toward New-Generation Hardware Applications)

► Show Figures

Figure 1

Journal Menu

Journal Browser

Innovative Semiconducting Materials Technology toward New-Generation Hardware Applications

Share This Special Issue

Special Issue Editors

Special Issue Information

Keywords

Published Papers (8 papers)

Research

Review

Further Information

Guidelines

MDPI Initiatives

Follow MDPI