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Applied Sciences
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Device and Integration Technology of Microelectronics
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Device and Integration Technology of Microelectronics

A special issue of Applied Sciences (ISSN 2076-3417). This special issue belongs to the section "Electrical, Electronics and Communications Engineering".

Deadline for manuscript submissions: closed (20 June 2023) | Viewed by 2013

Special Issue Editors

Prof. Zhengsheng Han

E-Mail Website
Guest Editor
Institute of Microelectronics of Chinese Academy of Sciences, Beijing 100029, China
Interests: integrated circuit technique
Prof. Dr. Jinshun Bi

E-Mail Website
Guest Editor
Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China
Interests: integrated circuit technique and reliability issues
Prof. Dr. Gang Niu

E-Mail Website
Guest Editor
Electronic Materials Research Laboratory, Key Laboratory of the Ministry of Education & International Center for Dielectric Research, School of Electronic Science and Engineering, Xi’an Jiaotong University, Xi’an 710049, China
Interests: post-Moore information materials and devices
Dr. Chun Zhao

E-Mail Website
Guest Editor
School of Advanced Technology, Xi'an Jiaotong–Liverpool University, Suzhou 21500, China
Interests: third/fourth-generation novel semiconductors; wide bandgap metal oxide; advanced synaptic electronic devices and their artificial intelligence applications (AI-integrated circuit); wearable electronics with integration of bio-sensors and TENG
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

Dear Colleagues,

The basic and core content of microelectronics is the semiconductor devices. These devices help with miniaturization and integration through advanced integration technology. The development of devices in the post-Moore era occurs mainly through two aspects. On the one hand, devices continue to be scaled down, but the focus of optimization is both performance and power consumption. On the other hand, the development of devices is diversified, and various devices prepared with new structures, new principles or new methods have emerged. As for integration technology, three-dimensional vertical integration plays the key role in its effective scaling down at this stage. This solves the contradiction between the planar resolution bottleneck and the requirement to increase the density.

This Special Issue intends to present new ideas and experimental results in the field of advanced devices and integration technology of microelectronics, evolving it from theories, simulations, processes and experiments to practical uses. Areas relevant to this field include, but are not limited to, new processes, novel devices, advanced integration technology and applications.

This Special Issue will publish original, high-quality research papers on topics including, but not limited to, the following:

  • Advances in various conventional micro/nanoelectronic devices (optoelectronics, power devices, sensors, bioelectronics, etc.).
  • Emerging micro/nanoelectronic devices and physics (tunnel FET, 2D materials, CNTs, nanowires, etc.).
  • Device and integration technology of memory, including advances in both conventional memories (SRAM, DRAM and Flash) and emerging memories (RRAM, MRAM, PRAM and FeRAM).
  • Integration technology of microelectronics (2.5D/3D/heterogeneous integration, novel integration schemes for advanced nodes, integrated implementations of power/optical/biodevices, etc.).
  • Electrical and physical characterization, reliability evaluation and yield analysis of device and integration technology of microelectronics.

Prof. Zhengsheng Han
Prof. Dr. Jinshun Bi
Prof. Dr. Gang Niu
Dr. Chun Zhao
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Applied Sciences is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • emerging devices
  • integration technology
  • technology of memory
  • reliability evaluation

Published Papers (2 papers)

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12 pages, 988 KiB  
Article
Prediction of Microwave Characteristic Parameters Based on MMIC Gold Wire Bonding
by Shenglin Yu and Hao Li
Appl. Sci. 2023, 13(17), 9631; https://doi.org/10.3390/app13179631 - 25 Aug 2023
Viewed by 669
Abstract
In this paper, a method based on deep learning is proposed to predict the parameters of bonded metal wires, which solves the problem that the transmission characteristics of S-parameters cannot be predicted. In an X-band microwave chip circuit, gold wire bonding technology is [...] Read more.
In this paper, a method based on deep learning is proposed to predict the parameters of bonded metal wires, which solves the problem that the transmission characteristics of S-parameters cannot be predicted. In an X-band microwave chip circuit, gold wire bonding technology is often used to realize bonding interconnection, and the arch height and span of the bonded metal wire will have a great influence on the microwave transmission characteristics. By predicting the S-parameters of the bonded metal wire, the relationship between the structure parameters of the single wire and the transmission performance of the microwave device can be deduced. First, the gold wire bonding model is established in HFSS simulation software. After parameter optimization, the simulation results meet the requirements of establishing data sets. Then the sampling range of S parameters is set, and the parameters are scanned to establish data sets. Second, the artificial neural network model is built. The model adds a dropout mechanism to the hidden layer to enhance the generalization of the neural network, prevent overfitting phenomenon, and significantly improve the model’s prediction performance. Finally, the model predicts the corresponding relationship between the arch height and span of the bonding wire and the insertion loss, return loss and standing wave ratio. The mean square error of the test set is less than 0.8. The experimental results show that compared with the traditional process measurement method, this method can quickly and accurately infer whether the microwave characteristics of the bonded product are qualified, which greatly reduces the time and economic cost of the engineer and improves the work efficiency. Full article
(This article belongs to the Special Issue Device and Integration Technology of Microelectronics)
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12 pages, 2241 KiB  
Article
Research on an Intelligent Test Method for Interconnect Resources in an FPGA
by Weikun Xie, Wenjing Qi, Xiaohui Lin and Houjun Wang
Appl. Sci. 2023, 13(13), 7951; https://doi.org/10.3390/app13137951 - 7 Jul 2023
Viewed by 909
Abstract
With the rapid development of integrated circuit production technology, the scale of FPGA circuits has expanded to billions of gates. The complexity of the internal resource structures in the FPGAs (field programmable gate arrays) is continually increasing, and there is an increasing possibility [...] Read more.
With the rapid development of integrated circuit production technology, the scale of FPGA circuits has expanded to billions of gates. The complexity of the internal resource structures in the FPGAs (field programmable gate arrays) is continually increasing, and there is an increasing possibility of various faults in these circuits, especially in interconnect resources. These occupy more than 80% of a chip’s area and have the highest fault rate. To ensure the reliability of the FPGAs, it is very important to perform high-coverage testing on the interconnect resources within them. This article uses AMD Xilinx’s Kintex-7 series FPGA as the research object and proposes a deep-priority algorithm based on graph-based models and improved priority algorithms to intelligently wire the FPGA interconnected resources. The routing results were produced using a configuration script written in the XDL language, and the FPGA configuration and testing were conducted accordingly. This approach achieved a high coverage and intelligent testing for the interconnect resources in the FPGAs. Full article
(This article belongs to the Special Issue Device and Integration Technology of Microelectronics)
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