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32 pages, 6975 KiB

Open AccessArticle

Cost-Efficient Approaches for Fulfillment of Functional Coverage during Verification of Digital Designs

by Alexandru Dinu, Gabriel Mihail Danciu and Petre Lucian Ogrutan

Micromachines 2022, 13(5), 691; https://doi.org/10.3390/mi13050691 - 28 Apr 2022

Cited by 5 | Viewed by 1532

Abstract

Digital integrated circuits play an important role in the development of new information technologies and support Industry 4.0 from a hardware point of view. There is great pressure on electronics companies to reduce the time-to-market for product development as much as possible. The [...] Read more.

Digital integrated circuits play an important role in the development of new information technologies and support Industry 4.0 from a hardware point of view. There is great pressure on electronics companies to reduce the time-to-market for product development as much as possible. The most time-consuming stage in hardware development is functional verification. As a result, many industry and academic stakeholders are investing in automating this crucial step in electronics production. The present work aims to automate the functional verification process by means of genetic algorithms that are used for generating the relevant input stimuli for full simulation of digital design behavior. Two important aspects are pursued throughout the current work: the implementation of genetic algorithms must be time-worthy compared to the application of the classical constrained-driven generation and the verification process must be implemented using tools accessible to a wide range of practitioners. It is demonstrated that for complex designs, functional verification powered by the use of genetic algorithms can go beyond the classical method of performing verification, which is based on constrained-random stimulus generation. The currently proposed methods were able to generate several sets of highly performing stimuli compared to the constraint-random stimulus generation method, in a ratio ranging from 57:1 to 205:1. The performance of the proposed approaches is comparable to that of the well-known NSGA-II and SPEA2 algorithms. Full article

(This article belongs to the Special Issue Smart Embedded Processors)

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35 pages, 6438 KiB

Open AccessArticle

Design of FPGA-Based SHE and SPWM Digital Switching Controllers for 21-Level Cascaded H-Bridge Multilevel Inverter Model

by Emilia Noorsal, Asyraf Rongi, Intan Rahayu Ibrahim, Rosheila Darus, Daniel Kho and Samsul Setumin

Micromachines 2022, 13(2), 179; https://doi.org/10.3390/mi13020179 - 25 Jan 2022

Cited by 11 | Viewed by 3430

Abstract

Multilevel inverters are a type of power electronic circuit that converts direct current (DC) to alternating current (AC) for use in high-voltage and high-power applications. Many recent studies on multilevel inverters have used field-programmable gate arrays (FPGAs) as a switching controller device to [...] Read more.

Multilevel inverters are a type of power electronic circuit that converts direct current (DC) to alternating current (AC) for use in high-voltage and high-power applications. Many recent studies on multilevel inverters have used field-programmable gate arrays (FPGAs) as a switching controller device to overcome the limitations of microcontrollers or DSPs, such as limited sampling rate, low execution speed, and a limited number of IO pins. However, the design techniques of most existing FPGA-based switching controllers require large amounts of memory (RAM) for storage of sampled data points as well as complex controller architectures to generate the output gating pulses. Therefore, in this paper, we propose two types of FPGA-based digital switching controllers, namely selective harmonic elimination (SHE) and sinusoidal pulse width modulation (SPWM), for a 21-level multilevel inverter. Both switching controllers were designed with minimal hardware complexity and logic utilisation. The designed SHE switching controller mainly consists of a four-bit finite state machine (FSM) and a 13-bit counter, while the SPWM switching controller employs a simple iterative CORDIC algorithm with a small amount of data storage requirement, a six-bit up-down counter, and a few adders. Initially, both digital switching controllers (SHE and SPWM) were designed using the hardware description language (HDL) in Verilog codes and functionally verified using the developed testbenches. The designed digital switching controllers were then synthesised and downloaded to the Intel FPGA (DE2-115) board for real-time verification purposes. For system-level verification, both switching controllers were tested on five cascaded H-Bridge circuits for a 21-level multilevel inverter model using the HDL co-simulation method in MATLAB Simulink. From the synthesised logic gates, it was found that the designed SHE and SPWM switching controllers require only 186 and 369 logic elements (LEs), respectively, which is less than 1% of the total LEs in an FPGA (Cyclone IV E) chip. The execution speed of the SHE switching controller implemented in the FPGA (Cyclone IV E) chip was found to be a maximum of 99.97% faster when compared with the microcontroller (PIC16F877A). The THD percentage of the 21-level SHE digital switching controller (3.91%) was found to be 37% less than that of the SPWM digital switching controller (6.17%). In conclusion, the proposed simplified design architectures of SHE and SPWM digital switching controllers have been proven to not only require minimal logic resources, achieve high processing speeds, and function correctly when tested on a real-time FPGA board, but also generate the desired 21-level stepped sine-wave output voltage (±360 V_PP) at a frequency of 50 Hz with low THD percentages when tested on a 21-level cascaded H-Bridge multilevel inverter model. Full article

(This article belongs to the Special Issue Smart Embedded Processors)

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14 pages, 2498 KiB

Open AccessArticle

Open-Source FPGA Coprocessor for the Doppler Emulation of Moving Fluids

by Stefano Ricci

Micromachines 2021, 12(12), 1549; https://doi.org/10.3390/mi12121549 - 12 Dec 2021

Cited by 2 | Viewed by 1970

Abstract

Embedded systems are nowadays employed in a wide range of application, and their capability to implement calculation-intensive algorithms is growing quickly and constantly. This result is obtained by the exploitation of powerful embedded processors that are often connected to coprocessors optimized for a [...] Read more.

Embedded systems are nowadays employed in a wide range of application, and their capability to implement calculation-intensive algorithms is growing quickly and constantly. This result is obtained by the exploitation of powerful embedded processors that are often connected to coprocessors optimized for a particular application. This work presents an open-source coprocessor dedicated to the real-time generation of a synthetic signal that mimics the echoes produced by a moving fluid when investigated by ultrasounds. The coprocessor is implemented in a Field Programmable Gate Array (FPGA) device and integrated in an embedded system. The system can replace the complex and inaccurate flow-rigs employed in laboratorial tests of Doppler ultrasound systems and methods. This paper details the coprocessor and its standard interfaces, and shows how it can be integrated in the wider architecture of an embedded system. Experiments showed its capability to emulate a fluid flowing in a pipe when investigated by an echographic Doppler system. Full article

(This article belongs to the Special Issue Smart Embedded Processors)

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12 pages, 3393 KiB

Open AccessArticle

An FPGA-Based ECU for Remote Reconfiguration in Automotive Systems

by Kwonneung Cho, Jeongeun Kim, Do Young Choi, Young Hyun Yoon, Jung Hwan Oh and Seung Eun Lee

Micromachines 2021, 12(11), 1309; https://doi.org/10.3390/mi12111309 - 26 Oct 2021

Cited by 9 | Viewed by 3698

Abstract

Growing interest in intelligent vehicles is leading automotive systems to include numerous electronic control units (ECUs) inside. As a result, efficient implementation and management of automotive systems is gaining importance. Flexible updating and reconfiguration of ECUs is one appropriate strategy for these goals. [...] Read more.

Growing interest in intelligent vehicles is leading automotive systems to include numerous electronic control units (ECUs) inside. As a result, efficient implementation and management of automotive systems is gaining importance. Flexible updating and reconfiguration of ECUs is one appropriate strategy for these goals. Software updates to the ECUs are expected to improve performance and bug handling, but there are limitations due to the fixed hardware circuit. By applying hardware-reconfigurable ECUs to the automotive system, patches that are not able to be handled with only software updates are enabled. In this paper, a remotely hardware-reconfigurable ECU for automotive systems is proposed. The proposed ECU is implemented with a field programmable gate array (FPGA) and microcontroller unit (MCU) to support in-system reconfiguration (ISR). The communication interface between the FPGA and MCU employs Zipwire communication for high speed and resilient communication. For the Zipwire communication, a Zipwire controller is designed and implemented in the FPGA. The proposed hardware-reconfigurable ECU was successfully implemented, and feasibility was demonstrated. Full article

(This article belongs to the Special Issue Smart Embedded Processors)

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35 pages, 11116 KiB

Open AccessArticle

Design of an FPGA-Based Fuzzy Feedback Controller for Closed-Loop FES in Knee Joint Model

by Emilia Noorsal, Saharul Arof, Saiful Zaimy Yahaya, Zakaria Hussain, Daniel Kho and Yusnita Mohd Ali

Micromachines 2021, 12(8), 968; https://doi.org/10.3390/mi12080968 - 16 Aug 2021

Cited by 9 | Viewed by 3412

Abstract

Functional electrical stimulation (FES) device has been widely used by spinal cord injury (SCI) patients in their rehab exercises to restore motor function to their paralysed muscles. The major challenge of muscle contraction induced by FES is early muscle fatigue due to the [...] Read more.

Functional electrical stimulation (FES) device has been widely used by spinal cord injury (SCI) patients in their rehab exercises to restore motor function to their paralysed muscles. The major challenge of muscle contraction induced by FES is early muscle fatigue due to the open-loop stimulation strategy. To reduce the early muscle fatigue phenomenon, a closed-loop FES system is proposed to track the angle of the limb’s movement and provide an accurate amount of charge according to the desired reference angle. Among the existing feedback controllers, fuzzy logic controller (FLC) has been found to exhibit good control performance in handling complex non-linear systems without developing any complex mathematical model. Recently, there has been considerable interest in the implementation of FLC in hardware embedded systems. Therefore, in this paper, a digital fuzzy feedback controller (FFC) embedded in a field-programmable gate array (FPGA) board was proposed. The digital FFC mainly consists of an analog-to-digital converter (ADC) Data Acquisition and FLC sub-modules. The FFC was designed to monitor and control the progress of knee extension movement by regulating the stimulus pulse width duration to meet the target angle. The knee is expected to extend to a maximum reference angle setting (70°, 40° or 30°) from its normal position of 0° once the stimulus charge is applied to the muscle by the FES device. Initially, the FLC was modelled using MATLAB Simulink. Then, the FLC was hardcoded into digital logic using hardware description language (HDL) Verilog codes. Thereafter, the performance of the digital FLC was tested with a knee extension model using the HDL co-simulation technique in MATLAB Simulink. Finally, for real-time verification, the designed digital FFC was downloaded to the Intel FPGA (DE2-115) board. The digital FFC utilized only 4% of the total FPGA (Cyclone IV E) logic elements (LEs) and required 238 µs to regulate stimulus pulse width data, including 3 µs for the FLC computation. The high processing speed of the digital FFC enables the stimulus pulse width duration to be updated every stimulation cycle. Furthermore, the implemented digital FFC has demonstrated good control performance in accurately controlling the stimulus pulse width duration to reach the desired reference angle with very small overshoot (1.4°) and steady-state error (0.4°). These promising results are very useful for a real-world closed-loop FES application. Full article

(This article belongs to the Special Issue Smart Embedded Processors)

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16 pages, 4817 KiB

Open AccessArticle

A Multi-Core Controller for an Embedded AI System Supporting Parallel Recognition

by Suyeon Jang, Hyun Woo Oh, Young Hyun Yoon, Dong Hyun Hwang, Won Sik Jeong and Seung Eun Lee

Micromachines 2021, 12(8), 852; https://doi.org/10.3390/mi12080852 - 21 Jul 2021

Cited by 3 | Viewed by 2549

Abstract

Recent advances in artificial intelligence (AI) technology encourage the adoption of AI systems for various applications. In most deployments, AI-based computing systems adopt the architecture in which the central server processes most of the data. This characteristic makes the system use a high [...] Read more.

Recent advances in artificial intelligence (AI) technology encourage the adoption of AI systems for various applications. In most deployments, AI-based computing systems adopt the architecture in which the central server processes most of the data. This characteristic makes the system use a high amount of network bandwidth and can cause security issues. In order to overcome these issues, a new AI model called federated learning was presented. Federated learning adopts an architecture in which the clients take care of data training and transmit only the trained result to the central server. As the data training from the client abstracts and reduces the original data, the system operates with reduced network resources and reinforced data security. A system with federated learning supports a variety of client systems. To build an AI system with resource-limited client systems, composing the client system with multiple embedded AI processors is valid. For realizing the system with this architecture, introducing a controller to arbitrate and utilize the AI processors becomes a stringent requirement. In this paper, we propose an embedded AI system for federated learning that can be composed flexibly with the AI core depending on the application. In order to realize the proposed system, we designed a controller for multiple AI cores and implemented it on a field-programmable gate array (FPGA). The operation of the designed controller was verified through image and speech applications, and the performance was verified through a simulator. Full article

(This article belongs to the Special Issue Smart Embedded Processors)

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12 pages, 1008 KiB

Open AccessArticle

ASimOV: A Framework for Simulation and Optimization of an Embedded AI Accelerator

by Dong Hyun Hwang, Chang Yeop Han, Hyun Woo Oh and Seung Eun Lee

Micromachines 2021, 12(7), 838; https://doi.org/10.3390/mi12070838 - 19 Jul 2021

Cited by 7 | Viewed by 3458

Abstract

Artificial intelligence algorithms need an external computing device such as a graphics processing unit (GPU) due to computational complexity. For running artificial intelligence algorithms in an embedded device, many studies proposed light-weighted artificial intelligence algorithms and artificial intelligence accelerators. In this paper, we [...] Read more.

Artificial intelligence algorithms need an external computing device such as a graphics processing unit (GPU) due to computational complexity. For running artificial intelligence algorithms in an embedded device, many studies proposed light-weighted artificial intelligence algorithms and artificial intelligence accelerators. In this paper, we propose the ASimOV framework, which optimizes artificial intelligence algorithms and generates Verilog hardware description language (HDL) code for executing intelligence algorithms in field programmable gate array (FPGA). To verify ASimOV, we explore the performance space of k-NN algorithms and generate Verilog HDL code to demonstrate the k-NN accelerator in FPGA. Our contribution is to provide the artificial intelligence algorithm as an end-to-end pipeline and ensure that it is optimized to a specific dataset through simulation, and an artificial intelligence accelerator is generated in the end. Full article

(This article belongs to the Special Issue Smart Embedded Processors)

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24 pages, 772 KiB

Open AccessArticle

High-Efficiency Parallel Cryptographic Accelerator for Real-Time Guaranteeing Dynamic Data Security in Embedded Systems

by Zhun Zhang, Xiang Wang, Qiang Hao, Dongdong Xu, Jinlei Zhang, Jiakang Liu and Jinhui Ma

Micromachines 2021, 12(5), 560; https://doi.org/10.3390/mi12050560 - 15 May 2021

Cited by 7 | Viewed by 2963

Abstract

Dynamic data security in embedded systems is raising more and more concerns in numerous safety-critical applications. In particular, the data exchanges in embedded Systems-on-Chip (SoCs) using main memory are exposing many security vulnerabilities to external attacks, which will cause confidential information leakages and [...] Read more.

Dynamic data security in embedded systems is raising more and more concerns in numerous safety-critical applications. In particular, the data exchanges in embedded Systems-on-Chip (SoCs) using main memory are exposing many security vulnerabilities to external attacks, which will cause confidential information leakages and program execution failures for SoCs at key points. Therefore, this paper presents a security SoC architecture with integrating a four-parallel Advanced Encryption Standard-Galois/Counter Mode (AES-GCM) cryptographic accelerator for achieving high-efficiency data processing to guarantee data exchange security between the SoC and main memory against bus monitoring, off-line analysis, and data tampering attacks. The architecture design has been implemented and verified on a Xilinx Virtex-5 Field Programmable Gate Array (FPGA) platform. Based on evaluation of the cryptographic accelerator in terms of performance overhead, security capability, processing efficiency, and resource consumption, experimental results show that the parallel cryptographic accelerator does not incur significant performance overhead on providing confidentiality and integrity protections for exchanged data; its average performance overhead reduces to as low as 2.65% on typical 8-KB I/D-Caches, and its data processing efficiency is around 3 times that of the pipelined AES-GCM construction. The reinforced SoC under the data tampering attacks and benchmark tests confirms the effectiveness against external physical attacks and satisfies a good trade-off between high-efficiency and hardware overhead. Full article

(This article belongs to the Special Issue Smart Embedded Processors)

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11 pages, 1137 KiB

Open AccessArticle

Lossless Decompression Accelerator for Embedded Processor with GUI

by Gwan Beom Hwang, Kwon Neung Cho, Chang Yeop Han, Hyun Woo Oh, Young Hyun Yoon and Seung Eun Lee

Micromachines 2021, 12(2), 145; https://doi.org/10.3390/mi12020145 - 31 Jan 2021

Cited by 5 | Viewed by 2718

Abstract

The development of the mobile industry brings about the demand for high-performance embedded systems in order to meet the requirement of user-centered application. Because of the limitation of memory resource, employing compressed data is efficient for an embedded system. However, the workload for [...] Read more.

The development of the mobile industry brings about the demand for high-performance embedded systems in order to meet the requirement of user-centered application. Because of the limitation of memory resource, employing compressed data is efficient for an embedded system. However, the workload for data decompression causes an extreme bottleneck to the embedded processor. One of the ways to alleviate the bottleneck is to integrate a hardware accelerator along with the processor, constructing a system-on-chip (SoC) for the embedded system. In this paper, we propose a lossless decompression accelerator for an embedded processor, which supports LZ77 decompression and static Huffman decoding for an inflate algorithm. The accelerator is implemented on a field programmable gate array (FPGA) to verify the functional suitability and fabricated in a Samsung 65 nm complementary metal oxide semiconductor (CMOS) process. The performance of the accelerator is evaluated by the Canterbury corpus benchmark and achieved throughput up to 20.7 MB/s at 50 MHz system clock frequency. Full article

(This article belongs to the Special Issue Smart Embedded Processors)

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Review

Jump to: Research

22 pages, 4053 KiB

Open AccessReview

Advancements in Microprocessor Architecture for Ubiquitous AI—An Overview on History, Evolution, and Upcoming Challenges in AI Implementation

by Fatima Hameed Khan, Muhammad Adeel Pasha and Shahid Masud

Micromachines 2021, 12(6), 665; https://doi.org/10.3390/mi12060665 - 06 Jun 2021

Cited by 11 | Viewed by 10800

Abstract

Artificial intelligence (AI) has successfully made its way into contemporary industrial sectors such as automobiles, defense, industrial automation 4.0, healthcare technologies, agriculture, and many other domains because of its ability to act autonomously without continuous human interventions. However, this capability requires processing huge [...] Read more.

Artificial intelligence (AI) has successfully made its way into contemporary industrial sectors such as automobiles, defense, industrial automation 4.0, healthcare technologies, agriculture, and many other domains because of its ability to act autonomously without continuous human interventions. However, this capability requires processing huge amounts of learning data to extract useful information in real time. The buzz around AI is not new, as this term has been widely known for the past half century. In the 1960s, scientists began to think about machines acting more like humans, which resulted in the development of the first natural language processing computers. It laid the foundation of AI, but there were only a handful of applications until the 1990s due to limitations in processing speed, memory, and computational power available. Since the 1990s, advancements in computer architecture and memory organization have enabled microprocessors to deliver much higher performance. Simultaneously, improvements in the understanding and mathematical representation of AI gave birth to its subset, referred to as machine learning (ML). ML includes different algorithms for independent learning, and the most promising ones are based on brain-inspired techniques classified as artificial neural networks (ANNs). ANNs have subsequently evolved to have deeper and larger structures and are often characterized as deep neural networks (DNN) and convolution neural networks (CNN). In tandem with the emergence of multicore processors, ML techniques started to be embedded in a range of scenarios and applications. Recently, application-specific instruction-set architecture for AI applications has also been supported in different microprocessors. Thus, continuous improvement in microprocessor capabilities has reached a stage where it is now possible to implement complex real-time intelligent applications like computer vision, object identification, speech recognition, data security, spectrum sensing, etc. This paper presents an overview on the evolution of AI and how the increasing capabilities of microprocessors have fueled the adoption of AI in a plethora of application domains. The paper also discusses the upcoming trends in microprocessor architectures and how they will further propel the assimilation of AI in our daily lives. Full article

(This article belongs to the Special Issue Smart Embedded Processors)

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