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Micromachines
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Smart Embedded Systems: A Self-Aware System-on-Chip (SoC) and Applications
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Smart Embedded Systems: A Self-Aware System-on-Chip (SoC) and Applications

A special issue of Micromachines (ISSN 2072-666X). This special issue belongs to the section "E：Engineering and Technology".

Deadline for manuscript submissions: closed (30 April 2022) | Viewed by 9078

Special Issue Editor

Prof. Dr. Wen-Jyi Hwang

E-Mail Website
Guest Editor
Department of Computer Science and Information Engineering, National Taiwan Normal University, Taipei 10610, Taiwan
Interests: internet of things; system on a chip; artificial intelligence; gesture recognition
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

Dear Colleagues,

A common feature across diverse sets of embedded systems is the need for correct operation in the face of highly dynamic environmental conditions and changing application characteristics. Depending on the embedded system context, the corresponding architectures are highly customized to achieve the often-conflicting constraints of performance, energy efficiency, and reliability. Given the increasing complexity of tasks faced by embedded systems, smart cyberphysical systems are the major focus for SoC implementations, which allow the resulting embedded systems to be self-aware, adaptive, and achieve a high level of resilience in the face of highly dynamic and unpredictable environments.

The scope of this Special Issue is on smart embedded systems for novel cyberphysical applications, especially regarding embedded systems hardware. This Special Issue provides an excellent opportunity for communities from both research and industry to present new results. Of special interest are contributions that describe new methods, architectures, and applications of a self-aware system-on-chip (SoC). The topics of this Special Issue include but are not limited to cyberphysical SoC for smart embedded systems design and self-awareness for the design of architectural, physical, and circuit layers of SoC systems.

Prof. Dr. Wen-Jyi Hwang
Guest Editor

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Micromachines is an international peer-reviewed open access monthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2600 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • system-on-chip (SoC)
  • multiprocessor system-on-chips (MPSoCs)
  • sensor network-on-chip (sNoC)
  • communication network-on-Chip (cNoC)
  • self-aware system-on-chip (SoC)
  • cyberphysical system-on-chip
  • deep learning hardware

Published Papers (4 papers)

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Research

14 pages, 1480 KiB  
Article
Limited Duplication-Based List Scheduling Algorithm for Heterogeneous Computing System
by Hong Guo, Jiayin Zhou and Haonan Gu
Micromachines 2022, 13(7), 1067; https://doi.org/10.3390/mi13071067 - 03 Jul 2022
Cited by 4 | Viewed by 1332
Abstract
Efficient scheduling algorithms have been a leading research topic for heterogeneous computing systems. Although duplication-based scheduling algorithms can significantly reduce the total completion time, they are generally accompanied by an exorbitant time complexity. In this paper, we propose a new task duplication-based heuristic [...] Read more.
Efficient scheduling algorithms have been a leading research topic for heterogeneous computing systems. Although duplication-based scheduling algorithms can significantly reduce the total completion time, they are generally accompanied by an exorbitant time complexity. In this paper, we propose a new task duplication-based heuristic scheduling algorithm, LDLS, that can reduce the total completion time and maintains a low time complexity. The scheduling procedure of LDLS is composed of three main phases: In the beginning phase, the maximum number of duplications per level and per task is calculated to prevent excessive duplications from blocking regular tasks. In the next phase, the optimistic cost table (OCT) and ranking of tasks are calculated with reference to PEFT. In the final phase, scheduling is conducted based on the ranking, and the duplication of each task is dynamically determined, enabling the duplicated tasks to effectively reduce the start execution time of its successor tasks. Experiments of algorithms on randomly generated graphs and real-world applications indicate that both the scheduling length and the number of better case occurrences of LDLS are better than others. Full article
(This article belongs to the Special Issue Smart Embedded Systems: A Self-Aware System-on-Chip (SoC) and Applications)
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18 pages, 5041 KiB  
Article
Deep Q-Learning with Bit-Swapping-Based Linear Feedback Shift Register fostered Built-In Self-Test and Built-In Self-Repair for SRAM
by Mohammed Altaf Ahmed and Suleman Alnatheer
Micromachines 2022, 13(6), 971; https://doi.org/10.3390/mi13060971 - 19 Jun 2022
Cited by 5 | Viewed by 1955
Abstract
Including redundancy is popular and widely used in a fault-tolerant method for memories. Effective fault-tolerant methods are a demand of today’s large-size memories. Recently, system-on-chips (SOCs) have been developed in nanotechnology, with most of the chip area occupied by memories. Generally, memories in [...] Read more.
Including redundancy is popular and widely used in a fault-tolerant method for memories. Effective fault-tolerant methods are a demand of today’s large-size memories. Recently, system-on-chips (SOCs) have been developed in nanotechnology, with most of the chip area occupied by memories. Generally, memories in SOCs contain various sizes with poor accessibility. Thus, it is not easy to repair these memories with the conventional external equipment test method. For this reason, memory designers commonly use the redundancy method for replacing rows–columns with spare ones mainly to improve the yield of the memories. In this manuscript, the Deep Q-learning (DQL) with Bit-Swapping-based linear feedback shift register (BSLFSR) for Fault Detection (DQL-BSLFSR-FD) is proposed for Static Random Access Memory (SRAM). The proposed Deep Q-learning-based memory built-in self-test (MBIST) is used to check the memory array unit for faults. The faults are inserted into the memory using the Deep Q-learning fault injection process. The test patterns and faults injection are controlled during testing using different test cases. Subsequently, fault memory is repaired after inserting faults in the memory cell using the Bit-Swapping-based linear feedback shift register (BSLFSR) based Built-In Self-Repair (BISR) model. The BSLFSR model performs redundancy analysis that detects faulty cells, utilizing spare rows and columns instead of defective cells. The design and implementation of the proposed BIST and Built-In Self-Repair methods are developed on FPGA, and Verilog’s simulation is conducted. Therefore, the proposed DQL-BSLFSR-FD model simulation has attained 23.5%, 29.5% lower maximum operating frequency (minimum clock period), and 34.9%, 26.7% lower total power consumption than the existing approaches. Full article
(This article belongs to the Special Issue Smart Embedded Systems: A Self-Aware System-on-Chip (SoC) and Applications)
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24 pages, 4317 KiB  
Article
Novel Record Replacement Algorithm and Architecture for QoS Management over Local Area Networks
by Yi-Chih Tung, Yuk-Wing Law, Wen-Jyi Hwang, Tsung-Ming Tai, Chih-Hsiang Ho and Cheng-Chang Chen
Micromachines 2022, 13(4), 594; https://doi.org/10.3390/mi13040594 - 10 Apr 2022
Viewed by 1519
Abstract
An effective System-on-Chip (SoC) for smart Quality-of-Service (QoS) management over a virtual local area network (LAN) is presented in this study. The SoC is implemented by field programmable gate array (FPGA) for accelerating the delivery quality prediction for a service. The quality prediction [...] Read more.
An effective System-on-Chip (SoC) for smart Quality-of-Service (QoS) management over a virtual local area network (LAN) is presented in this study. The SoC is implemented by field programmable gate array (FPGA) for accelerating the delivery quality prediction for a service. The quality prediction is carried out by the general regression neural network (GRNN) algorithm based on a time-varying profile consisting of the past delivery records of the service. A novel record replacement algorithm is presented to update the profile, so that the bandwidth usage of the service can be effectively tracked by GRNN. Experimental results show that the SoC provides self-aware QoS management with low computation costs for applications over virtual LAN. Full article
(This article belongs to the Special Issue Smart Embedded Systems: A Self-Aware System-on-Chip (SoC) and Applications)
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20 pages, 4133 KiB  
Article
Optimal Method for Test and Repair Memories Using Redundancy Mechanism for SoC
by Suleman Alnatheer and Mohammed Altaf Ahmed
Micromachines 2021, 12(7), 811; https://doi.org/10.3390/mi12070811 - 10 Jul 2021
Cited by 6 | Viewed by 3386
Abstract
The current system-on-chip (SoC)-based devices uses embedded memories of enormous size. Most of these systems’ area is dense with memories and promotes different types of faults appearance in memory. The memory faults become a severe issue when they affect the yield of the [...] Read more.
The current system-on-chip (SoC)-based devices uses embedded memories of enormous size. Most of these systems’ area is dense with memories and promotes different types of faults appearance in memory. The memory faults become a severe issue when they affect the yield of the product. A memory-test and -repair scheme is an attractive solution to tackle this kind of problem. The built-in self-repair (BISR) scheme is a prominent method to handle this issue. The BISR scheme is widely used to repair the defective memories for an SoC-based system. It uses a built-in redundancy analysis (BIRA) circuit to allocate the redundancy when defects appear in the memory. The data are accessed from the redundancy allocation when the faulty memory is operative. Thus, this BIRA scheme affects the area overhead for the BISR circuit when it integrates to the SoC. The spare row and spare column–based BISR method is proposed to receive the optimal repair rate with a low area overhead. It tests the memories for almost all the fault types and repairs the memory by using spare rows and columns. The proposed BISR block’s performance was measured for the optimal repair rate and the area overhead. The area overhead, timing, and repair rate were compared with the other approaches. Furthermore, the study noticed that the repair rate and area overhead would increase by increasing the spare-row/column allocation. Full article
(This article belongs to the Special Issue Smart Embedded Systems: A Self-Aware System-on-Chip (SoC) and Applications)
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