Editorial

2 pages, 161 KiB

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Editorial for the Special Issue on the Progress of Emerging Hardware Development for Post-Moore’s Computing

by Yao-Feng Chang

Micromachines 2023, 14(1), 193; https://doi.org/10.3390/mi14010193 - 12 Jan 2023

Viewed by 632

The potential of machine learning and novel computing architecture can be exploited in the immediate future if more efficient hardware is developed that meets the special requirements of bio-inspired computing or unconventional computing schemes [...] Full article

(This article belongs to the Special Issue Progress of Emerging Hardware Development for Post-Moore’s Computing)

Research

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17 pages, 7476 KiB

Open AccessArticle

Exploiting Pull-In/Pull-Out Hysteresis in Electrostatic MEMS Sensor Networks to Realize a Novel Sensing Continuous-Time Recurrent Neural Network

by Mohammad H Hasan, Amin Abbasalipour, Hamed Nikfarjam, Siavash Pourkamali, Muhammad Emad-Ud-Din, Roozbeh Jafari and Fadi Alsaleem

Micromachines 2021, 12(3), 268; https://doi.org/10.3390/mi12030268 - 05 Mar 2021

Cited by 13 | Viewed by 2701

Abstract

The goal of this paper is to provide a novel computing approach that can be used to reduce the power consumption, size, and cost of wearable electronics. To achieve this goal, the use of microelectromechanical systems (MEMS) sensors for simultaneous sensing and computing [...] Read more.

The goal of this paper is to provide a novel computing approach that can be used to reduce the power consumption, size, and cost of wearable electronics. To achieve this goal, the use of microelectromechanical systems (MEMS) sensors for simultaneous sensing and computing is introduced. Specifically, by enabling sensing and computing locally at the MEMS sensor node and utilizing the usually unwanted pull in/out hysteresis, we may eliminate the need for cloud computing and reduce the use of analog-to-digital converters, sampling circuits, and digital processors. As a proof of concept, we show that a simulation model of a network of three commercially available MEMS accelerometers can classify a train of square and triangular acceleration signals inherently using pull-in and release hysteresis. Furthermore, we develop and fabricate a network with finger arrays of parallel plate actuators to facilitate coupling between MEMS devices in the network using actuating assemblies and biasing assemblies, thus bypassing the previously reported coupling challenge in MEMS neural networks. Full article

(This article belongs to the Special Issue Progress of Emerging Hardware Development for Post-Moore’s Computing)

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10 pages, 3578 KiB

Open AccessFeature PaperEditor’s ChoiceArticle

Post-Moore Memory Technology: Sneak Path Current (SPC) Phenomena on RRAM Crossbar Array and Solutions

by Ying-Chen Chen, Chao-Cheng Lin and Yao-Feng Chang

Micromachines 2021, 12(1), 50; https://doi.org/10.3390/mi12010050 - 03 Jan 2021

Cited by 26 | Viewed by 5114

Abstract

The sneak path current (SPC) is the inevitable issue in crossbar memory array while implementing high-density storage configuration. The crosstalks are attracting much attention, and the read accuracy in the crossbar architecture is deteriorated by the SPC. In this work, the sneak path [...] Read more.

The sneak path current (SPC) is the inevitable issue in crossbar memory array while implementing high-density storage configuration. The crosstalks are attracting much attention, and the read accuracy in the crossbar architecture is deteriorated by the SPC. In this work, the sneak path current problem is observed and investigated by the electrical experimental measurements in the crossbar array structure with the half-read scheme. The read margin of the selected cell is improved by the bilayer stacked structure, and the sneak path current is reduced ~20% in the bilayer structure. The voltage-read stress-induced read margin degradation has also been investigated, and less voltage stress degradation is showed in bilayer structure due to the intrinsic nonlinearity. The oxide-based bilayer stacked resistive random access memory (RRAM) is presented to offer immunity toward sneak path currents in high-density memory integrations when implementing the future high-density storage and in-memory computing applications. Full article

(This article belongs to the Special Issue Progress of Emerging Hardware Development for Post-Moore’s Computing)

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18 pages, 5427 KiB

Open AccessArticle

A New Embedded Key–Value Store for NVM Device Simulator

by Tao Cai, Qingjian He, Dejiao Niu, Fuli Chen, Jie Wang and Lei Li

Micromachines 2020, 11(12), 1075; https://doi.org/10.3390/mi11121075 - 02 Dec 2020

Cited by 1 | Viewed by 1828

Abstract

The non-volatile memory (NVM) device is a useful way to solve the memory wall in computers. However, the current I/O software stack in operating systems becomes a performance bottleneck for applications based on NVM devices, especially for key–value stores. We analyzed the characteristics [...] Read more.

The non-volatile memory (NVM) device is a useful way to solve the memory wall in computers. However, the current I/O software stack in operating systems becomes a performance bottleneck for applications based on NVM devices, especially for key–value stores. We analyzed the characteristics of key–value stores and NVM devices and designed a new embedded key–value store for an NVM device simulator named PMEKV. The embedded processor in NVM devices was used to manage key–value pairs to reduce the data transfer between NVM devices and key–value applications. Meanwhile, it also cut down the data copy between the user space and the kernel space in the operating system to alleviate the I/O software stacks on the efficiency of key–value stores. The architecture, data layout, management strategy, new interface and log strategy of PMEKV are given. Finally, a prototype of PMEKV was implemented based on PMEM. We used YCSB to test and compare it with Redis, MongDB, and Memcache. Meanwhile, the Redis for PMEM named PMEM-Redis and PMEM-KV were also used to test and compared with PMEKV. The results show that PMEKV had the advantage of throughput and adaptability compared with the current key–value stores. Full article

(This article belongs to the Special Issue Progress of Emerging Hardware Development for Post-Moore’s Computing)

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10 pages, 1727 KiB

Open AccessArticle

Improved Stability and Controllability in ZrN-Based Resistive Memory Device by Inserting TiO₂ Layer

by Junhyeok Choi and Sungjun Kim

Micromachines 2020, 11(10), 905; https://doi.org/10.3390/mi11100905 - 29 Sep 2020

Cited by 9 | Viewed by 2084

Abstract

In this work, the enhanced resistive switching of ZrN-based resistive switching memory is demonstrated by embedding TiO₂ layer between Ag top electrode and ZrN switching layer. The Ag/ZrN/n-Si device exhibits unstable resistive switching as a result of the uncontrollable Ag migration. Both [...] Read more.

In this work, the enhanced resistive switching of ZrN-based resistive switching memory is demonstrated by embedding TiO₂ layer between Ag top electrode and ZrN switching layer. The Ag/ZrN/n-Si device exhibits unstable resistive switching as a result of the uncontrollable Ag migration. Both unipolar and bipolar resistive switching with high RESET current were observed. Negative-SET behavior in the Ag/ZrN/n-Si device makes set-stuck, causing permanent resistive switching failure. On the other hand, the analogue switching in the Ag/TiO₂/ZrN/n-Si device, which could be adopted for the multi-bit data storage applications, is obtained. The gradual switching in Ag/TiO₂/ZrN/n-Si device is achieved, possibly due to the suppressed Ag diffusion caused by TiO₂ inserting layer. The current–voltage (I–V) switching characteristics of Ag/ZrN/n-Si and Ag/TiO₂/ZrN/n-Si devices can be well verified by pulse transient. Finally, we established that the Ag/TiO₂/ZrN/n-Si device is suitable for neuromorphic application through a comparison study of conductance update. This paper paves the way for neuromorphic application in nitride-based memristor devices. Full article

(This article belongs to the Special Issue Progress of Emerging Hardware Development for Post-Moore’s Computing)

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13 pages, 1470 KiB

Open AccessArticle

Efficient Acceleration of Stencil Applications through In-Memory Computing

by Hasan Erdem Yantır, Ahmed M. Eltawil and Khaled N. Salama

Micromachines 2020, 11(6), 622; https://doi.org/10.3390/mi11060622 - 26 Jun 2020

Cited by 7 | Viewed by 3042

Abstract

The traditional computer architectures severely suffer from the bottleneck between the processing elements and memory that is the biggest barrier in front of their scalability. Nevertheless, the amount of data that applications need to process is increasing rapidly, especially after the era of [...] Read more.

The traditional computer architectures severely suffer from the bottleneck between the processing elements and memory that is the biggest barrier in front of their scalability. Nevertheless, the amount of data that applications need to process is increasing rapidly, especially after the era of big data and artificial intelligence. This fact forces new constraints in computer architecture design towards more data-centric principles. Therefore, new paradigms such as in-memory and near-memory processors have begun to emerge to counteract the memory bottleneck by bringing memory closer to computation or integrating them. Associative processors are a promising candidate for in-memory computation, which combines the processor and memory in the same location to alleviate the memory bottleneck. One of the applications that need iterative processing of a huge amount of data is stencil codes. Considering this feature, associative processors can provide a paramount advantage for stencil codes. For demonstration, two in-memory associative processor architectures for 2D stencil codes are proposed, implemented by both emerging memristor and traditional SRAM technologies. The proposed architecture achieves a promising efficiency for a variety of stencil applications and thus proves its applicability for scientific stencil computing. Full article

(This article belongs to the Special Issue Progress of Emerging Hardware Development for Post-Moore’s Computing)

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28 pages, 3698 KiB

Open AccessArticle

STT-DPSA: Digital PUF-Based Secure Authentication Using STT-MRAM for the Internet of Things

by Wei-Chen Chien, Yu-Chian Chang, Yao-Tung Tsou, Sy-Yen Kuo and Ching-Ray Chang

Micromachines 2020, 11(5), 502; https://doi.org/10.3390/mi11050502 - 15 May 2020

Cited by 7 | Viewed by 2443

Abstract

Physical unclonable function (PUF), a hardware-efficient approach, has drawn a lot of attention in the security research community for exploiting the inevitable manufacturing variability of integrated circuits (IC) as the unique fingerprint of each IC. However, analog PUF is not robust and resistant [...] Read more.

Physical unclonable function (PUF), a hardware-efficient approach, has drawn a lot of attention in the security research community for exploiting the inevitable manufacturing variability of integrated circuits (IC) as the unique fingerprint of each IC. However, analog PUF is not robust and resistant to environmental conditions. In this paper, we propose a digital PUF-based secure authentication model using the emergent spin-transfer torque magnetic random-access memory (STT-MRAM) PUF (called STT-DPSA for short). STT-DPSA is an original secure identity authentication architecture for Internet of Things (IoT) devices to devise a computationally lightweight authentication architecture which is not susceptible to environmental conditions. Considering hardware security level or cell area, we alternatively build matrix multiplication or stochastic logic operation for our authentication model. To prove the feasibility of our model, the reliability of our PUF is validated via the working windows between temperature interval (−35

^{\circ}

C, 110

^{\circ}

C) and Vdd interval [0.95 V, 1.16 V] and STT-DPSA is implemented with parameters n = 32, i = o = 1024, k = 8, and l = 2 using FPGA design flow. Under this setting of parameters, an attacker needs to take time complexity O(

2^{256}

) to compromise STT-DPSA. We also evaluate STT-DPSA using Synopsys design compiler with TSMC 0.18 um process. Full article

(This article belongs to the Special Issue Progress of Emerging Hardware Development for Post-Moore’s Computing)

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13 pages, 759 KiB

Open AccessArticle

Binary Addition in Resistance Switching Memory Array by Sensing Majority

by John Reuben

Micromachines 2020, 11(5), 496; https://doi.org/10.3390/mi11050496 - 14 May 2020

Cited by 18 | Viewed by 3891

Abstract

The flow of data between processing and memory units in contemporary computing systems is their main performance and energy-efficiency bottleneck, often referred to as the ‘von Neumann bottleneck’ or ‘memory wall’. Emerging resistance switching memories (memristors) show promising signs to overcome the ‘memory [...] Read more.

The flow of data between processing and memory units in contemporary computing systems is their main performance and energy-efficiency bottleneck, often referred to as the ‘von Neumann bottleneck’ or ‘memory wall’. Emerging resistance switching memories (memristors) show promising signs to overcome the ‘memory wall’ by enabling computation in the memory array. Majority logic is a type of Boolean logic, and in many nanotechnologies, it has been found to be an efficient logic primitive. In this paper, a technique is proposed to implement a majority gate in a memory array. The majority gate is realised in an energy-efficient manner as a memory

R E A D

operation. The proposed logic family disintegrates arithmetic operations to majority and NOT operations which are implemented as memory

R E A D

and

W R I T E

operations. A 1-bit full adder can be implemented in 6 steps (memory cycles) in a 1T–1R array, which is faster than

I M P L Y

,

N A N D

,

N O R

and other similar logic primitives. Full article

(This article belongs to the Special Issue Progress of Emerging Hardware Development for Post-Moore’s Computing)

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10 pages, 2524 KiB

Open AccessArticle

Improving the Recognition Accuracy of Memristive Neural Networks via Homogenized Analog Type Conductance Quantization

by Qilai Chen, Tingting Han, Minghua Tang, Zhang Zhang, Xuejun Zheng and Gang Liu

Micromachines 2020, 11(4), 427; https://doi.org/10.3390/mi11040427 - 18 Apr 2020

Cited by 9 | Viewed by 2747

Abstract

Conductance quantization (QC) phenomena occurring in metal oxide based memristors demonstrate great potential for high-density data storage through multilevel switching, and analog synaptic weight update for effective training of the artificial neural networks. Continuous, linear and symmetrical modulation of the device conductance is [...] Read more.

Conductance quantization (QC) phenomena occurring in metal oxide based memristors demonstrate great potential for high-density data storage through multilevel switching, and analog synaptic weight update for effective training of the artificial neural networks. Continuous, linear and symmetrical modulation of the device conductance is a critical issue in QC behavior of memristors. In this contribution, we employ the scanning probe microscope (SPM) assisted electrode engineering strategy to control the ion migration process to construct single conductive filaments in Pt/HfO_x/Pt devices. Upon deliberate tuning and evolution of the filament, 32 half integer quantized conductance states in the 16 G₀ to 0.5 G₀ range with enhanced distribution uniformity was achieved. Simulation results revealed that the numbers of the available QC states and fluctuation of the conductance at each state play an important role in determining the overall performance of the neural networks. The 32-state QC behavior of the hafnium oxide device shows improved recognition accuracy approaching 90% for handwritten digits, based on analog type operation of the multilayer perception (MLP) neural network. Full article

(This article belongs to the Special Issue Progress of Emerging Hardware Development for Post-Moore’s Computing)

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12 pages, 5250 KiB

Open AccessArticle

A Low-Profile and High-isolated MIMO Antenna for 5G Mobile Terminal

by Rongqiang Li, Zixu Mo, Haoran Sun, Xiaofeng Sun and Guohong Du

Micromachines 2020, 11(4), 360; https://doi.org/10.3390/mi11040360 - 30 Mar 2020

Cited by 37 | Viewed by 4522

Abstract

An eight-element multiple-input multiple-output (MIMO) frame antenna array in the 3.5 GHz band (3400–3600 MHz) for 5G mobile terminal systems was presented. By using the adjacent grounding and electromagnetic coupling feeding technology, the loop antenna element could generate two resonant frequencies, thus effectively [...] Read more.

An eight-element multiple-input multiple-output (MIMO) frame antenna array in the 3.5 GHz band (3400–3600 MHz) for 5G mobile terminal systems was presented. By using the adjacent grounding and electromagnetic coupling feeding technology, the loop antenna element could generate two resonant frequencies, thus effectively expanding its bandwidth. By adopting double-sided parallel strip line (DSPSL) technology, the electromagnetic coupling inside the loop antenna could be adjusted, and the size of the loop antenna could be effectively reduced so that the MIMO antenna array could obtain a low-profile structure. The total size of the MIMO array was 150 mm × 75 mm × 5.3 mm. Without additional isolation measures, the measured −6 dB impedance bandwidth (BW) was 3400–3660 MHz, and the minimum isolation between antenna elements was better than −20 dB. The proposed antenna was expected to be applied to 5G mobile terminals based on its low-profile, high-isolated characteristics, and good MIMO performance. Full article

(This article belongs to the Special Issue Progress of Emerging Hardware Development for Post-Moore’s Computing)

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