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Micromachines
Special Issues
Recent Advances in Emerging Transistor Technologies and Their Applications
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Recent Advances in Emerging Transistor Technologies and Their Applications

A special issue of Micromachines (ISSN 2072-666X). This special issue belongs to the section "E：Engineering and Technology".

Deadline for manuscript submissions: 31 October 2024 | Viewed by 6844

Special Issue Editors

Dr. Fawnizu Azmadi Hussin

E-Mail Website
Guest Editor
Department of Electrical and Electronics Engineering, Universiti Teknologi PETRONAS, Seri Iskandar 32610, Malaysia
Interests: novel semiconductor materials and devices; integrated circuit design; flexible electronics
Dr. Furqan Zahoor

E-Mail Website
Guest Editor
School of Computer Science and Engineering, Nanyang Technological University, Singapore 639798, Singapore
Interests: digital and analog circuits; logic design; carbon nanotube field-effect transistors (CNTFETs)
Dr. Haider Abbas

E-Mail Website
Guest Editor
School of Electrical and Electronic Engineering, Nanyang Technological University (NTU), Singapore 639798, Singapore
Interests: neuromorphic computing; emerging nanotechnology devices; electronic synapse
Special Issues, Collections and Topics in MDPI journals
Dr. Faisal Bashir

E-Mail Website
Guest Editor
Department of Electronics & Instrumentation Technology, University of Kashmir, Kashmir 190006, India
Interests: nanowire transistors; nanoscale devices; MOSFET circuits; neural networks

Special Issue Information

Dear Colleagues,

The evolution and growth of transistors over the years have transformed the manner in which humans think and interact with modern electronic devices, which have rapidly increased their footprint in all sectors from industry to healthcare, security, smart electronic devices and beyond. The domain of electronics has witnessed rapid growth, which is primarily attributed to the conventional semiconductor technologies, but in the last few decades, the emergence of a variety of novel materials has led to renewed interest in testing the performance of various devices for a wide range of applications.

With the domain of electronics progressing at a rapid rate, research in the domain of transistor technologies becomes more critical and has expanded to include novel materials, device concepts, and integrated systems that offer enhanced functionality and performance. This Special Issue aims to highlight the key recent developments in the broader domain of emerging transistor technologies, with a focus on their fundamental properties, working mechanisms, device fabrication, performance metrics and applications such as neuromorphic computing, ternary logic design, hardware security, etc. Original research papers and review articles are welcome.

The topics of interest of this Special issue include, but are not limited to, the following:

  • Energy-efficient computing designs based on emerging transistor technologies.
  • Design of electronic synapses and neurons for neuromorphic computing.
  • Memories that utilize emerging transistors as design elements.
  • Emerging transistor technology-based hardware security applications.

Dr. Fawnizu Azmadi Hussin
Dr. Furqan Zahoor
Dr. Haider Abbas
Dr. Faisal Bashir
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Micromachines is an international peer-reviewed open access monthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2600 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • novel semiconductor materials
  • CNTFETs
  • neuromorphic computing
  • nanoscale devices
  • MOSFET circuits
  • logic design

Published Papers (4 papers)

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Research

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14 pages, 10318 KiB  
Article
Leakage and Thermal Reliability Optimization of Stacked Nanosheet Field-Effect Transistors with SiC Layers
by Cong Li, Yali Shao, Fengyu Kuang, Fang Liu, Yunqi Wang, Xiaoming Li and Yiqi Zhuang
Micromachines 2024, 15(4), 424; https://doi.org/10.3390/mi15040424 - 22 Mar 2024
Viewed by 750
Abstract
In this work, we propose a SiC-NSFET structure that uses a PTS scheme only under the gate, with SiC layers under the source and drain, to improve the leakage current and thermal reliability. Punch-through stopper (PTS) doping is widely used to suppress the [...] Read more.
In this work, we propose a SiC-NSFET structure that uses a PTS scheme only under the gate, with SiC layers under the source and drain, to improve the leakage current and thermal reliability. Punch-through stopper (PTS) doping is widely used to suppress the leakage current, but aggressively high PTS doping will cause additional band-to-band (BTBT) current. Therefore, the bottom oxide isolation nanosheet field-effect transistor (BOX-NSFET) can further reduce the leakage current and become an alternative to conventional structures with PTS. However, thermal reliability issues, like bias temperature instability (BTI), hot carrier injection (HCI), and time-dependent dielectric breakdown (TDDB), induced by the self-heating effect (SHE) of BOX-NSFET, become more profound due to the lower thermal conductivity of SiO2 than silicon. Moreover, the bottom oxide will reduce the stress along the channel due to the challenges associated with growing high-quality SiGe material on SiO2. Therefore, this method faces difficulties in enhancing the mobility of p-type devices. The comprehensive TCAD simulation results show that SiC-NSFET significantly suppresses the substrate leakage current compared to the conventional structure with PTS. In addition, compared to the BOX-NSFET, the stress reduction caused by the bottom oxide is avoided, and the SHE is mitigated. This work provides significant design guidelines for leakage and thermal reliability optimization of next-generation advanced nodes. Full article
(This article belongs to the Special Issue Recent Advances in Emerging Transistor Technologies and Their Applications)
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18 pages, 14420 KiB  
Article
Phase Behavior and Role of Organic Additives for Self-Doped CsPbI3 Perovskite Semiconductor Thin Films
by Tamiru Kebede, Mulualem Abebe, Dhakshnamoorthy Mani, Jibin Keloth Paduvilan, Lishin Thottathi, Aparna Thankappan, Sabu Thomas, Sarfaraz Kamangar, Abdul Saddique Shaik, Irfan Anjum Badruddin, Fekadu Gochole Aga and Jung Yong Kim
Micromachines 2023, 14(8), 1601; https://doi.org/10.3390/mi14081601 - 14 Aug 2023
Cited by 1 | Viewed by 1124
Abstract
The phase change of all-inorganic cesium lead halide (CsPbI3) thin film from yellow δ-phase to black γ-/α-phase has been a topic of interest in the perovskite optoelectronics field. Here, the main focus is how to secure a black perovskite phase by [...] Read more.
The phase change of all-inorganic cesium lead halide (CsPbI3) thin film from yellow δ-phase to black γ-/α-phase has been a topic of interest in the perovskite optoelectronics field. Here, the main focus is how to secure a black perovskite phase by avoiding a yellow one. In this work, we fabricated a self-doped CsPbI3 thin film by incorporating an excess cesium iodide (CsI) into the perovskite precursor solution. Then, we studied the effect of organic additive such as 1,8-diiodooctane (DIO), 1-chloronaphthalene (CN), and 1,8-octanedithiol (ODT) on the optical, structural, and morphological properties. Specifically, for elucidating the binary additive–solvent solution thermodynamics, we employed the Flory–Huggins theory based on the oligomer level of additives’ molar mass. Resultantly, we found that the miscibility of additive–solvent displaying an upper critical solution temperature (UCST) behavior is in the sequence CN:DMF > ODT:DMF > DIO:DMF, the trends of which could be similarly applied to DMSO. Finally, the self-doping strategy with additive engineering should help fabricate a black γ-phase perovskite although the mixed phases of δ-CsPbI3, γ-CsPbI3, and Cs4PbI6 were observed under ambient conditions. However, the results may provide insight for the stability of metastable γ-phase CsPbI3 at room temperature. Full article
(This article belongs to the Special Issue Recent Advances in Emerging Transistor Technologies and Their Applications)
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19 pages, 8234 KiB  
Article
Ternary Full Adder Designs Employing Unary Operators and Ternary Multiplexers
by Ramzi A. Jaber, Ali M. Haidar, Abdallah Kassem and Furqan Zahoor
Micromachines 2023, 14(5), 1064; https://doi.org/10.3390/mi14051064 - 17 May 2023
Cited by 3 | Viewed by 2415
Abstract
The design of the Ternary Full Adders (TFA) employing Carbon Nanotube Field-Effect Transistors (CNFET) has been widely presented in the literature. To obtain the optimal design of these ternary adders, we propose two new different designs, TFA1 with 59 CNFETs and TFA2 with [...] Read more.
The design of the Ternary Full Adders (TFA) employing Carbon Nanotube Field-Effect Transistors (CNFET) has been widely presented in the literature. To obtain the optimal design of these ternary adders, we propose two new different designs, TFA1 with 59 CNFETs and TFA2 with 55 CNFETs, that use unary operator gates with two voltage supplies (Vdd and Vdd/2) to reduce the transistor count and energy consumption. In addition, this paper proposes two 4-trit Ripple Carry Adders (RCA) based on the two proposed TFA1 and TFA2; we use the HSPICE simulator and 32 nm CNFET to simulate the proposed circuits under different voltages, temperatures, and output loads. The simulation results show the improvements of the designs in a reduction of over 41% in energy consumption (PDP), and over 64% in Energy Delay Product (EDP) compared to the best recent works in the literature. Full article
(This article belongs to the Special Issue Recent Advances in Emerging Transistor Technologies and Their Applications)
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Review

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16 pages, 5289 KiB  
Review
Review on Main Gate Characteristics of P-Type GaN Gate High-Electron-Mobility Transistors
by Zhongxu Wang, Jiao Nan, Zhiwen Tian, Pei Liu, Yinhe Wu and Jincheng Zhang
Micromachines 2024, 15(1), 80; https://doi.org/10.3390/mi15010080 - 30 Dec 2023
Viewed by 1380
Abstract
As wide bandgap semiconductors, gallium nitride (GaN) lateral high-electron-mobility transistors (HEMTs) possess high breakdown voltage, low resistance and high frequency performance. PGaN gate HEMTs are promising candidates for high-voltage, high-power applications due to the normally off operation and robust gate reliability. However, the [...] Read more.
As wide bandgap semiconductors, gallium nitride (GaN) lateral high-electron-mobility transistors (HEMTs) possess high breakdown voltage, low resistance and high frequency performance. PGaN gate HEMTs are promising candidates for high-voltage, high-power applications due to the normally off operation and robust gate reliability. However, the threshold and gate-breakdown voltages are relatively low compared with Si-based and SiC-based power MOSFETs. The epitaxial layers and device structures were optimized to enhance the main characteristics of pGaN HEMTs. In this work, various methods to improve threshold and gate-breakdown voltages are presented, such as the top-layer optimization of the pGaN cap, hole-concentration enhancement, the low-work-function gate electrode, and the MIS-type pGaN gate. The discussion of the main gate characteristic enhancement of p-type GaN gate HEMTs would accelerate the development of GaN power electronics to some extent. Full article
(This article belongs to the Special Issue Recent Advances in Emerging Transistor Technologies and Their Applications)
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