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Silicon Carbide: Material Growth, Device Processing and Applications

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A special issue of Materials (ISSN 1996-1944). This special issue belongs to the section "Electronic Materials".

Deadline for manuscript submissions: closed (20 April 2024) | Viewed by 16396

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Special Issue Editors

Dr. Marilena Vivona

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Guest Editor

Institute for Microelectronics and Microsystems, National Research Council of Italy, 95121 Catania, Italy
Interests: 4H-SiC; schottky diodes; ohmic contacts; current transport; metal/SiC interfaces

Prof. Dr. Mike Jennings

E-Mail Website
Guest Editor

Electronic and Electrical Engineering, Swansea University, Swansea SA2 8PP, UK
Interests: silicon carbide; gallium nitride; silicon power electronics
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

Dear Colleagues,

Owing to its superior performance and higher energy efficiency with respect to silicon, silicon carbide (SiC) plays a pivotal role in modern power electronics, where it can be used in energy conversion systems, electric vehicles, transportation, etc.

Although commercial SiC (the 4H-SiC polytype) material quality and device technology are already mature and a large variety of devices are already on the market, considerable efforts are still being dedicated to further improving device performance across several application areas. For this purpose, a deeper understanding of the material properties, processing issues and device physics is required, which can also pave the way for the applications in other fields, such as quantum technologies, sensing and detecting.

This Special Issue is aimed at collecting papers on silicon carbide, covering relevant aspects from material growth through to device processing and applications.

The topics covered by the Special Issue include, but are not limited to:

Bulk and epitaxial growth of SiC materials;
Material characterization;
Surfaces and interfaces in SiC devices;
Fabrication processing (contacts, implantation doping, gate oxides, etc.);
Power devices (Schottky Diodes, JBS, MOSFETs, BJT, etc.);
Modelling and reliability;
System applications (electric vehicles, railway, avionic, energy conversion, sensors, detectors, etc.);
Radiation hardness of 4H-SiC devices.

Both concise reviews and original articles on new findings are welcome.

Dr. Marilena Vivona
Dr. Mike Jennings
Guest Editors

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Keywords

silicon carbide
homoepitaxial and heteroepitaxial growth
device processing
power- and high-frequency electronics
schottky diodes and MOSFETs
optoelectronics
sensors
detectors
metal/semiconductor interfaces

Published Papers (10 papers)

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Research

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12 pages, 4150 KiB

Open AccessArticle

4H-SiC MOSFET Threshold Voltage Instability Evaluated via Pulsed High-Temperature Reverse Bias and Negative Gate Bias Stresses

by Laura Anoldo, Edoardo Zanetti, Walter Coco, Alfio Russo, Patrick Fiorenza and Fabrizio Roccaforte

Materials 2024, 17(8), 1908; https://doi.org/10.3390/ma17081908 - 20 Apr 2024

Viewed by 313

Abstract

This paper presents a reliability study of a conventional 650 V SiC planar MOSFET subjected to pulsed HTRB (High-Temperature Reverse Bias) stress and negative HTGB (High-Temperature Gate Bias) stress defined by a TCAD static simulation showing the electric field distribution across the SiC/SiO₂ interface. The instability of several electrical parameters was monitored and their drift analyses were investigated. Moreover, the shift of the onset of the Fowler–Nordheim gate injection current under stress conditions provided a reliable method to quantify the trapped charge inside the gate oxide bulk, and it allowed us to determine the real stress conditions. Moreover, it has been demonstrated from the cross-correlation, the TCAD simulation, and the experimental ΔV_th and ΔV_FN variation that HTGB stress is more severe compared to HTRB. In fact, HTGB showed a 15% variation in both ΔV_th and ΔV_FN, while HTRB showed only a 4% variation in both ΔV_th and ΔV_FN. The physical explanation was attributed to the accelerated degradation of the gate insulator in proximity to the source region under HTGB configuration. Full article

(This article belongs to the Special Issue Silicon Carbide: Material Growth, Device Processing and Applications)

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15 pages, 6758 KiB

Open AccessArticle

Modeling of Charge-to-Breakdown with an Electron Trapping Model for Analysis of Thermal Gate Oxide Failure Mechanism in SiC Power MOSFETs

by Jiashu Qian, Limeng Shi, Michael Jin, Monikuntala Bhattacharya, Atsushi Shimbori, Hengyu Yu, Shiva Houshmand, Marvin H. White and Anant K. Agarwal

Materials 2024, 17(7), 1455; https://doi.org/10.3390/ma17071455 - 22 Mar 2024

Viewed by 592

Abstract

The failure mechanism of thermal gate oxide in silicon carbide (SiC) power metal oxide semiconductor field effect transistors (MOSFETs), whether it is field-driven breakdown or charge-driven breakdown, has always been a controversial topic. Previous studies have demonstrated that the failure time of thermally grown silicon dioxide (SiO₂) on SiC stressed with a constant voltage is indicated as charge driven rather than field driven through the observation of Weibull Slope β. Considering the importance of the accurate failure mechanism for the thermal gate oxide lifetime prediction model of time-dependent dielectric breakdown (TDDB), charge-driven breakdown needs to be further fundamentally justified. In this work, the charge-to-breakdown (

Q_{B D}

) of the thermal gate oxide in a type of commercial planar SiC power MOSFETs, under the constant current stress (CCS), constant voltage stress (CVS), and pulsed voltage stress (PVS) are extracted, respectively. A mathematical electron trapping model in thermal SiO₂ grown on single crystal silicon (Si) under CCS, which was proposed by M. Liang et al., is proven to work equally well with thermal SiO₂ grown on SiC and used to deduce the

Q_{B D}

model of the device under test (DUT). Compared with the

Q_{B D}

obtained under the three stress conditions, the charge-driven breakdown mechanism is validated in the thermal gate oxide of SiC power MOSFETs. Full article

(This article belongs to the Special Issue Silicon Carbide: Material Growth, Device Processing and Applications)

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14 pages, 6160 KiB

Open AccessArticle

Characteristics of the Discoloration Switching Phenomenon of 4H-SiC Single Crystals Grown by PVT Method Using ToF-SIMS and Micro-Raman Analysis

by Seul-Ki Kim, Hajun Kim, Hyun Sik Kim, Tae Eun Hong, Younki Lee and Eun Young Jung

Materials 2024, 17(5), 1005; https://doi.org/10.3390/ma17051005 - 22 Feb 2024

Viewed by 504

Abstract

The discoloration switching appearing in the initial and final growth stages of 4H-silicon carbide (4H-SiC) single crystals grown using the physical vapor transport (PVT) technique was investigated. This phenomenon was studied, investigating the correlation with linear-type micro-pipe defects on the surface of 4H-SiC single crystals. Based on the experimental results obtained using time-of-flight secondary ion mass spectrometry (ToF-SIMS) and micro-Raman analysis, it was deduced that the orientation of the 4H-SiC c-axis causes an axial change that correlates with low levels of carbon. In addition, it was confirmed that the incorporation of additional elements and the concentrations of these doped impurity elements were the main causes of discoloration and changes in growth orientation. Overall, this work provides guidelines for evaluating the discoloration switching in 4H-SiC single crystals and contributes to a greater understanding of this phenomenon. Full article

(This article belongs to the Special Issue Silicon Carbide: Material Growth, Device Processing and Applications)

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13 pages, 2323 KiB

Open AccessArticle

Thorough Wide-Temperature-Range Analysis of Pt/SiC and Cr/SiC Schottky Contact Non-Uniformity

by Razvan Pascu, Gheorghe Pristavu, Dan-Theodor Oneata, Gheorghe Brezeanu, Cosmin Romanitan, Nikolay Djourelov, Andrei Enache, Florin Draghici, Andrei Mario Ivan and Emilian Ceuca

Materials 2024, 17(2), 400; https://doi.org/10.3390/ma17020400 - 13 Jan 2024

Viewed by 554

Abstract

This paper evaluates the non-uniformity degree of platinum and chromium Schottky contacts on silicon carbide. The forward characteristics of experimental samples were acquired in a wide, 60–500 K, temperature range. Microstructural and conventional electrical characterizations were performed, revealing the presence of inhomogeneities on the contact surface. The main parameters were extracted using inhomogeneity models of varying complexity levels. Their relevance is discussed with respect to the models’ applicable, limited, temperature ranges. Finally, complete forward curve fitting was achieved using p-diode modeling, evincing that each type of contact behaves as four parallel-connected ideal diodes. Since these parallel diodes have varying influences on the overall device current with temperature and bias, operable domains can be identified where the samples behave suitably. Full article

(This article belongs to the Special Issue Silicon Carbide: Material Growth, Device Processing and Applications)

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10 pages, 2282 KiB

Open AccessEditor’s ChoiceArticle

Al₂O₃ Layers Grown by Atomic Layer Deposition as Gate Insulator in 3C-SiC MOS Devices

by Emanuela Schilirò, Patrick Fiorenza, Raffaella Lo Nigro, Bruno Galizia, Giuseppe Greco, Salvatore Di Franco, Corrado Bongiorno, Francesco La Via, Filippo Giannazzo and Fabrizio Roccaforte

Materials 2023, 16(16), 5638; https://doi.org/10.3390/ma16165638 - 15 Aug 2023

Cited by 2 | Viewed by 1117

Abstract

Metal-oxide-semiconductor (MOS) capacitors with Al₂O₃ as a gate insulator are fabricated on cubic silicon carbide (3C-SiC). Al₂O₃ is deposited both by thermal and plasma-enhanced Atomic Layer Deposition (ALD) on a thermally grown 5 nm SiO₂ interlayer to improve the ALD nucleation and guarantee a better band offset with the SiC. The deposited Al₂O₃/SiO₂ stacks show lower negative shifts of the flat band voltage V_FB (in the range of about −3 V) compared with the conventional single SiO₂ layer (in the range of −9 V). This lower negative shift is due to the combined effect of the Al₂O₃ higher permittivity (ε = 8) and to the reduced amount of carbon defects generated during the short thermal oxidation process for the thin SiO₂. Moreover, the comparison between thermal and plasma-enhanced ALD suggests that this latter approach produces Al₂O₃ layers possessing better insulating behavior in terms of distribution of the leakage current breakdown. In fact, despite both possessing a breakdown voltage of 26 V, the T-ALD Al₂O₃ sample is characterised by a higher current density starting from 15 V. This can be attributable to the slightly inferior quality (in terms of density and defects) of Al₂O₃ obtained by the thermal approach and, which also explains its non-uniform dC/dV distribution arising by SCM maps. Full article

(This article belongs to the Special Issue Silicon Carbide: Material Growth, Device Processing and Applications)

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15 pages, 5092 KiB

Open AccessEditor’s ChoiceArticle

SiC Doping Impact during Conducting AFM under Ambient Atmosphere

by Christina Villeneuve-Faure, Abdelhaq Boumaarouf, Vishal Shah, Peter M. Gammon, Ulrike Lüders and Rosine Coq Germanicus

Materials 2023, 16(15), 5401; https://doi.org/10.3390/ma16155401 - 01 Aug 2023

Viewed by 894

Abstract

The characterization of silicon carbide (SiC) by specific electrical atomic force microscopy (AFM) modes is highly appreciated for revealing its structure and properties at a nanoscale. However, during the conductive AFM (C-AFM) measurements, the strong electric field that builds up around and below the AFM conductive tip in ambient atmosphere may lead to a direct anodic oxidation of the SiC surface due to the formation of a water nanomeniscus. In this paper, the underlying effects of the anodization are experimentally investigated for SiC multilayers with different doping levels by studying gradual SiC epitaxial-doped layers with nitrogen (N) from 5 × 10¹⁷ to 10¹⁹ at/cm³. The presence of the water nanomeniscus is probed by the AFM and analyzed with the force–distance curve when a negative bias is applied to the AFM tip. From the water meniscus breakup distance measured without and with polarization, the water meniscus volume is increased by a factor of three under polarization. AFM experimental results are supported by electrostatic modeling to study oxide growth. By taking into account the presence of the water nanomeniscus, the surface oxide layer and the SiC doping level, a 2D-axisymmetric finite element model is developed to calculate the electric field distribution nearby the tip contact and the current distributions at the nanocontact. The results demonstrate that the anodization occurred for the conductive regime in which the current depends strongly to the doping; its threshold value is 7 × 10¹⁸ at/cm³ for anodization. Finally, the characterization of a classical planar SiC-MOSFET by C-AFM is examined. Results reveal the local oxidation mechanism of the SiC material at the surface of the MOSFET structure. AFM topographies after successive C-AFM measurements show that the local oxide created by anodization is located on both sides of the MOS channel; these areas are the locations of the highly n-type-doped zones. A selective wet chemical etching confirms that the oxide induced by local anodic oxidation is a SiOCH layer. Full article

(This article belongs to the Special Issue Silicon Carbide: Material Growth, Device Processing and Applications)

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10 pages, 2425 KiB

Open AccessEditor’s ChoiceArticle

Study of Carrier Mobilities in 4H-SiC MOSFETS Using Hall Analysis

by Suman Das, Yongju Zheng, Ayayi Ahyi, Marcelo A. Kuroda and Sarit Dhar

Materials 2022, 15(19), 6736; https://doi.org/10.3390/ma15196736 - 28 Sep 2022

Cited by 7 | Viewed by 1911

Abstract

The channel conduction in 4H-SiC metal–oxide–semiconductor field effect transistors (MOSFETs) are highly impacted by charge trapping and scattering at the interface. Even though nitridation reduces the interface trap density, scattering still plays a crucial role in increasing the channel resistance in these transistors. In this work, the dominant scattering mechanisms are distinguished for inversion layer electrons and holes using temperature and body-bias-dependent Hall measurements on nitrided lateral 4H-SiC MOSFETs. The effect of the transverse electric field (

E_{e f f}

) on carrier mobility is analyzed under strong inversion condition where surface roughness scattering becomes prevalent. Power law dependencies of the electron and hole Hall mobility for surface roughness scattering are determined to be

E_{e f f}^{- 1.8}

and

E_{e f f}^{- 2.4}

, respectively, analogous to those of silicon MOSFETs. Moreover, for n-channel MOSFETs, the effect of phonon scattering is observed at zero body bias, whereas in p-channel MOSFETs, it is observed only under negative body biases. Along with the identification of regimes governed by different scattering mechanisms, these results highlight the importance of the selection of substrate doping and of

E_{e f f}

in controlling the value of channel mobility in 4H-SiC MOSFETs. Full article

(This article belongs to the Special Issue Silicon Carbide: Material Growth, Device Processing and Applications)

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6 pages, 1865 KiB

Open AccessCommunication

A New Cell Topology for 4H-SiC Planar Power MOSFETs for High-Frequency Switching

by Shengnan Zhu, Tianshi Liu, Junchong Fan, Arash Salemi, Marvin H. White, David Sheridan and Anant K. Agarwal

Materials 2022, 15(19), 6690; https://doi.org/10.3390/ma15196690 - 27 Sep 2022

Cited by 1 | Viewed by 1611

Abstract

A new cell topology named the dodecagonal (a polygon with twelve sides, short for Dod) cell is proposed to optimize the gate-to-drain capacitance (

C_{gd}

) and reduce the specific ON-resistance (

R_{on, sp}

) of 4H-SiC planar power MOSFETs. [...] Read more.

A new cell topology named the dodecagonal (a polygon with twelve sides, short for Dod) cell is proposed to optimize the gate-to-drain capacitance (

C_{gd}

) and reduce the specific ON-resistance (

R_{on, sp}

) of 4H-SiC planar power MOSFETs. The Dod and the octagonal (Oct) cells are used in the layout design of the 650 V SiC MOSFETs in this work. The experimental results confirm that the Dod-cell MOSFET achieves a 2.2× lower

R_{on, sp}

, 2.1× smaller high-frequency figure of merit (HF-FOM), higher turn on/off dv/dt, and 29% less switching loss than the fabricated Oct-cell MOSFET. The results demonstrate that the Dod cell is an attractive candidate for high-frequency power applications. Full article

(This article belongs to the Special Issue Silicon Carbide: Material Growth, Device Processing and Applications)

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11 pages, 2437 KiB

Open AccessArticle

Effects of JFET Region Design and Gate Oxide Thickness on the Static and Dynamic Performance of 650 V SiC Planar Power MOSFETs

by Shengnan Zhu, Tianshi Liu, Junchong Fan, Hema Lata Rao Maddi, Marvin H. White and Anant K. Agarwal

Materials 2022, 15(17), 5995; https://doi.org/10.3390/ma15175995 - 30 Aug 2022

Cited by 7 | Viewed by 2571

Abstract

650 V SiC planar MOSFETs with various JFET widths, JFET doping concentrations, and gate oxide thicknesses were fabricated by a commercial SiC foundry on two six-inch SiC epitaxial wafers. An orthogonal

P^{+}

layout was used for the 650 V SiC MOSFETs to [...] Read more.

P^{+}

layout was used for the 650 V SiC MOSFETs to reduce the ON-resistance. The devices were packaged into open-cavity TO-247 packages for evaluation. Trade-off analysis of the static and dynamic performance of the 650 V SiC power MOSFETs was conducted. The measurement results show that a short JFET region with an enhanced JFET doping concentration reduces specific ON-resistance (

R_{on, sp}

) and lowers the gate-drain capacitance (

C_{gd}

). It was experimentally shown that a thinner gate oxide further reduces

R_{on, sp}

, although with a penalty in terms of increased

C_{gd}

. A design with 0.5

μ

m half JFET width, enhanced JFET doping concentration of

5.5 \times 10^{16}

cm⁻³, and thin gate oxide produces an excellent high-frequency figure of merit (HF-FOM) among recently published studies on 650 V SiC devices. Full article

(This article belongs to the Special Issue Silicon Carbide: Material Growth, Device Processing and Applications)

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Review

Jump to: Research

29 pages, 8956 KiB

Open AccessEditor’s ChoiceReview

Novel Photonic Applications of Silicon Carbide

by Haiyan Ou, Xiaodong Shi, Yaoqin Lu, Manuel Kollmuss, Johannes Steiner, Vincent Tabouret, Mikael Syväjärvi, Peter Wellmann and Didier Chaussende

Materials 2023, 16(3), 1014; https://doi.org/10.3390/ma16031014 - 22 Jan 2023

Cited by 14 | Viewed by 4668

Abstract

Silicon carbide (SiC) is emerging rapidly in novel photonic applications thanks to its unique photonic properties facilitated by the advances of nanotechnologies such as nanofabrication and nanofilm transfer. This review paper will start with the introduction of exceptional optical properties of silicon carbide. Then, a key structure, i.e., silicon carbide on insulator stack (SiCOI), is discussed which lays solid fundament for tight light confinement and strong light-SiC interaction in high quality factor and low volume optical cavities. As examples, microring resonator, microdisk and photonic crystal cavities are summarized in terms of quality (Q) factor, volume and polytypes. A main challenge for SiC photonic application is complementary metal-oxide-semiconductor (CMOS) compatibility and low-loss material growth. The state-of-the-art SiC with different polytypes and growth methods are reviewed and a roadmap for the loss reduction is predicted for photonic applications. Combining the fact that SiC possesses many different color centers with the SiCOI platform, SiC is also deemed to be a very competitive platform for future quantum photonic integrated circuit applications. Its perspectives and potential impacts are included at the end of this review paper. Full article

(This article belongs to the Special Issue Silicon Carbide: Material Growth, Device Processing and Applications)

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