Research

18 pages, 1010 KiB

Open AccessArticle

Improving Real-Time Performance of Micro-ROS with Priority-Driven Chain-Aware Scheduling

by Zilong Wang, Songran Liu, Dong Ji and Wang Yi

Electronics 2024, 13(9), 1658; https://doi.org/10.3390/electronics13091658 - 25 Apr 2024

Viewed by 159

Micro-ROS is widely used to bridge the performance gap between resource-constrained microcontrollers and powerful computing devices in ROS-based robotic applications. After modeling the callback scheduling module and the communication module in micro-ROS, we found that there are some design flaws that significantly impact [...] Read more.

Micro-ROS is widely used to bridge the performance gap between resource-constrained microcontrollers and powerful computing devices in ROS-based robotic applications. After modeling the callback scheduling module and the communication module in micro-ROS, we found that there are some design flaws that significantly impact the real-time performance of micro-ROS. To improve the timing predictability and run-time efficiency of micro-ROS, we design and implement a priority-driven chain-aware scheduling system (PoDS) based on the existing micro-ROS architecture. The experimental results demonstrate that our proposed PoDS exhibits significantly improved real-time performance compared to the default micro-ROS. Full article

(This article belongs to the Special Issue Embedded Systems: Fundamentals, Design and Practical Applications)

22 pages, 1083 KiB

Open AccessArticle

Robust Embedded PID Control Software Execution Based on Automatic Malfunction Profile Feedback

by Sanghoon Lee and Daejin Park

Electronics 2024, 13(8), 1526; https://doi.org/10.3390/electronics13081526 - 17 Apr 2024

Viewed by 277

Abstract

As the information technology (IT) industry advances, embedded systems are being applied in various industrial sectors. With the expansion of application areas, there is a growing demand for high-precision, high-specification embedded systems, leading to the increased complexity of embedded software. Consequently, software errors [...] Read more.

As the information technology (IT) industry advances, embedded systems are being applied in various industrial sectors. With the expansion of application areas, there is a growing demand for high-precision, high-specification embedded systems, leading to the increased complexity of embedded software. Consequently, software errors can cause system malfunctions, resulting in accidents such as airplane crashes and the sudden acceleration of cars, leading to significant loss of life and property damage. Therefore, measures to ensure the safety and stability of increasing embedded systems malfunctions are necessary. This paper proposes a system that monitors the operation of target embedded systems in real-time and compares the extracted normal operation current/voltage patterns with the current/voltage data of a target embedded system (TES). It compares the operation data of the TES with automatically generated normal operation patterns by forcibly exposing them. It suggests algorithms for immediately detecting and efficiently recovering from the TES malfunctions. The proposed system applies two algorithms. (a) Monitoring TES current: When a malfunction is detected, a monitoring embedded systme (MES) resets the TES to restore normal operation. If malfunctions persist, it controls TES by using an algorithm to shut it down. Additionally, a proportional integral derivation (PID) control is applied to stabilize the current state. (b) Monitoring TES voltage: If a voltage drop occurs, the MES immediately stops the TES operation to minimize damage. The proposed algorithms were validated through experiments. For a normal TES consuming up to 95 mA, an error detection rate of 20% was applied. The TES was reset if it consumed over 114 mA. It was confirmed that the TES was stopped upon detecting the third malfunction. Regarding voltage, when the normal operating voltage of the system was around 5 V, if the TES operating voltage dropped below 4.3 V, it was detected as a malfunction, and the algorithm to stop the TES operation was validated. Full article

(This article belongs to the Special Issue Embedded Systems: Fundamentals, Design and Practical Applications)

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20 pages, 690 KiB

Open AccessArticle

Generative Design of the Architecture Platform in Multiprocessor System Design

by Luise Müller, Nico Schumacher, Lukas Steffen and Christian Haubelt

Electronics 2024, 13(7), 1404; https://doi.org/10.3390/electronics13071404 - 08 Apr 2024

Viewed by 423

Abstract

When designing a system at the Electronic System Level (ESL), designers are confronted with a very large number of design decisions, each affecting the characteristics of the resulting system. Simultaneously, the demands for the system’s performance, reliability, and energy consumption have increased drastically. [...] Read more.

When designing a system at the Electronic System Level (ESL), designers are confronted with a very large number of design decisions, each affecting the characteristics of the resulting system. Simultaneously, the demands for the system’s performance, reliability, and energy consumption have increased drastically. Design Space Exploration (DSE) aims to facilitate this complex task by automating the system synthesis and traversing the design space autonomously. Previous studies on DSE have mainly considered fixed architectures with a fixed set of hardware components only. In the paper at hand, we overcome this limitation to allow for a higher degree of freedom in the design of a multiprocessor system. Instead of a fixed architecture as input, we are using a resource library containing resource types whose instances can then be arbitrarily placed and connected. More specifically, we enable the exploration of the types, the number, and the positions of required processing-type instances in a grid-based topology template in addition to deciding on the remaining system synthesis tasks, namely, resource allocation, task binding, routing, and scheduling. We provide an extensible framework, based on Answer Set Programming (ASP) modulo Theories (ASPmT), for generating system architectures fulfilling predefined constraints. Our studies show that this higher degree of freedom, originating from fewer restrictions regarding the architecture, leads to an increased complexity of the problem. In extensive experiments, we show scalability trends for a set of parameters, demonstrating the capabilities and limits of our approach. Full article

(This article belongs to the Special Issue Embedded Systems: Fundamentals, Design and Practical Applications)

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16 pages, 478 KiB

Open AccessArticle

On-Cloud Linking Approach Using a Linkable Glue Layer for Metamorphic Edge Devices

by Dongkyu Lee and Daejin Park

Electronics 2023, 12(24), 4901; https://doi.org/10.3390/electronics12244901 - 06 Dec 2023

Viewed by 728

Abstract

As sensors operating at the edge continue to evolve, the amount of data that edge devices need to process is increasing. Cloud computing methods have been proposed to process complex data on edge devices that are powered by limited resources. However, the existing [...] Read more.

As sensors operating at the edge continue to evolve, the amount of data that edge devices need to process is increasing. Cloud computing methods have been proposed to process complex data on edge devices that are powered by limited resources. However, the existing cloud computing approach, which provides services from servers determined at the compile stage on the edge, is not suitable for the metamorphic edge device proposed in this paper. Therefore, we have realized the operation of metamorphic edge devices by changing the service that accelerates the application in real time according to the surrounding environmental conditions on the edge device. The on-cloud linking approach separates the code for communication from the edge and server into a linkable glue layer. The separated communication code in the linkable glue layer is reconfigured in real time according to the environment of the edge device. To verify the computational acceleration of cloud computing and the real-time service change of the metamorphic edge device, we operated services that perform matrix multiplication operations with one process, two processes, and four processes in parallel on the edge–cloud system based on the on-cloud linking approach. Through the experiments, it was confirmed that the on-cloud linking approach changes the service provided in real time according to changes in external environmental data without changing the code built into the edge. When a square matrix operation with 1000 rows was loaded onto the proposed platform, the size of the code embedded into the edge device decreased by 8.88% and the operation time decreased by 96.7%. Full article

(This article belongs to the Special Issue Embedded Systems: Fundamentals, Design and Practical Applications)

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23 pages, 1695 KiB

Open AccessArticle

FPGA Implementation of IEC 61131-3-Based Hardware-Aided Timers for Programmable Logic Controllers

by Miroslaw Chmiel, Robert Czerwinski and Andrzej Malcher

Electronics 2023, 12(20), 4255; https://doi.org/10.3390/electronics12204255 - 14 Oct 2023

Viewed by 1159

Abstract

Designs of timer function blocks (FBs) are presented in the article. The developed modules are IEC 61131-3. An analysis of IEC 61131-3 in terms of timer functionality and implementation options is presented. Three types are presented, timer-on, timer-off, and timer-pulse, with each type [...] Read more.

Designs of timer function blocks (FBs) are presented in the article. The developed modules are IEC 61131-3. An analysis of IEC 61131-3 in terms of timer functionality and implementation options is presented. Three types are presented, timer-on, timer-off, and timer-pulse, with each type designed to be fully hardware or software-like. Both designs, hardware or software-like, can operate as multi-channel timers. Particularly noteworthy is the software-like design, for which a solution without edge detectors was achieved. Such a feature was obtained by reversing the method of time determination by counting the difference between the start and end times and by using specific features of the D flip-flops, that is, clock-enable inputs. The presented timers were written in Verilog language and implemented in an FPGA chip. Thanks to the universal design of the interface, the proposed FBs can be used for the hardware support of existing programmable logic controllers (PLCs) or as an integral part of newly built PLC CPUs. The idea of a CPU architecture with hardware support is proposed. The paper presents the results of the implementation in an FPGA of the Kintex UltraScale+ family from AMD-Xilinx. Full article

(This article belongs to the Special Issue Embedded Systems: Fundamentals, Design and Practical Applications)

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23 pages, 807 KiB

Open AccessFeature PaperArticle

Open-Source HW/SW Co-Simulation Using QEMU and GHDL for VHDL-Based SoC Design

by Giorgio Biagetti, Laura Falaschetti, Paolo Crippa, Michele Alessandrini and Claudio Turchetti

Electronics 2023, 12(18), 3986; https://doi.org/10.3390/electronics12183986 - 21 Sep 2023

Cited by 1 | Viewed by 1984

Abstract

Hardware/software co-simulation is a technique that can help design and validate digital circuits controlled by embedded processors. Co-simulation has largely been applied to system-level models, and tools for SystemC or SystemVerilog are readily available, but they are either not compatible or very cumbersome [...] Read more.

Hardware/software co-simulation is a technique that can help design and validate digital circuits controlled by embedded processors. Co-simulation has largely been applied to system-level models, and tools for SystemC or SystemVerilog are readily available, but they are either not compatible or very cumbersome to use with VHDL, the most commonly used language for FPGA design. This paper presents a direct, simple-to-use solution to co-simulate a VHDL design together with the firmware (FW) that controls it. It aims to bring the power of co-simulation to every digital designer, so it uses open-source tools, and the developed code is also open. A small patch applied to the QEMU emulator allows it to communicate with a custom-written VHDL module that exposes a CPU bus to the digital design, controlled by the FW emulated in QEMU. No changes to FW code or VHDL device code are required: with our approach, it is possible to co-simulate the very same code base that would then be implemented into an FPGA, enabling debugging, verification, and tracing capabilities that would not be possible even with the real hardware. Full article

(This article belongs to the Special Issue Embedded Systems: Fundamentals, Design and Practical Applications)

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17 pages, 390 KiB

Open AccessArticle

A New Approach for Implementing Finite State Machines with Input Multiplexing

by Ignacio Garcia-Vargas and Raouf Senhadji-Navarro

Electronics 2023, 12(18), 3763; https://doi.org/10.3390/electronics12183763 - 06 Sep 2023

Viewed by 652

Abstract

The model called Finite State Machine with Input Multiplexing (FSMIM) was proposed as a mechanism for implementing Finite State Machines (FSMs) using ROM memory. This paper presents a novel approach for achieving more efficient FSMIM implementations in Field Programmable Gate Array (FPGA) devices. [...] Read more.

The model called Finite State Machine with Input Multiplexing (FSMIM) was proposed as a mechanism for implementing Finite State Machines (FSMs) using ROM memory. This paper presents a novel approach for achieving more efficient FSMIM implementations in Field Programmable Gate Array (FPGA) devices. The aim of the proposed approach is to obtain further reductions in the use of Embedded Memory Blocks (EMBs). Unlike previous works, the proposed approach reduces the depth of the ROM by grouping states before simplifying the input selectors of the FSMIM. For this purpose, a new strategy for grouping states is proposed, and its optimality is proven. In addition, a new variant of the Minimum Maximal k-Partial Matching (MMKPM) problem and its corresponding Integer Linear Programming (ILP) formulation are proposed for simplifying input selectors. The proposed approach requires a significantly smaller number of EMBs than the approaches proposed previously. Full article

(This article belongs to the Special Issue Embedded Systems: Fundamentals, Design and Practical Applications)

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21 pages, 5266 KiB

Open AccessArticle

Secure Sensor Prototype Using Hardware Security Modules and Trusted Execution Environments in a Blockchain Application: Wine Logistic Use Case

by Antonio J. Cabrera-Gutiérrez, Encarnación Castillo, Antonio Escobar-Molero, Juan Cruz-Cozar, Diego P. Morales and Luis Parrilla

Electronics 2023, 12(13), 2987; https://doi.org/10.3390/electronics12132987 - 07 Jul 2023

Cited by 1 | Viewed by 1367

Abstract

The security of Industrial Internet of Things (IIoT) systems is a challenge that needs to be addressed immediately, as the increasing use of new communication paradigms and the abundant use of sensors opens up new opportunities to compromise these types of systems. In [...] Read more.

The security of Industrial Internet of Things (IIoT) systems is a challenge that needs to be addressed immediately, as the increasing use of new communication paradigms and the abundant use of sensors opens up new opportunities to compromise these types of systems. In this sense, technologies such as Trusted Execution Environments (TEEs) and Hardware Security Modules (HSMs) become crucial for adding new layers of security to IIoT systems, especially to edge nodes that incorporate sensors and perform continuous measurements. These technologies, coupled with new communication paradigms such as Blockchain, offer a high reliability, robustness and good interoperability between them. This paper proposes the design of a secure sensor incorporating the above mentioned technologies—HSMs and a TEE—in a hardware device based on a dual-core architecture. Through this combination of technologies, one of the cores collects the data extracted by the sensors and implements the security mechanisms to guarantee the integrity of these data, while the remaining core is responsible for sending these data through the appropriate communication protocol. This proposed approach fits into the Blockchain networks, which act as an Oracle. Finally, to illustrate the application of this concept, a use case applied to wine logistics is described, where this secure sensor is integrated into a Blockchain that collects data from the storage and transport of barrels, and a performance evaluation of the implemented prototype is provided. Full article

(This article belongs to the Special Issue Embedded Systems: Fundamentals, Design and Practical Applications)

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28 pages, 5675 KiB

Open AccessArticle

Towards On-Board SAR Processing with FPGA Accelerators and a PCIe Interface

by Emilio Isaac Baungarten-Leon, Gustavo Daniel Martín-del-Campo-Becerra, Susana Ortega-Cisneros, Maron Schlemon, Jorge Rivera and Andreas Reigber

Electronics 2023, 12(12), 2558; https://doi.org/10.3390/electronics12122558 - 06 Jun 2023

Viewed by 1513

Abstract

This article addresses a novel methodology for the utilization of Field Programmable Gate Array (FPGA) accelerators in on-board Synthetic Aperture Radar (SAR) processing routines. The methodology consists of using High-Level Synthesis (HLS) to create Intellectual property (IP) blocks and using the Reusable Integration [...] Read more.

This article addresses a novel methodology for the utilization of Field Programmable Gate Array (FPGA) accelerators in on-board Synthetic Aperture Radar (SAR) processing routines. The methodology consists of using High-Level Synthesis (HLS) to create Intellectual property (IP) blocks and using the Reusable Integration Framework for FPGA Accelerators (RIFFA) to develop a Peripheral Component Interconnect express (PCIe) interface between the Central Processing Unit (CPU) and the FPGA, attaining transfer rates up to 15.7 GB/s. HLS and RIFFA reduce development time (between fivefold and tenfold) by using high-level programming languages (e.g., C/C++); moreover, HLS provides optimizations like pipeline, cyclic partition, and unroll. The proposed schematic also has the advantage of being highly flexible and scalable since the IPs can be exchanged to perform different processing routines, and since RIFFA allows employing up to five FPGAs, multiple IPs can be implemented in each FPGA. Since Fast Fourier Transform (FFT) is one of the main functions in SAR processing, we present a FPGA accelerator in charge of the reordering stage of VEC-FFT (an optimized version of FFT) as a proof of concept. Results are retrieved in reversed bit order, and the conventional reordering function may consume more than half of the total clock cycles. Next, to demonstrate flexibility, an IP for matrix transposition is implemented, another computationally expensive process in SAR due to memory access. Full article

(This article belongs to the Special Issue Embedded Systems: Fundamentals, Design and Practical Applications)

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16 pages, 12471 KiB

Open AccessArticle

Control System for Indoor Safety Measures Using a Faster R-CNN Architecture

by Julio Vega

Electronics 2023, 12(11), 2378; https://doi.org/10.3390/electronics12112378 - 24 May 2023

Cited by 1 | Viewed by 864

Abstract

This paper presents a control system for indoor safety measures using a Faster R-CNN (Region-based Convolutional Neural Network) architecture. The proposed system aims to ensure the safety of occupants in indoor environments by detecting and recognizing potential safety hazards in real time, such [...] Read more.

This paper presents a control system for indoor safety measures using a Faster R-CNN (Region-based Convolutional Neural Network) architecture. The proposed system aims to ensure the safety of occupants in indoor environments by detecting and recognizing potential safety hazards in real time, such as capacity control, social distancing, or mask use. Using deep learning techniques, the system detects these situations to be controlled, notifying the person in charge of the company if any of these are violated. The proposed system was tested in a real teaching environment at Rey Juan Carlos University, using Raspberry Pi 4 as a hardware platform together with an Intel Neural Stick board and a pair of PiCamera RGB (Red Green Blue) cameras to capture images of the environment and a Faster R-CNN architecture to detect and classify objects within the images. To evaluate the performance of the system, a dataset of indoor images was collected and annotated for object detection and classification. The system was trained using this dataset, and its performance was evaluated based on precision, recall, and F1 score. The results show that the proposed system achieved a high level of accuracy in detecting and classifying potential safety hazards in indoor environments. The proposed system includes an efficiently implemented software infrastructure to be launched on a low-cost hardware platform, which is affordable for any company, regardless of size or revenue, and it has the potential to be integrated into existing safety systems in indoor environments such as hospitals, warehouses, and factories, to provide real-time monitoring and alerts for safety hazards. Future work will focus on enhancing the system’s robustness and scalability to larger indoor environments with more complex safety hazards. Full article

(This article belongs to the Special Issue Embedded Systems: Fundamentals, Design and Practical Applications)

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13 pages, 2895 KiB

Open AccessArticle

Research and Implementation of Low-Power Anomaly Recognition Method for Intelligent Manhole Covers

by Jiahu Guo, Kai Wang, Jianquan Sun and Youcheng Jia

Electronics 2023, 12(8), 1926; https://doi.org/10.3390/electronics12081926 - 19 Apr 2023

Cited by 2 | Viewed by 1064

Abstract

This paper addresses the difficulty of balancing a real-time response and low power consumption in intelligent manhole cover application scenarios. It proposes a method to distinguish normal and abnormal events by segmenting the boundary at which the acceleration of the intelligent manhole cover [...] Read more.

This paper addresses the difficulty of balancing a real-time response and low power consumption in intelligent manhole cover application scenarios. It proposes a method to distinguish normal and abnormal events by segmenting the boundary at which the acceleration of the intelligent manhole cover deviates from a set threshold and lasts for a certain period, based on the difference in the intelligent manhole cover’s vibration patterns when a normal event and an abnormal event occur. This paper uses the autonomous data fusion of digital output motion sensor data to implement a pattern recognition algorithm for the above-mentioned pattern, which reduces the MCU computing and working time and the overall power consumption of the system while meeting real-time response requirements. The test results demonstrate that the method has a high rate of anomaly recognition accuracy. The method ensures the system’s real-time response capability, and the actual low power consumption test demonstrates that the device can operate continuously for 9.5 years. The low power consumption index exceeds the requirements of the existing national standard, thereby resolving the issue that it is challenging to balance intelligent manhole cover abnormality recognition and low power consumption. Full article

(This article belongs to the Special Issue Embedded Systems: Fundamentals, Design and Practical Applications)

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15 pages, 604 KiB

Open AccessArticle

Mapping Outputs and States Encoding Bits to Outputs Using Multiplexers in Finite State Machine Implementations

by Raouf Senhadji-Navarro and Ignacio Garcia-Vargas

Electronics 2023, 12(3), 502; https://doi.org/10.3390/electronics12030502 - 18 Jan 2023

Cited by 1 | Viewed by 1126

Abstract

This paper proposes a new technique for implementing Finite State Machines (FSMs) in Field Programmable Gate Arrays (FPGAs). The proposed approach extends the called column compaction in two ways. First, it is applied to the state-encoding bits in addition to the outputs, allowing [...] Read more.

This paper proposes a new technique for implementing Finite State Machines (FSMs) in Field Programmable Gate Arrays (FPGAs). The proposed approach extends the called column compaction in two ways. First, it is applied to the state-encoding bits in addition to the outputs, allowing a reduction in the number of logic functions required both by the state transition function and by the output function. Second, the technique exploits the dedicated multiplexers usually included in FPGAs to increase the number of columns that can be compacted. Unlike conventional state-encoding techniques, the proposed approach reduces the number of logic functions instead of their complexity. An Integer Linear Programming (ILP) formulation that maximizes the number of compacted columns has been proposed. In order to evaluate the effectiveness of the proposed approach, experimental results using standard benchmarks are presented. In most cases, the proposed approach reduces the number of used Look-Up Tables (LUTs) with respect to the conventional FSM implementation. Full article

(This article belongs to the Special Issue Embedded Systems: Fundamentals, Design and Practical Applications)

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18 pages, 2256 KiB

Open AccessFeature PaperArticle

A Mixed Hardware-Software Implementation of a High-Performance PMSM Controller

by Adam Milik and Tomasz Rudnicki

Electronics 2023, 12(2), 440; https://doi.org/10.3390/electronics12020440 - 14 Jan 2023

Cited by 4 | Viewed by 1088

Abstract

Implementation of the permanent magnet synchronous motor vector control implies strong time dependencies. The control process requires precise measurement of motor shaft position and winding currents to establish correct driving. The tight time dependencies are difficult to achieve using a programmatic approach. Specific [...] Read more.

Implementation of the permanent magnet synchronous motor vector control implies strong time dependencies. The control process requires precise measurement of motor shaft position and winding currents to establish correct driving. The tight time dependencies are difficult to achieve using a programmatic approach. Specific controller architecture is proposed for programmable systems on chip architectures enabling operations precise timing and improved processing performance. The controller is decomposed into a dedicated hardware interface system and programmatic part for easy implementation and modification of the control algorithm. The proposed architecture offers precise and repeatable input-output operations timing and assures meeting tight time dependencies. The control algorithm is executed as an interrupt service requested by the interface system in a constant processing period with relatively weak time dependencies. Additionally, the interface system preprocesses input and output signals reducing the computation effort and saving time for algorithm computations. The specific implementation enabled improved measurement of the motor’s windings current with suppression of disturbances caused by inverter operation. There is shown an efficient implementation of Parke’s and Clarke’s transformations using specific resources of modern programmable logic devices. In opposite to the software-managed implementation presented implementation assures completing processing faster, using a minimal number of hardware resources of the FPGA platform and offering the highest flexibility of software part implementation. Full article

(This article belongs to the Special Issue Embedded Systems: Fundamentals, Design and Practical Applications)

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23 pages, 1188 KiB

Open AccessArticle

Mutable Observation Used by Television Drone Pilots: Efficiency of Aerial Filming Regarding the Quality of Completed Shots

by Grzegorz Borowik, Monika Kożdoń-Dębecka and Sebastian Strzelecki

Electronics 2022, 11(23), 3881; https://doi.org/10.3390/electronics11233881 - 24 Nov 2022

Cited by 2 | Viewed by 1447

Abstract

Drones, as mobile media of the present day, increase the operational and narrative capabilities of television and accelerate the logistics of shooting. Unmanned aerial vehicles with a camera properly steered by a pilot are able, to some extent, to replace a jimmy jib/crane [...] Read more.

Drones, as mobile media of the present day, increase the operational and narrative capabilities of television and accelerate the logistics of shooting. Unmanned aerial vehicles with a camera properly steered by a pilot are able, to some extent, to replace a jimmy jib/crane and a dolly; basic technical devices, used in the studios, enabling the creation of narrative systems of pictures in film and television. Television is more and more often using drone footage to report events, broadcast live, as well as create coverage and television documentaries. In many productions, the pilot of the drone simultaneously acts as the drone camera operator, which can improve the effectiveness of shooting, but also carries some risks related to flight safety. The article describes and presents in the form of processed footage the real conditional ties of a Visual Line of Sight (VLOS) flight faced by pilots filming with a drone. VLOS is a type of air operation, which requires maintaining eye contact with the drone. In many countries, a drone visibility flight is legally sanctioned as VLOS Operation. An experiment was conducted to investigate the interactions between a human and a machine in airspace steered using a controller with a touchscreen. The drone pilot was considered an integral part of the drone’s flight system control Experimental data was collected with the use of a mobile eye-tracker, video cameras, surveys, and pilot declarations. During the experiment, eight television drone pilot operators recaptured a model shot under the regime of VLOS flight at low altitudes. They all show that both advanced and beginner pilots did not look at the UAV for over half the time of shot execution. The experiment allowed establishing two coefficients related to the effectiveness of a VLOS flight aiming at filming from the drone. The results point to clear differences in screen perception styles used by drone television pilots. The coefficients were described in the form of mathematical formulas and their limit values were determined. The research also determines the limits of pilots’ perception, within which they can film with a drone. The outcomes may help to optimize the process of aerial filming with the use of a drone, carried out for television, film, and other media, as well as in a simulation of such a flight for research and training. From the perspective of media science and social communication, the presented study included a technological component that can be accessed through information science, using statistical models and variable distributions. Media scholars can study the impact of the media without having to look into the metaphorical black box. Computer science opens up this possibility. Full article

(This article belongs to the Special Issue Embedded Systems: Fundamentals, Design and Practical Applications)

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19 pages, 3649 KiB

Open AccessArticle

Efficient FPGA Implementation of an RFIR Filter Using the APC–OMS Technique with WTM for High-Throughput Signal Processing

by Kasarla Satish Reddy, Sowmya Madhavan, Przemysław Falkowski-Gilski, Parameshachari Bidare Divakarachari and Arun Mathiyalagan

Electronics 2022, 11(19), 3118; https://doi.org/10.3390/electronics11193118 - 29 Sep 2022

Cited by 8 | Viewed by 1777

Abstract

Nowadays, Finite Impulse Response (FIR) filters are used to change the attributes of a signal in the time or frequency domain. Among FIR filters, a reconfigurable filter has the advantage of changing the coefficient in real-time, while performing the operation. In this paper, [...] Read more.

Nowadays, Finite Impulse Response (FIR) filters are used to change the attributes of a signal in the time or frequency domain. Among FIR filters, a reconfigurable filter has the advantage of changing the coefficient in real-time, while performing the operation. In this paper, the Anti-Symmetric Product Coding (APC) and Odd Multiple Storage (OMS) modules are utilized to implement the reconfigurable FIR filter (RFIR–APC–OMS). Herein, the APC–OMS module is used to reduce the area of the RFIR architecture. The performance of the RFIR–APC–OMS is analyzed in terms of: area, power, delay, LUT, flip flop, slices, and frequency. RFIR–APC–OMS has reduced 3.44% of area compared to the existing RFIR architecture employing the Dynamic Reconfigurable Partial Product Generator (DRPPG) module. Full article

(This article belongs to the Special Issue Embedded Systems: Fundamentals, Design and Practical Applications)

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26 pages, 7151 KiB

Open AccessArticle

Using a Double-Core Structure to Reduce the LUT Count in FPGA-Based Mealy FSMs

by Alexander Barkalov, Larysa Titarenko and Kazimierz Krzywicki

Electronics 2022, 11(19), 3089; https://doi.org/10.3390/electronics11193089 - 27 Sep 2022

Cited by 2 | Viewed by 1453

Abstract

A method is proposed which aims at reducing the numbers of look-up table (LUT) elements in logic circuits of Mealy finite state machines (FSMs). The FSMs with twofold state assignment are discussed. The reduction is achieved due to using two cores of LUTs [...] Read more.

A method is proposed which aims at reducing the numbers of look-up table (LUT) elements in logic circuits of Mealy finite state machines (FSMs). The FSMs with twofold state assignment are discussed. The reduction is achieved due to using two cores of LUTs for generating partial Boolean functions. One core is based on maximum binary state codes. The second core uses extended state codes. Such an approach allows reducing the number of LUTs in the block of state codes’ transformation. The proposed approach leads to LUT-based Mealy FSM circuits having three levels of logic blocks. Each partial function for any core is represented by a single-LUT circuit. A formal method is proposed for redistribution of states between these cores. An example of synthesis is shown to explain peculiarities of the proposed method. An example of state redistribution is given. The results of experiments conducted with standard benchmarks show that the double-core approach produces LUT-based FSM circuits with better area-temporal characteristics than they are for circuits produced by other investigated methods (Auto and One-hot of Vivado, JEDI, and twofold state assignment). Both the LUT counts and maximum operating frequencies are improved. The gain in LUT counts varies from 5.74% to 36.92%, and the gain in frequency varies from 5.42% to 12.4%. These improvements are connected with a very small growth of the power consumption (less than 1%). The advantages of the proposed approach increase as the number of FSM inputs and states increases. Full article

(This article belongs to the Special Issue Embedded Systems: Fundamentals, Design and Practical Applications)

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22 pages, 2802 KiB

Open AccessArticle

A Knowledge Base Technique for Detecting Multiple High-Speed Serial Interface Synchronization Errors in Multiprocessor-Based Real-Time Embedded Systems

by Sabeen Masood, Shoab Ahmed Khan, Ali Hassan and Fatima Khalique

Electronics 2022, 11(18), 2945; https://doi.org/10.3390/electronics11182945 - 17 Sep 2022

Viewed by 1363

Abstract

The heterogeneity of the multiple processing elements (PEs) is a feature of real-time embedded systems. General-purpose processors and several embedded processors, as well as dedicated high-speed interfaces, are among these elements. Communication between the processors is among the most significant characteristics of developing [...] Read more.

The heterogeneity of the multiple processing elements (PEs) is a feature of real-time embedded systems. General-purpose processors and several embedded processors, as well as dedicated high-speed interfaces, are among these elements. Communication between the processors is among the most significant characteristics of developing such complex systems. Furthermore, synchronization is a common issue during interprocessor communication in embedded systems. Debugging and testing such systems is time-consuming, difficult, and laborious, with the majority of the complexities centered on debugging real-time interprocessor communication, such as synchronization in terms of timing and accuracy. While the hardware design features of heterogeneous multiprocessor real-time embedded systems have received a lot of attention, the design and development of software-based solutions still have the potential to be addressed. In particular, software-based testing becomes challenging due to interprocessor communication and the synchronization of real-time applications. A knowledge-based technique that aids in testing high-speed serial interfaces in multiprocessor-based real-time embedded systems is proposed that needs debugging in real time while an application is running. It is becoming much more important to test and validate these interfaces in real time as the demand for high data transmission rates increases. The presented work uses a technique to simulate, create and enhance the knowledge base used as correlation-based error detection that reduces the development time. The proposed technique helps in detecting synchronization-related errors that occur during communication among multiple high-speed serial interfaces. The presented work also lists a series of experiments to validate the effectiveness of the proposed technique. The results show that the presented techniques are effective for error identification in real-time embedded systems. Full article

(This article belongs to the Special Issue Embedded Systems: Fundamentals, Design and Practical Applications)

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20 pages, 3035 KiB

Open AccessArticle

An Efficient Real-Time FPGA-Based ORB Feature Extraction for an UHD Video Stream for Embedded Visual SLAM

by Mateusz Wasala, Hubert Szolc and Tomasz Kryjak

Electronics 2022, 11(14), 2259; https://doi.org/10.3390/electronics11142259 - 20 Jul 2022

Cited by 7 | Viewed by 2847

Abstract

The detection and description of feature points are important components of many computer vision systems. For example, in the field of autonomous unmanned aerial vehicles (UAV), these methods form the basis of so-called Visual Odometry (VO) and Simultaneous Localisation and Mapping (SLAM) algorithms. [...] Read more.

The detection and description of feature points are important components of many computer vision systems. For example, in the field of autonomous unmanned aerial vehicles (UAV), these methods form the basis of so-called Visual Odometry (VO) and Simultaneous Localisation and Mapping (SLAM) algorithms. In this paper, we present a hardware feature points detection system able to process a 4K video stream in real-time. We use the ORB algorithm—Oriented FAST (Features from Accelerated Segment Test) and Rotated BRIEF (Binary Robust Independent Elementary Features)—to detect and describe feature points in the images. We make numerous modifications to the original ORB algorithm (among others, we use the RS-BRIEF instead of classic R-BRIEF) to adapt it to the high video resolution, make it computationally efficient, reduce the resource utilisation and achieve lower power consumption. Our hardware implementation supports a 4 ppc (pixels per clock) format (with simple adaptation to 2 ppc, 8 ppc, and more) and real-time processing of a 4K video stream (UHD—Ultra High Definition,

3840 \times 2160

pixels) @ 60 frames per second (150 MHz clock). We verify our system using simulations in the Vivado IDE and implement it in hardware on the ZCU 104 evaluation board with the AMD Xilinx Zynq UltraScale+ MPSoC device. The proposed design consumes only 5 watts. Full article

(This article belongs to the Special Issue Embedded Systems: Fundamentals, Design and Practical Applications)

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24 pages, 27795 KiB

Open AccessArticle

Real-Time CLAHE Algorithm Implementation in SoC FPGA Device for 4K UHD Video Stream

by Tomasz Kryjak, Krzysztof Blachut, Hubert Szolc and Mateusz Wasala

Electronics 2022, 11(14), 2248; https://doi.org/10.3390/electronics11142248 - 18 Jul 2022

Cited by 4 | Viewed by 5175

Abstract

One of the problems encountered in the field of computer vision and video data analysis is the extraction of information from low-contrast images. This problem can be addressed in several ways, including the use of histogram equalisation algorithms. In this work, a method [...] Read more.

One of the problems encountered in the field of computer vision and video data analysis is the extraction of information from low-contrast images. This problem can be addressed in several ways, including the use of histogram equalisation algorithms. In this work, a method designed for this purpose—the Contrast-Limited Adaptive Histogram Equalization (CLAHE) algorithm—is implemented in hardware. An FPGA platform is used for this purpose due to the ability to run parallel computations and very low power consumption. To enable the processing of a 4K resolution (UHD, 3840 × 2160 pixels) video stream at 60 fps (frames per second) by using the CLAHE method, it is necessary to use a vector data format and process multiple pixels simultaneously. The algorithm realised in this work can be a component of a larger vision system, such as in autonomous vehicles or drones, but it can also support the analysis of underwater, thermal, or medical images both by humans and in an automated system. Full article

(This article belongs to the Special Issue Embedded Systems: Fundamentals, Design and Practical Applications)

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26 pages, 449 KiB

Open AccessArticle

Using Codes of Output Collections for Hardware Reduction in Circuits of LUT-Based Finite State Machines

by Alexander Barkalov, Larysa Titarenko, Kazimierz Krzywicki and Kamil Mielcarek

Electronics 2022, 11(13), 2050; https://doi.org/10.3390/electronics11132050 - 29 Jun 2022

Viewed by 1285

Abstract

A method is proposed which aims to reduce the hardware in FPGA-based circuits of Mealy finite state machines (FSMs). The proposed method is a type of structural decomposition method. Its main goal is the reducing the number of look-up table (LUT) elements in [...] Read more.

A method is proposed which aims to reduce the hardware in FPGA-based circuits of Mealy finite state machines (FSMs). The proposed method is a type of structural decomposition method. Its main goal is the reducing the number of look-up table (LUT) elements in FSM circuits compared to the three-block FSM circuit. The main idea of the proposed method is the using codes of collections of FSM outputs for replacing the FSM inputs and state variables. The interstate transitions are defined using collections of outputs generated in two adjacent cycles of synchronization. One, of output collection codes, is kept into a register. To optimize block-generating FSM outputs, a new type of state codes is proposed. A state is encoded as an element of some class of states. This approach allows both the number of logic levels and inter-level interconnections in LUT-based FSM circuit to be diminished. An example of an LUT-based Mealy FSM circuit with the proposed method applied is shown. Moreover, the results of our research are represented. The research was conducted using the CAD tool Vivado by Xilinx. The experiments prove that the proposed approach allows the reduction of hardware compared with such known methods as Auto and One-hot of Vivado, and JEDI. Moreover, the proposed approach gives better results than a method based on the simultaneous replacement of inputs and encoding collections of outputs. Compared to circuits of the three-block FSMs, the LUT counts are reduced by an average of 10.07% without significant reduction in the value of operating frequency. The gain in LUT counts increases with the increasing the numbers of FSM states and inputs. Full article

(This article belongs to the Special Issue Embedded Systems: Fundamentals, Design and Practical Applications)

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