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Electronics
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Advanced Integrated Circuits Technology
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Advanced Integrated Circuits Technology

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Microelectronics".

Deadline for manuscript submissions: closed (30 November 2021) | Viewed by 33111

Special Issue Editors

Prof. Dr. Yuh-Shyan Hwang

E-Mail Website1 Website2
Guest Editor
Department of Electronic Engineering, National Taipei University of Technology, Taipei 106, Taiwan
Interests: analog/power/mixed-signal integrated circuit design; VLSI design; current-mode analog signal processing
Dr. San-Fu Wang

E-Mail Website1 Website2
Co-Guest Editor
Department of Electronic Engineering, National Chin-Yi University of Technology, Taichung City 41170, Taiwan
Interests: analog IC design; RF IC design; power IC design
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

Dear Colleagues,

This Special Issue pertains to the 5th International Symposium on Computer, Consumer and Control (IS3C2020) to be held in Taichung, Taiwan, 18–20 June 2020. This conference offers a great opportunity for scientists, engineers, and practitioners to present the latest research results, ideas, developments, and applications. IS3C, held every two years, is hosted and sponsored by the National Chin-Yi University of Technology, Taichung, Taiwan. As suggested by the name of the conference, its themes cover advanced multimedia, computer, telecommunication, sensors and semiconductors, consumer electronics, renewable energy, systems and control, and digital signal processing. Original high-quality papers related to these themes are especially solicited, including theories, methodologies, and applications in Computing, Consumer and Control.

The success and proliferation of integrated circuits has largely hinged on the ability of IC manufacturers to continue offering more performance and functionality for the money. Driving down the cost of ICs (on a per-function or per-performance basis) is inescapably tied to a growing arsenal of technologies and wafer-fab manufacturing disciplines as mainstream CMOS processes reach their theoretical, practical, and economic limits. Among the many levers being pulled by IC designers and manufacturers are feature-size reductions, introduction of new materials and transistor structures, migration to larger-diameter silicon wafers, higher throughput in fab equipment, increased factory automation, three-dimensional integration of circuitry and chips, and advanced IC packaging and holistic system-driven design approaches.

For five decades, the industry has enjoyed exponential improvements in the productivity and performance of integrated circuit technology. While the industry has continued to surmount obstacles placed in front of it, the barriers are getting bigger. Feature size reduction, wafer diameter increases, and yield improvement all have physical or statistical limits, or more commonly economic limits. Therefore, IC companies continue to wring every bit of productivity out of existing processes before looking to major technological advances to solve problems.

The topics are included but not limited to:

  • Sensor, measurement, and control;
  • Communication systems;
  • Low power analog circuit design;
  • AIoT network;
  • Wireless communication circuits for 5G applications;
  • Sensor applications;
  • Power circuit and energy harvesting.

Prof. Dr. Yuh-Shyan Hwang
Assoc. Prof. San-Fu Wang
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • systems on chip
  • application of microelectronics
  • measurement
  • control technology
  • sensors
  • sensing technology
  • micro electromechanical systems
  • micro actuators

Published Papers (8 papers)

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Research

14 pages, 4237 KiB  
Article
A Bootstrap Structure Directly Charged by BUS Voltage with Threshold-Based Digital Control for High-Speed Buck Converter
by Yujie Guo, Fang Yuan, Yukuan Chang, Yuxia Kou and Xu Zhang
Electronics 2021, 10(22), 2863; https://doi.org/10.3390/electronics10222863 - 20 Nov 2021
Cited by 1 | Viewed by 3031
Abstract
This article proposes a high-frequency, area-efficient high-side bootstrap circuit with threshold-based digital control (TBDC) that is directly charged by BUS voltage (DCBV). In the circuit, the voltage of the bootstrap is directly obtained from the BUS voltage instead of the on-chip low dropout [...] Read more.
This article proposes a high-frequency, area-efficient high-side bootstrap circuit with threshold-based digital control (TBDC) that is directly charged by BUS voltage (DCBV). In the circuit, the voltage of the bootstrap is directly obtained from the BUS voltage instead of the on-chip low dropout regulator (LDO), which is more suitable for a high operating frequency. An area-efficient threshold-based digital control structure is used to detect the bootstrap voltage, thereby effectively preventing bootstrap under-voltage or over-voltage that may result in insufficient driving capability, increased loss, or breakdown of the power device. The design and implementation of the circuit are based on CSMC 0.25 µm 60 V BCD technology, with an overall chip area of 1.4 × 1.3 mm2, of which the bootstrap area is 0.149 mm2 and the figure-of-merit (FOM) is 0.074. The experimental results suggest that the bootstrap circuit can normally operate at 5 MHz with a maximum buck converter efficiency of 83.6%. This work plays a vital role in promoting the development of a wide range of new products and new technologies, such as integrated power supplies, new energy vehicles, and data storage centers. Full article
(This article belongs to the Special Issue Advanced Integrated Circuits Technology)
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20 pages, 5398 KiB  
Article
Memory Access Optimization of a Neural Network Accelerator Based on Memory Controller
by Rongshan Wei, Chenjia Li, Chuandong Chen, Guangyu Sun and Minghua He
Electronics 2021, 10(4), 438; https://doi.org/10.3390/electronics10040438 - 10 Feb 2021
Cited by 4 | Viewed by 5090
Abstract
Special accelerator architecture has achieved great success in processor architecture, and it is trending in computer architecture development. However, as the memory access pattern of an accelerator is relatively complicated, the memory access performance is relatively poor, limiting the overall performance improvement of [...] Read more.
Special accelerator architecture has achieved great success in processor architecture, and it is trending in computer architecture development. However, as the memory access pattern of an accelerator is relatively complicated, the memory access performance is relatively poor, limiting the overall performance improvement of hardware accelerators. Moreover, memory controllers for hardware accelerators have been scarcely researched. We consider that a special accelerator memory controller is essential for improving the memory access performance. To this end, we propose a dynamic random access memory (DRAM) memory controller called NNAMC for neural network accelerators, which monitors the memory access stream of an accelerator and transfers it to the optimal address mapping scheme bank based on the memory access characteristics. NNAMC includes a stream access prediction unit (SAPU) that analyzes the type of data stream accessed by the accelerator via hardware, and designs the address mapping for different banks using a bank partitioning model (BPM). The image mapping method and hardware architecture were analyzed in a practical neural network accelerator. In the experiment, NNAMC achieved significantly lower access latency of the hardware accelerator than the competing address mapping schemes, increased the row buffer hit ratio by 13.68% on average (up to 26.17%), reduced the system access latency by 26.3% on average (up to 37.68%), and lowered the hardware cost. In addition, we also confirmed that NNAMC efficiently adapted to different network parameters. Full article
(This article belongs to the Special Issue Advanced Integrated Circuits Technology)
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27 pages, 9703 KiB  
Article
Versatile Voltage-Mode Biquadratic Filter and Quadrature Oscillator Using Four OTAs and Two Grounded Capacitors
by San-Fu Wang, Hua-Pin Chen, Yitsen Ku and Chia-Ling Lee
Electronics 2020, 9(9), 1493; https://doi.org/10.3390/electronics9091493 - 11 Sep 2020
Cited by 28 | Viewed by 3019
Abstract
This article presents a versatile voltage-mode (VM) biquad filter with independently electronic tunability. The proposed structure using one dual-output operational transconductance amplifier, three single-output operational transconductance amplifiers (OTAs) and two grounded capacitors was explored to derive a new VM quadrature oscillator with the [...] Read more.
This article presents a versatile voltage-mode (VM) biquad filter with independently electronic tunability. The proposed structure using one dual-output operational transconductance amplifier, three single-output operational transconductance amplifiers (OTAs) and two grounded capacitors was explored to derive a new VM quadrature oscillator with the independent control of the oscillation frequency and the oscillation condition. The proposed versatile VM biquad filter achieves nearly all of the main advantages: (i) simultaneous realizations of band-reject, band-pass, and low-pass from the same architecture, (ii) multiple-input and multiple-output functions, (iii) independent electronic adjustability of quality factor and resonant angular frequency, (iv) no resistor needed, (v) all input terminals with cascade functions, (vi) no additional inverting amplifier for input signals, (vii) using only grounded capacitors, and (viii) easy to implement a VM quadrature oscillator with independent electronically controlled oscillation frequency and oscillation condition. The proposed versatile VM biquad filter employs only four OTAs and two grounded capacitors. The active components of the proposed VM biquad filter are one less than that of recent reports. The proposed circuit also brings versatility and simplicity to the design of VM biquad filters and VM quadrature oscillators. Filters and oscillators with less active and passive components have the advantages of low cost, low power dissipation, low circuit complexity, and low noise. Commercially available integrated circuit LT1228 and discrete components can be used to implement the proposed OTA-based circuits. The simulation and experiment results validated the theoretical analysis. Full article
(This article belongs to the Special Issue Advanced Integrated Circuits Technology)
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17 pages, 2454 KiB  
Article
The Design of Compact SM4 Encryption and Decryption Circuits That Are Resistant to Bypass Attack
by Fang Zhou, Benjun Zhang, Ning Wu and Xiangli Bu
Electronics 2020, 9(7), 1102; https://doi.org/10.3390/electronics9071102 - 06 Jul 2020
Cited by 5 | Viewed by 3308
Abstract
In order to achieve the purpose of defending against side channel attacks, a compact SM4 circuit was designed based on the mask and random delay technique, and the linear transformation module was designed with random insertion of the pseudo operation method. By analyzing [...] Read more.
In order to achieve the purpose of defending against side channel attacks, a compact SM4 circuit was designed based on the mask and random delay technique, and the linear transformation module was designed with random insertion of the pseudo operation method. By analyzing the glitch data generated by the S-box of SM4 with different inputs, the security against glitch attacks was confirmed. Then, the DPA (Differential Power Analysis) was performed on the designed circuit. The key could not be successfully obtained even in the case of 100,000 power curves, so that the safety of SM4 against DPA is verified. Finally, using Synopsys DC (Design Compiler, Mountain View, CA94043DC, USA) to synthesize the designed circuit, the results show that the area of the designed circuit in the SMIC 0.18 process is 82,734 μm2, which is 48% smaller than results reported in other papers. Full article
(This article belongs to the Special Issue Advanced Integrated Circuits Technology)
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15 pages, 8055 KiB  
Article
An Area-Efficient and Programmable 4 × 25-to-28.9 Gb/s Optical Receiver with DCOC in 0.13 µm SiGe BiCMOS
by Haojie Xu, Jiarui Liu, Zhiyu Wang, Min Zhou, Jiongjiong Mo and Faxin Yu
Electronics 2020, 9(6), 1032; https://doi.org/10.3390/electronics9061032 - 22 Jun 2020
Viewed by 2746
Abstract
In this paper, we present an area-efficient noise-optimized programmable 4 × 25-to-28.9 Gb/s optical receiver. Both high- and low-power modes are available for the receiver to meet different requirements. Emitter degeneration provides the input transimpedance amplifier (TIA) stage with improved stability. The noise [...] Read more.
In this paper, we present an area-efficient noise-optimized programmable 4 × 25-to-28.9 Gb/s optical receiver. Both high- and low-power modes are available for the receiver to meet different requirements. Emitter degeneration provides the input transimpedance amplifier (TIA) stage with improved stability. The noise of the TIA with emitter degeneration is analyzed, and an improved noise optimization method for the TIA is proposed. A sink current source with emitter degeneration in a DC offset cancellation (DCOC) loop reduces the noise introduced by the DCOC circuit. Moreover, with parasitic capacitor utilization in the DCOC loop and capacitive emitter degeneration in the variable-gain amplifier (VGA) stage, the chip area is minimized. Fabricated in a 0.13 µm SiGe BiCMOS technology, the receiver achieved a small area of 0.54 mm2 per lane. The measured bit error rate (BER) is 10−12 with input signal varying from 110 μApp to 1150 μApp. The one-lane power dissipation values in the low-power and high-power modes are 84.97 mW and 123.75 mW, respectively. Full article
(This article belongs to the Special Issue Advanced Integrated Circuits Technology)
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10 pages, 2996 KiB  
Article
Optimizing Crosstalk in Optical NoC through Heuristic Fusion Mapping
by Xinhao Shi, Ning Wu, Fen Ge, Fang Zhou and Muhammad Rehan Yahya
Electronics 2020, 9(6), 1006; https://doi.org/10.3390/electronics9061006 - 16 Jun 2020
Cited by 4 | Viewed by 1801
Abstract
Optical network-on-chip is considered to be a promising technology to solve the problems of low bandwidth and high latency in the traditional interconnection network. However, due to the inevitable leakage of optical devices, the optical signal will receive crosstalk noise during transmission. In [...] Read more.
Optical network-on-chip is considered to be a promising technology to solve the problems of low bandwidth and high latency in the traditional interconnection network. However, due to the inevitable leakage of optical devices, the optical signal will receive crosstalk noise during transmission. In this paper, a heuristic fusion mapping algorithm PSO_SA for crosstalk optimization is proposed. First, the initial optimal mapping is obtained by particle swarm optimization, and then the local optimization of the mapping scheme is removed by combining with simulated annealing algorithm. The experimental results show that the crosstalk optimization performance of PSO_SA algorithm is better than that of GA algorithm in 263 dec, Wavelet, DVOPD and other applications, and the maximum optimization degree is 28.7%. Full article
(This article belongs to the Special Issue Advanced Integrated Circuits Technology)
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27 pages, 6102 KiB  
Article
A Low Complexity, High Throughput DoA Estimation Chip Design for Adaptive Beamforming
by Kuan-Ting Chen, Wei-Hsuan Ma, Yin-Tsung Hwang and Kuan-Ying Chang
Electronics 2020, 9(4), 641; https://doi.org/10.3390/electronics9040641 - 13 Apr 2020
Cited by 4 | Viewed by 3431
Abstract
Direction of Arrival (DoA) estimation is essential to adaptive beamforming widely used in many radar and wireless communication systems. Although many estimation algorithms have been investigated, most of them focus on the performance enhancement aspect but overlook the computing complexity or the hardware [...] Read more.
Direction of Arrival (DoA) estimation is essential to adaptive beamforming widely used in many radar and wireless communication systems. Although many estimation algorithms have been investigated, most of them focus on the performance enhancement aspect but overlook the computing complexity or the hardware implementation issues. In this paper, a low-complexity yet effective DoA estimation algorithm and the corresponding hardware accelerator chip design are presented. The proposed algorithm features a combination of signal sub-space projection and parallel matching pursuit techniques, i.e., applying signal projection first before performing matching pursuit from a codebook. This measure helps minimize the interference from noise sub-space and makes the matching process free of extra orthogonalization computations. The computing complexity can thus be reduced significantly. In addition, estimations of all signal sources can be performed in parallel without going through a successive update process. To facilitate an efficient hardware implementation, the computing scheme of the estimation algorithm is also optimized. The most critical part of the algorithm, i.e., calculating the projection matrix, is largely simplified and neatly accomplished by using QR decomposition. In addition, the proposed scheme supports parallel matches of all signal sources from a beamforming codebook to improve the processing throughput. The algorithm complexity analysis shows that the proposed scheme outperforms other well-known estimation algorithms significantly under various system configurations. The performance simulation results further reveal that, subject to a beamforming codebook with a 5° angular resolution, the Root Mean Square (RMS) error of angle estimations is only 0.76° when Signal to Noise Ratio (SNR) = 20 dB. The estimation accuracy outpaces other matching pursuit based approaches and is close to that of the classic Estimation of Signal Parameters Via Rotational Invariance Techniques (ESPRIT) scheme but requires only one fifth of its computing complexity. In developing the hardware accelerator design, pipelined Coordinate Rotation Digital Computer (CORDIC) processors consisting of simple adders and shifters are employed to implement the basic trigonometric operations needed in QR decomposition. A systolic array architecture is developed as the computing kernel for QR decomposition. Other computing modules are also realized using various linear systolic arrays and chained together seamlessly to maximize the computing throughput. A Taiwan Semiconductor Manufacturing Company (TSMC) 40 nm CMOS process was chosen as the implementation technology. The gate count of the chip design is 454.4k, featuring a core size of 0.76 mm 2 , and can operate up to 333 MHz. This suggests that one DoA estimation, with up to three signal sources, can be performed every 2.38 μs. Full article
(This article belongs to the Special Issue Advanced Integrated Circuits Technology)
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11 pages, 3627 KiB  
Article
An AMOLED Pixel Circuit Based on LTPS Thin-film Transistors with Mono-Type Scanning Driving
by Jianyuan Ke, Lianwen Deng, Liying Zhen, Qing Wu, Congwei Liao, Heng Luo and Shengxiang Huang
Electronics 2020, 9(4), 574; https://doi.org/10.3390/electronics9040574 - 28 Mar 2020
Cited by 4 | Viewed by 9498
Abstract
Using low-temperature poly-silicon thin-film transistors (LTPS TFTs) as a basis, a pixel circuit for an active matrix organic light-emitting diode (AMOLED) with narrow bezel displays was developed. The pixel circuit features mono-type scanning signals, elimination of static power lines, and pixel-integrated emitting control [...] Read more.
Using low-temperature poly-silicon thin-film transistors (LTPS TFTs) as a basis, a pixel circuit for an active matrix organic light-emitting diode (AMOLED) with narrow bezel displays was developed. The pixel circuit features mono-type scanning signals, elimination of static power lines, and pixel-integrated emitting control functions. Therefore, gate driver circuits of the display bezel can be simplified efficiently. In addition, the pixel circuit has a high-resolution design due to an increase of the pulse width of the scan signal to extend the threshold voltage and internal–resistance drop (IR drop) detection period. Further, regarding the influences of process–voltage–temperature (PVT) variation in the pixel circuit, comparison investigations were carried out with the proposed circuit and other pixel circuits with mono-type scanning signals using Monte Carlo analysis. The feasibility of the proposed pixel circuit is well demonstrated, as the current variations can be reduced to 2.1% for the supplied power reduced from 5 V to 3 V due to IR drop, and the current variation is as low as 10.6% with operating temperatures from –40 degrees to 85 degrees. Full article
(This article belongs to the Special Issue Advanced Integrated Circuits Technology)
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