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Electronics
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Modeling and Design of Integrated CMOS Circuit
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Modeling and Design of Integrated CMOS Circuit

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Microelectronics".

Deadline for manuscript submissions: closed (31 March 2022) | Viewed by 11336

Special Issue Editors

Dr. Laurent Artola

E-Mail Website
Guest Editor
Department of Physics Instrumentation Environment and Space (ONERA/DPHY), Université de Toulouse, F-31055 Toulouse, France
Interests: electronic reliability; single event effects; radiation effects; semiconductor device; modelling
Special Issues, Collections and Topics in MDPI journals
Prof. Dr. Ricardo Reis

E-Mail Website
Guest Editor
Instituto de Informática of the Universidade Federal do Rio Grande do Sul (UFRGS), Porto Alegre, Brazil
Interests: microelectronics; electronic design automation; physical design; VLSI design; design of circuits tolerant to radiation effects; systems on chip

Special Issue Information

Dear Colleagues,

One of the main challenges for the electronic research field is to cope with the rapidly progressing technology which, today, reaches the nanometer scale and ultra-low voltages. The areas of interest of this Special Issue include the modeling and design of innovative chips and embedded systems. Emerging technologies have raised relevant topics related to performances, power, and reliability that to need to be investigated.

The topics of this Special Issue are dedicated but not limited to the following:

System-on-a-chip;

multiprocessor systems;

network-on-a-chip;

low-voltage and low-power systems;

Internet of Things sensor;

analog–digital convertor/digital–analog converter;

clock network;

emerging type of memories;

CMOS image sensors

Dr. Laurent Artola
Prof. Dr. Ricardo Reis
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • Semiconductor Device
  • Innovative design
  • Simulation
  • Reliability
  • Low-power voltage

Published Papers (6 papers)

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Research

10 pages, 8663 KiB  
Article
A 3.7-to-10 GHz Low Phase Noise Wideband LC-VCO Array in 55-nm CMOS Technology
by Yan Yao, Zhiqun Li, Zhennan Li, Bofan Chen and Xiaowei Wang
Electronics 2022, 11(12), 1897; https://doi.org/10.3390/electronics11121897 - 16 Jun 2022
Viewed by 1929
Abstract
This paper presents a four-core LC-VCO array in 55 nm CMOS technology. Based on the multi-core VCO array technology and the switched capacitor array technology, the tuning range is expanded, and the phase noise optimization in a wide tuning range is achieved based [...] Read more.
This paper presents a four-core LC-VCO array in 55 nm CMOS technology. Based on the multi-core VCO array technology and the switched capacitor array technology, the tuning range is expanded, and the phase noise optimization in a wide tuning range is achieved based on the second harmonic noise filtering technology and the Q value degeneration technology, as well as the optimization of the capacitor array switching transistors. The proposed VCO array, occupying a chip area of 1.65 × 1.44 mm2, realizes a measured oscillation frequency range of about 3.7−10 GHz with phase noise of −127.5~−116.08 dBc/Hz at 1 MHz frequency offset, and achieves an output power of 2.69 dBm from a total power consumption of 52.8 mW. Full article
(This article belongs to the Special Issue Modeling and Design of Integrated CMOS Circuit)
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13 pages, 3824 KiB  
Article
A 125 KHz, Single-Stage, Dual-Output Wireless Power Receiver with PSM Modulation
by Shuaipeng Zhao, Xin Liu, Yingxi Wang and Yong An
Electronics 2022, 11(8), 1184; https://doi.org/10.3390/electronics11081184 - 08 Apr 2022
Viewed by 1491
Abstract
This paper presents a 125 KHz, single-stage, dual-output wireless power receiver with pulse skip modulation (PSM). Multi-output receivers are proposed to supply different modules in one system. Conventional multi-output receivers contain a rectifier and a multi-output regulator, which degrade the power conversion efficiency [...] Read more.
This paper presents a 125 KHz, single-stage, dual-output wireless power receiver with pulse skip modulation (PSM). Multi-output receivers are proposed to supply different modules in one system. Conventional multi-output receivers contain a rectifier and a multi-output regulator, which degrade the power conversion efficiency (PCE) due to interstage loss of the rectifier and the regulator. Additionally, existing single-inductor multi-output (SIMO) receivers exhibit a cross-regulation phenomenon because of the sharing inductor, which decreases the stability of the output voltages, and the use of an inductor in SIMO receivers increases the cost of the circuit. The proposed receiver in this article realizes rectification and regulation in only one stage, which eliminates interstage loss; this improves the power conversion efficiency of the system and realizes dual-output voltages with only four power transistors without an inductor, which reduces the chip area and minimizes cost. There is no cross-regulation in this dual-output architecture because the dual-output voltages are charged by different phases of the input signal. PSM modulation was adopted to regulate output voltages for higher efficiency. The proposed single-stage, dual-output regulating rectifier delivers a maximum power of 47 mW, and the dual-output voltages are 1.8 V and 2 V. This receiver is designed by a 0.18 μm complementary metal-oxide-semiconductor (CMOS) process and realizes a peak efficiency of 86% when the output power ranges from 15 mW to 47 mW. Full article
(This article belongs to the Special Issue Modeling and Design of Integrated CMOS Circuit)
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25 pages, 1914 KiB  
Article
Impact of Molecular Electrostatics on Field-Coupled Nanocomputing and Quantum-Dot Cellular Automata Circuits
by Yuri Ardesi, Giuliana Beretta, Marco Vacca, Gianluca Piccinini and Mariagrazia Graziano
Electronics 2022, 11(2), 276; https://doi.org/10.3390/electronics11020276 - 16 Jan 2022
Cited by 5 | Viewed by 2175
Abstract
The molecular Field-Coupled Nanocomputing (FCN) is a promising implementation of the Quantum-dot Cellular Automata (QCA) paradigm for future low-power digital electronics. However, most of the literature assumes all the QCA devices as possible molecular FCN devices, ignoring the molecular physics. Indeed, the electrostatic [...] Read more.
The molecular Field-Coupled Nanocomputing (FCN) is a promising implementation of the Quantum-dot Cellular Automata (QCA) paradigm for future low-power digital electronics. However, most of the literature assumes all the QCA devices as possible molecular FCN devices, ignoring the molecular physics. Indeed, the electrostatic molecular characteristics play a relevant role in the interaction and consequently influence the functioning of the circuits. In this work, by considering three reference molecular species, namely neutral, oxidized, and zwitterionic, we analyze the fundamental devices, aiming to clarify how molecule physics impacts architectural behavior. We thus examine through energy analysis the fundamental cell-to-cell interactions involved in the layouts. Additionally, we simulate a set of circuits using two available simulators: SCERPA and QCADesigner. In fact, ignoring the molecular characteristics and assuming the molecules copying the QCA behavior lead to controversial molecular circuit proposals. This work demonstrates the importance of considering the molecular type during the design process, thus declaring the simulators working scope and facilitating the assessment of molecular FCN as a possible candidate for future digital electronics. Full article
(This article belongs to the Special Issue Modeling and Design of Integrated CMOS Circuit)
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10 pages, 465 KiB  
Article
An Optimum Structure of Scalable Capacitors in 3D Crosspoint Memory Technology
by Yuya Tone and Toru Tanzawa
Electronics 2021, 10(22), 2755; https://doi.org/10.3390/electronics10222755 - 11 Nov 2021
Viewed by 1369
Abstract
Memory chips need large capacitors in their periphery to drive boosted word-lines and bit-lines for read and write operations. In a previous work, scalable capacitors were proposed for 3D crosspoint memory to keep the area for the capacitors constant over technology generations. This [...] Read more.
Memory chips need large capacitors in their periphery to drive boosted word-lines and bit-lines for read and write operations. In a previous work, scalable capacitors were proposed for 3D crosspoint memory to keep the area for the capacitors constant over technology generations. This paper proposes the capacitance models of three types of wiring capacitors: (1) vertical capacitor, (2) vertical and horizontal capacitor with next-neighbor wires connected with the other terminal, and (3) vertical and horizontal capacitor with next-neighbor pairs connected with the other terminal. These models are based on Wong’s crossover capacitor model to determine the capacitor structure with the highest capacitance density in 3D crosspoint memory technology. One can determine the best structure through optimizing the process parameters such as the height H of the insulation material between the metal wires and the thickness T of the metal wires and the design rules such as the width W and space S of metal wires. The model accuracy was in good agreement with the measurement of twelve types of capacitor structures fabricated in a 180 nm 6 metal standard CMOS process with the maximum error of 20%. Contour plots of the capacitance density across H vs. S where it is assumed that W = T = S are shown. As a result, the boundary condition regarding H and S is determined per 3D crosspoint memory technology with three, four, or five levels of wires. Full article
(This article belongs to the Special Issue Modeling and Design of Integrated CMOS Circuit)
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17 pages, 5399 KiB  
Article
Runtime Analysis of Area-Efficient Uniform RO-PUF for Uniqueness and Reliability Balancing
by Zulfikar Zulfikar, Norhayati Soin, Sharifah Fatmadiana Wan Muhamad Hatta and Mohamad Sofian Abu Talip
Electronics 2021, 10(20), 2504; https://doi.org/10.3390/electronics10202504 - 14 Oct 2021
Cited by 2 | Viewed by 1515
Abstract
The main issue of ring oscillator physical unclonable functions (RO-PUF) is the existence of unstable ROs in response to environmental variations. The RO pairs with close frequency differences tend to contribute bit flips, reducing the reliability. Research on improving reliability has been carried [...] Read more.
The main issue of ring oscillator physical unclonable functions (RO-PUF) is the existence of unstable ROs in response to environmental variations. The RO pairs with close frequency differences tend to contribute bit flips, reducing the reliability. Research on improving reliability has been carried out over the years. However, it has led to other issues, such as decreasing the uniqueness and increasing the area utilized. Therefore, this paper proposes a uniform RO-PUF, requiring a smaller area than a conventional design, aiming to balance reliability and uniqueness. We analyzed RO runtimes to increase reliability. In general, our method (uniqueness = 47.48%, reliability = 99.16%) performs better than previously proposed methods for a similar platform (Altera), and the reliability is as good as the latest methods using the same IC technology (28 nm). Moreover, the reliability is higher than that of RO-PUF with challenge and response pair (CRP) enhancements. The evaluation was performed in longer runtimes, where the pulses produced by ROs exceeded the counter capacity. This work recommends choosing ranges of the runtime of RO for better performance. For the 11-stage ROs, the range should be 1.598–4.30 ms, or 6.12–8.61 ms, or 12.24–12.91 ms. Meanwhile, for the 20-stage, the range should be 2.717–8.37 ms, or 10.97–16.74 ms, or 21.93–25.10 ms. Full article
(This article belongs to the Special Issue Modeling and Design of Integrated CMOS Circuit)
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12 pages, 1226 KiB  
Article
Pre-Emphasis Pulse Design for Random-Access Memory
by Yoshihiro Sugiura and Toru Tanzawa
Electronics 2021, 10(12), 1454; https://doi.org/10.3390/electronics10121454 - 17 Jun 2021
Cited by 1 | Viewed by 1675
Abstract
This paper describes how one can reduce the memory access time with pre-emphasis (PE) pulses even in non-volatile random-access memory. Optimum PE pulse widths and resultant minimum word-line (WL) delay times are investigated as a function of column address. The impact of the [...] Read more.
This paper describes how one can reduce the memory access time with pre-emphasis (PE) pulses even in non-volatile random-access memory. Optimum PE pulse widths and resultant minimum word-line (WL) delay times are investigated as a function of column address. The impact of the process variation in the time constant of WL, the cell current, and the resistance of deciding path on optimum PE pulses are discussed. Optimum PE pulse widths and resultant minimum WL delay times are modeled with fitting curves as a function of column address of the accessed memory cell, which provides designers with the ability to set the optimum timing for WL and BL (bit-line) operations, reducing average memory access time. Full article
(This article belongs to the Special Issue Modeling and Design of Integrated CMOS Circuit)
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