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Electronics
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Integrated Circuits for Systems on Chip and Systems in Package...
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Integrated Circuits for Systems on Chip and Systems in Package towards Advanced Industrial Applications

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Circuit and Signal Processing".

Deadline for manuscript submissions: closed (31 March 2023) | Viewed by 3157

Special Issue Editors

Dr. Ahmad Hassan

E-Mail Website
Guest Editor
The Edward S. Rogers Sr. Department of Electrical & Computer Engineering, University of Toronto, 10 King's College Rd., Toronto, ON M5S 3G8, Canada
Interests: analog and mixed signal integrated circuit design; harsh environments electronics; photonic based devices and circuits
Dr. Mohamed Ali

E-Mail Website
Guest Editor
Department of Electrical Engineering, Polytechnique Montreal, Montreal, QC H3T 1J4, Canada
Interests: microelectronics; RF transceivers
Dr. Ali Roshanghias

E-Mail Website
Guest Editor
Heterogeneous Integration Technologies, Silicon Austria Labs (SAL) GmbH, 9524 Villach, Austria
Interests: microelectronics packaging; wafer bonding; 3D integration; hybrid printed electronics; interconnections; die bonding materials; MEMS hermetic packaging; system in package; system in module; materials characterization
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

Dear Colleagues,

Nowadays, modern industrial applications are supported by an increasing number of sensors, actuators, and corresponding bulky electronic systems. Redundancy and lack of versatility motivate the advanced industries to look for solutions to miniaturize conventional electronic systems in order to reduce cost, size, weight and power (CoSWaP) by shrinking the size of components and making sensor systems more flexible. To attain this level of miniaturization and reconfigurability, system-on-chip (SoC) and system-in-package (SiP) are considered potential solutions. In parallel, with higher integration density, thermal coupling between adjacent chips becomes critical in addition to the self-heating effect of each chip, which results in performance degradation in the SiP. Therefore, to handle the thermal impact on the performance of SiP, a careful design of the packaging should be considered.

This Special Issue is to focus on the recent developments in reconfigurable and integrated circuits including the design, implementation and measurements of SoC and SiP for sensor interfaces and industrial applications. This includes (but is not limited to) high-voltage circuits (on-chip digital isolators, power amplifiers, level shifters …) and low-voltage circuits (data converters, read-back circuits, filters …). Research works based on advanced packaging solutions for SoC and SiP are welcomed for this Special Issue. Authors are invited to submit their latest research findings (including simulation and measurement results) for publication. Both regular articles and review papers are welcomed.

Dr. Ahmad Hassan
Dr. Mohamed Ali
Dr. Ali Roshanghias
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • system on chip
  • system in package
  • integrated system
  • sensor interface
  • high-voltage circuits
  • analog and mixed circuits
  • advanced packaging
  • on-chip thermal management

Published Papers (2 papers)

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Research

15 pages, 7308 KiB  
Article
A Fully Integrated 0.6 Gbps Data Communication System for Inductive-Based Digital Isolator with 0.8 ns Propagation Delay and 10−15 BER
by Isa Altoobaji, Ahmad Hassan, Mohamed Ali, Morteza Nabavi, Yves Audet and Ahmed Lakhssassi
Electronics 2023, 12(15), 3336; https://doi.org/10.3390/electronics12153336 - 04 Aug 2023
Viewed by 1251
Abstract
Digital isolators are implemented to protect low-voltage electronics and ensure human safety during high-voltage surge events. In this work, we present the design of an inductive-based digital isolation system that can sustain up to 1 kVrms breakdown voltage. The proposed system is [...] Read more.
Digital isolators are implemented to protect low-voltage electronics and ensure human safety during high-voltage surge events. In this work, we present the design of an inductive-based digital isolation system that can sustain up to 1 kVrms breakdown voltage. The proposed system is designed using the pulse polarity modulation scheme and fabricated in a 0.35 μm CMOS. Two identical dies are bounded within the IC package, with one die housing the transmitter (Tx) and the isolation transformer, while the other die contains the receiver (Rx). Two different customized designs between three metal layers are implemented to form the isolation element. The transformer’s secondary coil is constructed in metal-1, while the primary coil is formed in metal-2 and metal-3 for comparing the system functionality, isolation capability, and propagation delay. The functionality has been verified by measurements for an operating frequency of 300 MHz with a 2.6 ns propagation delay and an energy consumption of 8.15 × 103 pJ/bit at 1 Mbps. The chip was tested under extreme temperatures and achieved a maximum measured common mode transient immunity (CMTI) of 500 V/μs. Jitter has been examined to ensure fast transmission at a bit error rate (BER) of 10−15 with a total jitter (TJ) of 188.18 ps. Full article
(This article belongs to the Special Issue Integrated Circuits for Systems on Chip and Systems in Package towards Advanced Industrial Applications)
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10 pages, 2105 KiB  
Communication
SRAM Compilation and Placement Co-Optimization for Memory Subsystems
by Biwei Liu
Electronics 2023, 12(6), 1353; https://doi.org/10.3390/electronics12061353 - 12 Mar 2023
Viewed by 1424
Abstract
Co-optimization for memory bank compilation and placement was suggested as a way to improve performance and power and reduce the size of a memory subsystem. First, a multi-configuration SRAM compiler was realized that could generate memory banks with different PPA by splitting or [...] Read more.
Co-optimization for memory bank compilation and placement was suggested as a way to improve performance and power and reduce the size of a memory subsystem. First, a multi-configuration SRAM compiler was realized that could generate memory banks with different PPA by splitting or merging, upsizing or downsizing, threshold swapping, and aspect ratio deformation. Then, a timing margin estimation method was proposed for the memory bank based on placed positions. Through an exhaustive enumeration of various configuration parameters under the constraint of timing margins, the best SRAM memory compilation configuration was found. This method could be integrated into the existing physical design flow. The experimental results showed that this method achieved up to an 11.1% power reduction and a 7.6% critical path delay reduction compared with the traditional design method. Full article
(This article belongs to the Special Issue Integrated Circuits for Systems on Chip and Systems in Package towards Advanced Industrial Applications)
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