Interconnects for Electronics Packaging

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Microelectronics".

Deadline for manuscript submissions: closed (31 January 2023) | Viewed by 14318

Special Issue Editors

Heterogeneous Integration Technologies, Silicon Austria Labs (SAL) GmbH, 9524 Villach, Austria
Interests: microelectronics packaging; wafer bonding; 3D integration; hybrid printed electronics; interconnections; die bonding materials; MEMS hermetic packaging; system in package; system in module; materials characterization
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Hochschule für Technik und Wirtschaft Berlin, University of Applied Sciences, Treskowallee 8, 10318 Berlin, Germany
Interests: microsystems; piezoresistive sensor; sensor for harsh environments; SOI and SiC-based sensor; accelerometers; gas sensor; design and simulation of microsystems; graphene; material research; graphene-based sensors; biosensors; printed sensors; 2D sensors; technologies
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

Dear Colleagues,

Advanced heterogeneous integration as the key enabler of the “more than Moore” era demands disruptive interconnects technologies. These interconnects enable 3D integration, chip embedding, and enhanced thermal and electrical performances, which lead to device shrinkage, an increase in computing efficiency, superior switching speed, and power. The continued scaling of interconnects has faced cost, integration, thermal, and reliability challenges, which require innovations in terms of both technologies and materials. This Special Issue will cover the most advanced and emerging interconnects. A reliability analysis and failure analysis of the emerging interconnects will also be addressed here. We encourage original research works describing novel interconnecting technologies, materials and processes that can potentially lead to significant advances in the field of microelectronics packaging.

Dr. Ali Roshanghias
Prof. Dr. Ha Duong Ngo
Guest Editors

Manuscript Submission Information

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Keywords

  • 2.5 and 3D interconnects
  • interconnects for flexible and stretchable electronics
  • direct bond interconnects
  • nanomaterials as interconnect
  • wire-bondless packages
  • ultra-fine pitch interconnects
  • interconnects for D2D, D2W, and W2W bonding
  • additive manufactured interconnects and packages
  • sinter-based interconnects

Published Papers (4 papers)

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Research

19 pages, 7585 KiB  
Article
A True Process-Heterogeneous Stacked Embedded DRAM Structure Based on Wafer-Level Hybrid Bonding
by Song Wang, Xiping Jiang, Fujun Bai, Wenwu Xiao, Xiaodong Long, Qiwei Ren and Yi Kang
Electronics 2023, 12(5), 1077; https://doi.org/10.3390/electronics12051077 - 21 Feb 2023
Cited by 2 | Viewed by 4164
Abstract
In response to the increasing manufacturing complexity/cost in maintaining DRAM advancements through traditional scaling, three-dimensional integrated circuits (3D ICs) and 2.5-dimensional ICs with Si interposers are known as promising candidates to overcome these challenges due to their advantages of low power, small form [...] Read more.
In response to the increasing manufacturing complexity/cost in maintaining DRAM advancements through traditional scaling, three-dimensional integrated circuits (3D ICs) and 2.5-dimensional ICs with Si interposers are known as promising candidates to overcome these challenges due to their advantages of low power, small form factor, high density, and high bandwidth. In this work, we present a true process-heterogeneous stacked embedded DRAM (SeDRAM) using hybrid bonding 3D integration process, achieving high bandwidth of 34 GBps/Gbit and high energy efficiency of 0.88 pJ/bit. Moreover, the critical factors of the SeDRAM design are presented (e.g., the low data movement energy, high-density physical interface, simplified protocol definition, process compatibility, density extensibility, and hybrid bonding connection fast test by DFT (design for test). Our results and design methodology have paved the way to realize applications of hybrid bonding to high bandwidth and energy efficiency DRAM. More importantly, the SeDRAM solution can also support the maximum storage density of 48 Gbit and the bandwidth capability of TBps. It can greatly alleviate the “memory wall” problem and thus improve its competitiveness in near-memory computing/computing-in-memory fields. Full article
(This article belongs to the Special Issue Interconnects for Electronics Packaging)
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11 pages, 1227 KiB  
Article
Evaluating Cu Printed Interconnects “Sinterconnects” versus Wire Bonds for Switching Converters
by Md. Nazmul Hasan, Timothy Polom, Dominik Holzmann, Perla Malagó, Alfred Binder and Ali Roshanghias
Electronics 2022, 11(9), 1373; https://doi.org/10.3390/electronics11091373 - 25 Apr 2022
Cited by 1 | Viewed by 1916
Abstract
This paper demonstrates the feasibility of the printed copper (Cu) paste interconnects for applications in power semiconductor modules and switching converters. Copper sinter paste interconnects denoted as “Sinterconnects” have been recently introduced as an alternative to wire-bonding technology for power electronic device packaging. [...] Read more.
This paper demonstrates the feasibility of the printed copper (Cu) paste interconnects for applications in power semiconductor modules and switching converters. Copper sinter paste interconnects denoted as “Sinterconnects” have been recently introduced as an alternative to wire-bonding technology for power electronic device packaging. However, the electrical domain properties of these novel interconnects have not yet been investigated in detail. To address this research opportunity, this paper evaluates the performance of two different types of Sinterconnects applied to multi-chip, insulated gate bipolar transistor (IGBT) power modules. First, parasitic or stray inductances of these Sinterconnected systems are calculated analytically and by using three-dimensional finite element (FE) analysis. In addition to that, resistivity (ρ) of those has been analysed and compared with conventional wire bond technology. Finally, the performances of the Sinterconnects in power device assemblies are experimentally investigated. Two Sinterconnect structures (i.e., printed Cu paste and Cu clip attach) as well as a state-of-the-art wire-bonded IGBT module, have been integrated into a switching DC-DC converter and benchmarked. Experimental measurements show how converters with Sinterconnects enable efficient power conversion. Full article
(This article belongs to the Special Issue Interconnects for Electronics Packaging)
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13 pages, 3966 KiB  
Article
Die-Level Thinning for Flip-Chip Integration on Flexible Substrates
by Muhammad Hassan Malik, Andreas Tsiamis, Hubert Zangl, Alfred Binder, Srinjoy Mitra and Ali Roshanghias
Electronics 2022, 11(6), 849; https://doi.org/10.3390/electronics11060849 - 08 Mar 2022
Cited by 6 | Viewed by 5036
Abstract
Die-level thinning, handling, and integration of singulated dies from multi-project wafers (MPW) are often used in research, early-stage development, and prototyping of flexible devices. There is a high demand for thin silicon devices for several applications, such as flexible electronics. To address this [...] Read more.
Die-level thinning, handling, and integration of singulated dies from multi-project wafers (MPW) are often used in research, early-stage development, and prototyping of flexible devices. There is a high demand for thin silicon devices for several applications, such as flexible electronics. To address this demand, we study a novel post-processing method on two silicon devices, an electrochemical impedance sensor, and Complementary Metal Oxide Semiconductor (CMOS) die. Both are drawn from an MPW batch, thinned at die-level after dicing and singulation down to 60 µm. The thinned dies were flip-chip bonded to flexible substrates and hermetically sealed by two techniques: thermosonic bonding of Au stud bumps and anisotropic conductive paste (ACP) bonding. The performance of the thinned dies was assessed via functional tests and compared to the original dies. Furthermore, the long-term reliability of the flip-chip bonded thinned sensors was demonstrated to be higher than the conventional wire-bonded sensors. Full article
(This article belongs to the Special Issue Interconnects for Electronics Packaging)
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19 pages, 22399 KiB  
Article
Simulation of TSV Protrusion in 3DIC Integration by Directly Loading on Coarse-Grained Phase-Field Crystal Model
by Xiaoting Luo, Zhiheng Huang, Shuanjin Wang, Min Xiao, Yuezhong Meng, Hui Yan, Qizhuo Li and Gang Wang
Electronics 2022, 11(2), 221; https://doi.org/10.3390/electronics11020221 - 11 Jan 2022
Cited by 3 | Viewed by 1839
Abstract
As thermal management in 3DIC integration becomes increasingly important in advanced semiconductor node processes, novel experimental and modeling approaches are in great demand to reveal the critical material issues involving multiscale microstructures that govern the behavior of through-silicon-via (TSV) protrusion. Here, a coarse-grained [...] Read more.
As thermal management in 3DIC integration becomes increasingly important in advanced semiconductor node processes, novel experimental and modeling approaches are in great demand to reveal the critical material issues involving multiscale microstructures that govern the behavior of through-silicon-via (TSV) protrusion. Here, a coarse-grained phase-field crystal model properly coupled with mechanics through the atomic density field is used to simulate the formation of polycrystalline structures and protrusion of nano-TSVs from the atomic scale. TSVs with different grain structures are directly loaded, and protrusion/intrusion profiles are obtained along with displacement, stress, and strain fields. Thermodynamic driving forces from external loadings and the mismatch of Young’s modulus between adjoining grains as well as detailed displacement and strain distributions are ascribed to control the complex deformation in TSVs. TSVs with sizes up to around 30 nm and an aspect ratio of 4 are successfully investigated, and a further increase in the size and aspect ratio to cover the micrometer range is feasible, which lays down a solid basis toward a multiscale material database for simulation inputs to the design of TSV-based 3DIC integration and relevant electronic design automation (EDA) tools. Full article
(This article belongs to the Special Issue Interconnects for Electronics Packaging)
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