Research

12 pages, 3290 KiB

Open AccessArticle

Magnetron Sputter-Deposited β-Ga₂O₃ Films on c-Sapphire Substrate: Effect of Rapid Thermal Annealing Temperature on Crystalline Quality

by Sakal Pech, Sara Kim and Nam-Hoon Kim

Coatings 2022, 12(2), 140; https://doi.org/10.3390/coatings12020140 - 25 Jan 2022

Cited by 7 | Viewed by 3190

Abstract

Gallium oxide (Ga₂O₃) is a semiconductor with a wide bandgap of ~5.0 eV and large breakdown voltages (>8 MV·cm⁻¹). Among the crystal phases of Ga₂O₃, the monoclinic β-Ga₂O₃ is well [...] Read more.

Gallium oxide (Ga₂O₃) is a semiconductor with a wide bandgap of ~5.0 eV and large breakdown voltages (>8 MV·cm⁻¹). Among the crystal phases of Ga₂O₃, the monoclinic β-Ga₂O₃ is well known to be suitable for many device applications because of its chemical and thermal stability. The crystalline quality of polycrystalline β-Ga₂O₃ films on c-plane sapphire substrates was studied by rapid thermal annealing (RTA) following magnetron sputtering deposition at room temperature. Polycrystalline β-Ga₂O₃ films are relatively simple to prepare; however, their crystalline quality needs enhancement. The β-phase was achieved at 900 °C with a crystallite size and d-spacing of 26.02 and 0.2350 nm, respectively, when a mixture of ε- and β-phases was observed at temperatures up to 800 °C. The strain was released in the annealed Ga₂O₃ films at 900 °C; however, the clear and uniform orientation was not perfect because of the increased oxygen vacancy in the film at that temperature. The improved polycrystalline β-Ga₂O₃ films with dominant (−402)-oriented crystals were obtained at 900 °C for 45 min under a N₂ gas atmosphere. Full article

(This article belongs to the Special Issue Semiconductor Thin Films)

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13 pages, 2631 KiB

Open AccessArticle

Comparative Study of High-Temperature Annealed and RTA Process β-Ga₂O₃ Thin Film by Sol–Gel Process

by Min-Sung Bae, Seoung-Hyoun Kim, Jin-Su Baek and Jung-Hyuk Koh

Coatings 2021, 11(10), 1220; https://doi.org/10.3390/coatings11101220 - 05 Oct 2021

Cited by 10 | Viewed by 3214

Abstract

As a wide energy band gap semiconductor, a Ga₂O₃ thin film was prepared by the sol–gel process with different annealing processes. Since Ga₂O₃ is a type of metal oxide structure, an oxygen annealing process can be considered [...] Read more.

As a wide energy band gap semiconductor, a Ga₂O₃ thin film was prepared by the sol–gel process with different annealing processes. Since Ga₂O₃ is a type of metal oxide structure, an oxygen annealing process can be considered to remove oxygen defects. An effective oxygen annealing process can help form a β-Ga₂O₃ structure with reduced defects. In this study, different types of annealing effects for β-Ga₂O₃ were investigated and compared. An electric furnace process using thermal effect characteristics of and an Rapid Thermal Annealing (RTA) process applied with an infrared radiation light source were compared. Two and 4 h thermal annealing processes were conducted at 900 °C in the furnace. Meanwhile, to study the optical annealing effects, 2 h furnace at 900 °C + 15 min in rapid thermal annealing and only 15 min in rapid thermal annealing effects were compared, respectively. Through increasing the thermal annealing temperature and time, β-Ga₂O₃ can be formed even though a sol–gel process was employed in this experiment. An annealing temperature of at least 900 °C was required to form β-Ga₂O₃ thin film. Moreover, by introducing an RTA process just after the spinning process of thin film, a β-Ga₂O₃ thin film was formed on the sapphire substrates. Compared with the electric furnace process applied for 2 h, the RTA process performed in 15 min has a relatively short process time and results in similar structural and optical characteristics of a thin film. From the X-ray diffraction patterns and UV spectrometer analysis, optically annealed β-Ga₂O₃ thin films on the sapphire substrate showed a highly crystalized structure with a wide energy band gap of 4.8 eV. Full article

(This article belongs to the Special Issue Semiconductor Thin Films)

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9 pages, 29745 KiB

Open AccessFeature PaperArticle

Low-Temperature Epitaxial Growth of AlN Thin Films on a Mo Electrode/Sapphire Substrate Using Reactive Sputtering

by Jihong Kim

Coatings 2021, 11(4), 443; https://doi.org/10.3390/coatings11040443 - 12 Apr 2021

Cited by 7 | Viewed by 6292

Abstract

High-crystalline aluminum nitride (AlN) thin films are essential for device applications, and epitaxial growth is a promising approach to improve their crystalline quality. However, a high substrate temperature is usually required for the epitaxial growth, which is not compatible with the complementary metal-oxide-semiconductor [...] Read more.

High-crystalline aluminum nitride (AlN) thin films are essential for device applications, and epitaxial growth is a promising approach to improve their crystalline quality. However, a high substrate temperature is usually required for the epitaxial growth, which is not compatible with the complementary metal-oxide-semiconductor (CMOS) process. Furthermore, it is very difficult to obtain epitaxial AlN thin films on the deposited metal layers that are sometimes necessary for the bottom electrodes. In this work, epitaxial AlN thin films were successfully prepared on a molybdenum (Mo) electrode/sapphire substrate using reactive sputtering at a low substrate temperature. The structural properties, including the out-of-plane and in-plane relationships between the AlN thin film and the substrate, were investigated using X-ray diffraction (XRD) 2θ-ω, rocking curve, and pole figure scans. Additional analyses using scanning electron microscopy (SEM), atomic force microscopy (AFM), and transmission electron microscopy (TEM) were also carried out. It was shown that highly c-axis-oriented AlN thin films were grown epitaxially on the Mo/sapphire substrate with an in-plane relationship of AlN [11

\bar{2}

0]//sapphire [10

\bar{1}

0]. This epitaxial growth was attributed to the highly ordered and oriented Mo electrode layer grown on the sapphire substrate. In contrast, the AlN deposition on the Mo/SiO₂/Si substrate under the same conditions caused poorly oriented films with a polycrystalline structure. There coexisted two different low-crystalline phases of Mo (110) and Mo (211) in the Mo layer on the SiO₂/Si substrate, which led to the high mosaicity and polycrystalline structure of the AlN thin films. Full article

(This article belongs to the Special Issue Semiconductor Thin Films)

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9 pages, 5453 KiB

Open AccessArticle

Influence of Growth Temperature of the Nucleation Layer on the Growth of InP on Si (001)

by Shizheng Yang, Hongliang Lv, Likun Ai, Fangkun Tian, Silu Yan and Yuming Zhang

Coatings 2019, 9(12), 823; https://doi.org/10.3390/coatings9120823 - 04 Dec 2019

Cited by 3 | Viewed by 2590

Abstract

InP layers grown on Si (001) were achieved by the two-step growth method using gas source molecular beam epitaxy. The effects of growth temperature of nucleation layer on InP/Si epitaxial growth were investigated systematically. Cross-section morphology, surface morphology and crystal quality were characterized [...] Read more.

InP layers grown on Si (001) were achieved by the two-step growth method using gas source molecular beam epitaxy. The effects of growth temperature of nucleation layer on InP/Si epitaxial growth were investigated systematically. Cross-section morphology, surface morphology and crystal quality were characterized by scanning electron microscope images, atomic force microscopy images, high-resolution X-ray diffraction (XRD), rocking curves and reciprocal space maps. The InP/Si interface and surface became smoother and the XRD peak intensity was stronger with the nucleation layer grown at 350 °C. The Results show that the growth temperature of InP nucleation layer can significantly affect the growth process of InP film, and the optimal temperature of InP nucleation layer is required to realize a high-quality wafer-level InP layers on Si (001). Full article

(This article belongs to the Special Issue Semiconductor Thin Films)

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7 pages, 11010 KiB

Open AccessArticle

A Low Impact Ionization Rate Poly-Si TFT with a Current and Electric Field Split Design

by Feng-Tso Chien, Kuang-Po Hsueh, Zhen-Jie Hong, Kuan-Ting Lin, Yao-Tsung Tsai and Hsien-Chin Chiu

Coatings 2019, 9(8), 514; https://doi.org/10.3390/coatings9080514 - 13 Aug 2019

Cited by 3 | Viewed by 3749

Abstract

In this study, a novel low impact ionization rate (low-IIR) poly-Si thin film transistor featuring a current and electric field split (CES) structure with bottom field plate (BFP) and partial thicker channel raised source/drain (RSD) designs is proposed and demonstrated. The bottom field [...] Read more.

In this study, a novel low impact ionization rate (low-IIR) poly-Si thin film transistor featuring a current and electric field split (CES) structure with bottom field plate (BFP) and partial thicker channel raised source/drain (RSD) designs is proposed and demonstrated. The bottom field plate design can allure the electron and alter the electron current path to evade the high electric field area and therefore reduce the device IIR and suppress the kink effect. A two-dimensional device simulator was applied to describe and compare the current path, electric field magnitude distributions, and IIR of the proposed structure and conventional devices. In addition, the advantages of a partial thicker channel RSD design are present, and the leakage current of CES-thin-film transistor (TFT) can be reduced and the ON/OFF current ratio be improved, owing to a smaller drain electric field. Full article

(This article belongs to the Special Issue Semiconductor Thin Films)

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11 pages, 2516 KiB

Open AccessArticle

Growth of GaN Thin Film on Amorphous Glass Substrate by Direct-Current Pulse Sputtering Deposition Technique

by Wei-Sheng Liu, Yu-Lin Chang and Hui-Yu Chen

Coatings 2019, 9(7), 419; https://doi.org/10.3390/coatings9070419 - 30 Jun 2019

Cited by 8 | Viewed by 5888

Abstract

We deposited 300-nm-thick GaN films on an amorphous glass substrate at a substrate temperature of 300 °C by using pulsed direct current (DC) sputtering. A ZnO buffer layer was utilized to improve the crystalline quality of the GaN films. Scanning electron microscopy results [...] Read more.

We deposited 300-nm-thick GaN films on an amorphous glass substrate at a substrate temperature of 300 °C by using pulsed direct current (DC) sputtering. A ZnO buffer layer was utilized to improve the crystalline quality of the GaN films. Scanning electron microscopy results showed that the GaN thin films were grown along the c-axis and possessed a columnar structure. Atomic force microscopy results revealed that the GaN film deposited at a sputtering power of 75 W had the maximum grain size (24.1 nm). Room-temperature photoluminescence measurement of the GaN films indicated an ultraviolet near-band-edge emission at 365 nm and a Zn impurity energy transition level at 430 nm. In addition, X-ray diffraction conducted on the GaN films revealed a predominant (002) hexagonal wurtzite structure. The GaN film deposited at the sputtering power of 75 W demonstrated a high optical transmittance level of 88.5% in the wavelength range of 400–1100 nm. The material characteristics of the GaN films and ZnO buffer layer were studied using cross-sectional high-resolution transmission electron microscopy. The deposition of GaN films by using pulsed DC magnetron sputtering can result in high material quality and has high potential for realizing GaN-related optoelectronic devices on glass substrates. Full article

(This article belongs to the Special Issue Semiconductor Thin Films)

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8 pages, 1858 KiB

Open AccessArticle

Double-Sided Anti-Reflection Nanostructures on Optical Convex Lenses for Imaging Applications

by Hyuk Jae Jang, Yeong Jae Kim, Young Jin Yoo, Gil Ju Lee, Min Seok Kim, Ki Soo Chang and Young Min Song

Coatings 2019, 9(6), 404; https://doi.org/10.3390/coatings9060404 - 21 Jun 2019

Cited by 14 | Viewed by 6815

Abstract

Anti-reflection coatings (ARCs) from the cornea nipple array of the moth-eye remarkably suppress the Fresnel reflection at the interface in broadband wavelength ranges. ARCs on flat glass have been studied to enhance the optical transmittance. However, little research on the implementation of ARCs [...] Read more.

Anti-reflection coatings (ARCs) from the cornea nipple array of the moth-eye remarkably suppress the Fresnel reflection at the interface in broadband wavelength ranges. ARCs on flat glass have been studied to enhance the optical transmittance. However, little research on the implementation of ARCs on curved optical lenses, which are the core element in imaging devices, has been reported. Here, we report double-sided, bio-inspired ARCs on bi-convex lenses with high uniformity. We theoretically optimize the nanostructure geometry, such as the height, period, and morphology, since an anti-reflection property results from the gradually changed effective refractive index by the geometry of nanostructures. In an experiment, the transmittance of an ARCs lens increases up to 10% for a broadband spectrum without distortion in spot size and focal length. Moreover, we demonstrate ~30% improved transmittance of an imaging system composed of three bi-convex lenses, in series with double-sided ARCs (DARCs). Full article

(This article belongs to the Special Issue Semiconductor Thin Films)

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7 pages, 4330 KiB

Open AccessArticle

Double-Gate Two-Step Source/Drain Poly-Si Thin-Film Transistor

by Feng-Tso Chien, Chih-Ping Hung, Hsien-Chin Chiu, Tsung-Kuei Kang, Ching-Hwa Cheng and Yao-Tsung Tsai

Coatings 2019, 9(4), 233; https://doi.org/10.3390/coatings9040233 - 03 Apr 2019

Cited by 8 | Viewed by 4601

Abstract

A current improved and electric field reduced double-gate (DG) polycrystalline silicon thin-film transistor with two-step source/drain (DGTSD-TFT) design is proposed and demonstrated in this study. The two-step source/drain (TSD) design, which consists of a raised source/drain (RSD) area together with a partial gate [...] Read more.

A current improved and electric field reduced double-gate (DG) polycrystalline silicon thin-film transistor with two-step source/drain (DGTSD-TFT) design is proposed and demonstrated in this study. The two-step source/drain (TSD) design, which consists of a raised source/drain (RSD) area together with a partial gate overlapped lightly doped drain (P-GOLDD) structure, can lower the device drain electric field (DEF) to reveal a better device performance. Comparisons have been made with respect to a traditional single top gate (STG) device. The operation current of the proposed DGTSD-TFT is almost twice as large as that of the STG structure. The OFF-state leakage current and kink effect, as well as the ON/OFF current ratio for this double-gate and two-step source/drain structure, are also improved simultaneously because of a reduced DEF. A hot carrier stress test reveals that that two-step source/drain structure can achieve more stable device characteristics than the traditional device. Full article

(This article belongs to the Special Issue Semiconductor Thin Films)

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