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Novel Architectures and Applications for Artificial Intelligent and Internet of...
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Novel Architectures and Applications for Artificial Intelligent and Internet of Things Ecosystems

A special issue of Sensors (ISSN 1424-8220). This special issue belongs to the section "Internet of Things".

Deadline for manuscript submissions: closed (10 March 2023) | Viewed by 6456

Special Issue Editors

Dr. Mostafa Rahimi Azghadi

E-Mail Website
Guest Editor
College of Science & Engineering, James Cook University, Townsville City QLD 4814, Australia
Interests: neuromorphic engineering; spiking neural networks; memristors and memristive systems; very lage scale Integration (VLSI) design; embedded systems; quantum cellular automata
Dr. Kun-Chih Chen

E-Mail Website
Guest Editor
Department of Computer Science and Engineering, National Sun Yat-Sen University, Kaohsiung 80421, Taiwan
Interests: multiprocessor SoC (MPSoC) design; neural network learning algorithm design; reliable system design; VLSI/CAD design
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

Dear Colleagues,

Internet of Things (IoT) and big data applications drive Artificial Intelligence (AI) technology development. Devices for IoT applications provide sensing, actuation, processing, and communication at low-power levels and at low cost. Thus, they must be resilient in the face of harsh environments, challenging communication requirements, and long lifetimes that may reach beyond the useful lives of the individual nodes. This SI explores the design of novel circuits and systems for future architectures and applications of the IoT era.

Emerging IoT devices and applications produce increasingly high volumes of data. At the same time, they require significant computational requirements that often do not fit into the stringent power envelopes of existing IoT devices. In this SI, the emerging hierarchical IoT structure and its cross-layer collaboration schemes to sense and process massive data will be investigated.

The SI topics of interest include but are not limited to:

  • Energy-aware circuits and systems for IoT applications;
  • Circuits and systems for big data processing;
  • Sensory circuits and systems for the IoT;
  • Communications circuits and systems for the IoT.

Dr. Mostafa Rahimi Azghadi
Prof. Dr. Kun-Chih Chen
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Sensors is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2600 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • artificial Intelligence
  • internet of Things
  • DNN
  • SNN
  • sensory circuits

Published Papers (2 papers)

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Research

17 pages, 15762 KiB  
Article
Developing Edge AI Computer Vision for Smart Poultry Farms Using Deep Learning and HPC
by Stevan Cakic, Tomo Popovic, Srdjan Krco, Daliborka Nedic, Dejan Babic and Ivan Jovovic
Sensors 2023, 23(6), 3002; https://doi.org/10.3390/s23063002 - 10 Mar 2023
Cited by 5 | Viewed by 4394
Abstract
This research describes the use of high-performance computing (HPC) and deep learning to create prediction models that could be deployed on edge AI devices equipped with camera and installed in poultry farms. The main idea is to leverage an existing IoT farming platform [...] Read more.
This research describes the use of high-performance computing (HPC) and deep learning to create prediction models that could be deployed on edge AI devices equipped with camera and installed in poultry farms. The main idea is to leverage an existing IoT farming platform and use HPC offline to run deep learning to train the models for object detection and object segmentation, where the objects are chickens in images taken on farm. The models can be ported from HPC to edge AI devices to create a new type of computer vision kit to enhance the existing digital poultry farm platform. Such new sensors enable implementing functions such as counting chickens, detection of dead chickens, and even assessing their weight or detecting uneven growth. These functions combined with the monitoring of environmental parameters, could enable early disease detection and improve the decision-making process. The experiment focused on Faster R-CNN architectures and AutoML was used to identify the most suitable architecture for chicken detection and segmentation for the given dataset. For the selected architectures, further hyperparameter optimization was carried out and we achieved the accuracy of AP = 85%, AP50 = 98%, and AP75 = 96% for object detection and AP = 90%, AP50 = 98%, and AP75 = 96% for instance segmentation. These models were installed on edge AI devices and evaluated in the online mode on actual poultry farms. Initial results are promising, but further development of the dataset and improvements in prediction models is needed. Full article
(This article belongs to the Special Issue Novel Architectures and Applications for Artificial Intelligent and Internet of Things Ecosystems)
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25 pages, 2520 KiB  
Article
An ASIP for Neural Network Inference on Embedded Devices with 99% PE Utilization and 100% Memory Hidden under Low Silicon Cost
by Muxuan Gao, He Chen and Dake Liu
Sensors 2022, 22(10), 3841; https://doi.org/10.3390/s22103841 - 19 May 2022
Viewed by 1529
Abstract
The computation efficiency and flexibility of the accelerator hinder deep neural network (DNN) implementation in embedded applications. Although there are many publications on deep neural network (DNN) processors, there is still much room for deep optimization to further improve results. Multiple dimensions must [...] Read more.
The computation efficiency and flexibility of the accelerator hinder deep neural network (DNN) implementation in embedded applications. Although there are many publications on deep neural network (DNN) processors, there is still much room for deep optimization to further improve results. Multiple dimensions must be simultaneously considered when designing a DNN processor to reach the performance limit of the architecture, including architecture decision, flexibility, energy efficiency, and silicon cost minimization. Flexibility is defined as the ability to support as many multiple networks as possible and to easily adjust the scale. For energy efficiency, there are huge opportunities for power efficiency optimization, which involves access minimization and memory latency minimization based on on-chip memory minimization. Therefore, this work focused on low-power and low-latency data access with minimized silicon cost. This research was implemented based on an ASIP (application specific instruction set processor) in which an ISA was based on the caffe2 inference operator and the hardware design was based on a single instruction multiple data (SIMD) architecture. The scalability and system performance of our SoC extension scheme were demonstrated. The VLIW was used to execute multiple instructions in parallel. All costs for data access time were thus eliminated for the convolution layer. Finally, the processor was synthesized based on TSMC 65 nm technology with a 200 MHz clock, and the Soc extension scheme was analyzed in an experimental model. Our design was tested on several typical neural networks, achieving 196 GOPS at 200 MHz and 241 GOPS/W on the VGG16Net and AlexNet. Full article
(This article belongs to the Special Issue Novel Architectures and Applications for Artificial Intelligent and Internet of Things Ecosystems)
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