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18 pages, 6387 KiB

Open AccessArticle

Backdoor Attack on Deep Neural Networks Triggered by Fault Injection Attack on Image Sensor Interface

by Tatsuya Oyama, Shunsuke Okura, Kota Yoshida and Takeshi Fujino

Sensors 2023, 23(10), 4742; https://doi.org/10.3390/s23104742 - 14 May 2023

Cited by 1 | Viewed by 1159

A backdoor attack is a type of attack method that induces deep neural network (DNN) misclassification. The adversary who aims to trigger the backdoor attack inputs the image with a specific pattern (the adversarial mark) into the DNN model (backdoor model). In general, [...] Read more.

A backdoor attack is a type of attack method that induces deep neural network (DNN) misclassification. The adversary who aims to trigger the backdoor attack inputs the image with a specific pattern (the adversarial mark) into the DNN model (backdoor model). In general, the adversary mark is created on the physical object input to an image by capturing a photo. With this conventional method, the success of the backdoor attack is not stable because the size and position change depending on the shooting environment. So far, we have proposed a method of creating an adversarial mark for triggering backdoor attacks by means of a fault injection attack on the mobile industry processor interface (MIPI), which is the image sensor interface. We propose the image tampering model, with which the adversarial mark can be generated in the actual fault injection to create the adversarial mark pattern. Then, the backdoor model was trained with poison data images, which the proposed simulation model created. We conducted a backdoor attack experiment using a backdoor model trained on a dataset containing 5% poison data. The clean data accuracy in normal operation was 91%; nevertheless, the attack success rate with fault injection was 83%. Full article

(This article belongs to the Special Issue Computer Vision and Sensor Technology)

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11 pages, 2457 KiB

Open AccessCommunication

Single-Channel Blind Image Separation Based on Transformer-Guided GAN

by Yaya Su, Dongli Jia, Yankun Shen and Lin Wang

Sensors 2023, 23(10), 4638; https://doi.org/10.3390/s23104638 - 10 May 2023

Viewed by 1158

Abstract

Blind source separation (BSS) has been a great challenge in the field of signal processing due to the unknown distribution of the source signal and the mixing matrix. Traditional methods based on statistics and information theory use prior information such as source distribution [...] Read more.

Blind source separation (BSS) has been a great challenge in the field of signal processing due to the unknown distribution of the source signal and the mixing matrix. Traditional methods based on statistics and information theory use prior information such as source distribution independence, non-Gaussianity, sparsity, etc. to solve this problem. Generative adversarial networks (GANs) learn source distributions through games without being constrained by statistical properties. However, the current blind image separation methods based on GANs ignores the reconstruction of the structure and details of the separated image, resulting in residual interference source information in the generated results. This paper proposes a Transformer-guided GAN guided by an attention mechanism. Through the adversarial training of the generator and the discriminator, U-shaped Network (UNet) is used to fuse the convolutional layer features to reconstruct the structure of the separated image, and Transformer is used to calculate the position attention and guide the detailed information. We validate our method with quantitative experiments, showing that it outperforms previous blind image separation algorithms in terms of PSNR and SSIM. Full article

(This article belongs to the Special Issue Computer Vision and Sensor Technology)

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25 pages, 13179 KiB

Open AccessArticle

Automated Measurement of Geometric Features in Curvilinear Structures Exploiting Steger’s Algorithm

by Nicola Giulietti, Paolo Chiariotti and Gian Marco Revel

Sensors 2023, 23(8), 4023; https://doi.org/10.3390/s23084023 - 16 Apr 2023

Cited by 2 | Viewed by 1053

Abstract

Accurately assessing the geometric features of curvilinear structures on images is of paramount importance in many vision-based measurement systems targeting technological fields such as quality control, defect analysis, biomedical, aerial, and satellite imaging. This paper aims at laying the basis for the development [...] Read more.

Accurately assessing the geometric features of curvilinear structures on images is of paramount importance in many vision-based measurement systems targeting technological fields such as quality control, defect analysis, biomedical, aerial, and satellite imaging. This paper aims at laying the basis for the development of fully automated vision-based measurement systems targeting the measurement of elements that can be treated as curvilinear structures in the resulting image, such as cracks in concrete elements. In particular, the goal is to overcome the limitation of exploiting the well-known Steger’s ridge detection algorithm in these applications because of the manual identification of the input parameters characterizing the algorithm, which are preventing its extensive use in the measurement field. This paper proposes an approach to make the selection phase of these input parameters fully automated. The metrological performance of the proposed approach is discussed. The method is demonstrated on both synthesized and experimental data. Full article

(This article belongs to the Special Issue Computer Vision and Sensor Technology)

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24 pages, 4082 KiB

Open AccessArticle

Design and Analysis of Area and Energy Efficient Reconfigurable Cryptographic Accelerator for Securing IoT Devices

by Xvpeng Zhang, Bingqiang Liu, Yaqi Zhao, Xiaoyu Hu, Zixuan Shen, Zhaoxia Zheng, Zhenglin Liu, Kwen-Siong Chong, Guoyi Yu, Chao Wang and Xuecheng Zou

Sensors 2022, 22(23), 9160; https://doi.org/10.3390/s22239160 - 25 Nov 2022

Cited by 2 | Viewed by 1528

Abstract

Achieving low-cost and high-performance network security communication is necessary for Internet of Things (IoT) devices, including intelligent sensors and mobile robots. Designing hardware accelerators to accelerate multiple computationally intensive cryptographic primitives in various network security protocols is challenging. Different from existing unified reconfigurable [...] Read more.

Achieving low-cost and high-performance network security communication is necessary for Internet of Things (IoT) devices, including intelligent sensors and mobile robots. Designing hardware accelerators to accelerate multiple computationally intensive cryptographic primitives in various network security protocols is challenging. Different from existing unified reconfigurable cryptographic accelerators with relatively low efficiency and high latency, this paper presents design and analysis of a reconfigurable cryptographic accelerator consisting of a reconfigurable cipher unit and a reconfigurable hash unit to support widely used cryptographic algorithms for IoT Devices, which require block ciphers and hash functions simultaneously. Based on a detailed and comprehensive algorithmic analysis of both the block ciphers and hash functions in terms of basic algorithm structures and common cryptographic operators, the proposed reconfigurable cryptographic accelerator is designed by reusing key register files and operators to build unified data paths. Both the reconfigurable cipher unit and the reconfigurable hash unit contain a unified data path to implement Data Encryption Standard (DES)/Advanced Encryption Standard (AES)/ShangMi 4 (SM4) and Secure Hash Algorithm-1 (SHA-1)/SHA-256/SM3 algorithms, respectively. A reconfigurable S-Box for AES and SM4 is designed based on the composite field Galois field (GF) GF(((2²)²)²), which significantly reduces hardware overhead and power consumption compared with the conventional implementation by look-up tables. The experimental results based on 65-nm application-specific integrated circuit (ASIC) implementation show that the achieved energy efficiency and area efficiency of the proposed design is 441 Gbps/W and 37.55 Gbps/mm², respectively, which is suitable for IoT devices with limited battery and form factor. The result of delay analysis also shows that the number of delay cycles of our design can be reduced by 83% compared with the state-of-the-art design, which shows that the proposed design is more suitable for applications including 5G/Wi-Fi/ZigBee/Ethernet network standards to accelerate block ciphers and hash functions simultaneously. Full article

(This article belongs to the Special Issue Computer Vision and Sensor Technology)

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22 pages, 7274 KiB

Open AccessArticle

Efficient Hardware Accelerator Design of Non-Linear Optimization Correlative Scan Matching Algorithm in 2D LiDAR SLAM for Mobile Robots

by Ao Hu, Guoyi Yu, Qianjin Wang, Dongxiao Han, Shilun Zhao, Bingqiang Liu, Yu Yu, Yuwen Li, Chao Wang and Xuecheng Zou

Sensors 2022, 22(22), 8947; https://doi.org/10.3390/s22228947 - 18 Nov 2022

Cited by 5 | Viewed by 2079

Abstract

Simultaneous localization and mapping (SLAM) is the major solution for constructing or updating a map of an unknown environment while simultaneously keeping track of a mobile robot’s location. Correlative Scan Matching (CSM) is a scan matching algorithm for obtaining the posterior distribution probability [...] Read more.

Simultaneous localization and mapping (SLAM) is the major solution for constructing or updating a map of an unknown environment while simultaneously keeping track of a mobile robot’s location. Correlative Scan Matching (CSM) is a scan matching algorithm for obtaining the posterior distribution probability for the robot’s pose in SLAM. This paper combines the non-linear optimization algorithm and CSM algorithm into an NLO-CSM (Non-linear Optimization CSM) algorithm for reducing the computation resources and the amount of computation while ensuring high calculation accuracy, and it presents an efficient hardware accelerator design of the NLO-CSM algorithm for the scan matching in 2D LiDAR SLAM. The proposed NLO-CSM hardware accelerator utilizes pipeline processing and module reusing techniques to achieve low hardware overhead, fast matching, and high energy efficiency. FPGA implementation results show that, at 100 MHz clock, the power consumption of the proposed hardware accelerator is as low as 0.79 W, while it performs a scan match at 8.98 ms and 7.15 mJ per frame. The proposed design outperforms the ARM-A9 dual-core CPU implementation with a 92.74% increase and 90.71% saving in computing speed and energy consumption, respectively. It has also achieved 80.3% LUTs, 84.13% FFs, and 20.83% DSPs saving, as well as an 8.17× increase in frame rate and 96.22% improvement in energy efficiency over a state-of-the-art hardware accelerator design in the literature. ASIC implementation in 65 nm can further reduce the computing time and energy consumption per scan to 5.94 ms and 0.06 mJ, respectively, which shows that the proposed NLO-CSM hardware accelerator design is suitable for resource-limited and energy-constrained mobile and micro robot applications. Full article

(This article belongs to the Special Issue Computer Vision and Sensor Technology)

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17 pages, 6384 KiB

Open AccessArticle

Five-Direction Occlusion Filling with Five Layer Parallel Two-Stage Pipeline for Stereo Matching with Sub-Pixel Disparity Map Estimation

by Yunhao Ma, Xiwei Fang, Xinyu Guan, Ke Li, Lei Chen and Fengwei An

Sensors 2022, 22(22), 8605; https://doi.org/10.3390/s22228605 - 08 Nov 2022

Cited by 1 | Viewed by 1216

Abstract

Binocular stereoscopic matching is an essential method in computer vision, imitating human binocular technology to obtain distance information. Among plentiful stereo matching algorithms, Semi-Global Matching (SGM) is recognized as one of the most popular vision algorithms due to its relatively low power consumption [...] Read more.

Binocular stereoscopic matching is an essential method in computer vision, imitating human binocular technology to obtain distance information. Among plentiful stereo matching algorithms, Semi-Global Matching (SGM) is recognized as one of the most popular vision algorithms due to its relatively low power consumption and high accuracy, resulting in many excellent SGM-based hardware accelerators. However, vision algorithms, including SGM, are still somewhat inaccurate in actual long-range applications. Therefore, this paper proposes a disparity improvement strategy based on subpixel interpolation and disparity optimization post-processing using an area optimization strategy, hardware-friendly divider, split look-up table, and the clock alignment multi-directional disparity occlusion filling, and depth acquisition based on floating-point operations. The hardware architecture based on optimization algorithms is on the Stratix-IV platform. It consumes about 5.6 K LUTs, 12.8 K registers, and 2.5 M bits of on-chip memory. Meanwhile, the non-occlusion error rate of only 4.61% is about 1% better than the state-of-the-art works in the KITTI2015 dataset. The maximum working frequency can reach up to 98.28 MHz for the 640 × 480 resolution video and 128 disparity range with the power dissipation of 1.459 W and 320 frames per second processing speed. Full article

(This article belongs to the Special Issue Computer Vision and Sensor Technology)

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14 pages, 4563 KiB

Open AccessArticle

The mr-MDA: An Invariant to Shifting, Scaling, and Rotating Variance for 3D Object Recognition Using Diffractive Deep Neural Network

by Liang Zhou, Jiashuo Shi and Xinyu Zhang

Sensors 2022, 22(20), 7754; https://doi.org/10.3390/s22207754 - 12 Oct 2022

Viewed by 1645

Abstract

The diffractive deep neural network (D²NN) can efficiently accomplish 2D object recognition based on rapid optical manipulation. Moreover, the multiple-view D²NN array (MDA) possesses the obvious advantage of being able to effectively achieve 3D object classification. At present, 3D [...] Read more.

The diffractive deep neural network (D²NN) can efficiently accomplish 2D object recognition based on rapid optical manipulation. Moreover, the multiple-view D²NN array (MDA) possesses the obvious advantage of being able to effectively achieve 3D object classification. At present, 3D target recognition should be performed in a high-speed and dynamic way. It should be invariant to the typical shifting, scaling, and rotating variance of targets in relatively complicated circumstances, which remains a shortcoming of optical neural network architectures. In order to efficiently recognize 3D targets based on the developed D²NN, a more robust MDA (mr-MDA) is proposed in this paper. Through utilizing a new training strategy to tackle several random disturbances introduced into the optical neural network system, a trained mr-MDA model constructed by us was numerically verified, demonstrating that the training strategy is able to dynamically recognize 3D objects in a relatively stable way. Full article

(This article belongs to the Special Issue Computer Vision and Sensor Technology)

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17 pages, 3348 KiB

Open AccessArticle

A Reconfigurable Visual–Inertial Odometry Accelerated Core with High Area and Energy Efficiency for Autonomous Mobile Robots

by Yonghao Tan, Mengying Sun, Huanshihong Deng, Haihan Wu, Minghao Zhou, Yifei Chen, Zhuo Yu, Qinghan Zeng, Ping Li, Lei Chen and Fengwei An

Sensors 2022, 22(19), 7669; https://doi.org/10.3390/s22197669 - 09 Oct 2022

Cited by 1 | Viewed by 1958

Abstract

With the wide application of autonomous mobile robots (AMRs), the visual inertial odometer (VIO) system that realizes the positioning function through the integration of a camera and inertial measurement unit (IMU) has developed rapidly, but it is still limited by the high complexity [...] Read more.

With the wide application of autonomous mobile robots (AMRs), the visual inertial odometer (VIO) system that realizes the positioning function through the integration of a camera and inertial measurement unit (IMU) has developed rapidly, but it is still limited by the high complexity of the algorithm, the long development cycle of the dedicated accelerator, and the low power supply capacity of AMRs. This work designs a reconfigurable accelerated core that supports different VIO algorithms and has high area and energy efficiency, precision, and speed processing characteristics. Experimental results show that the loss of accuracy of the proposed accelerator is negligible on the most authoritative dataset. The on-chip memory usage of 70 KB is at least 10× smaller than the state-of-the-art works. Thus, the FPGA implementation’s hardware-resource consumption, power dissipation, and synthesis in the 28 nm CMOS outperform the previous works with the same platform. Full article

(This article belongs to the Special Issue Computer Vision and Sensor Technology)

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16 pages, 10113 KiB

Open AccessArticle

AdaSG: A Lightweight Feature Point Matching Method Using Adaptive Descriptor with GNN for VSLAM

by Ye Liu, Kun Huang, Jingyuan Li, Xiangting Li, Zeng Zeng, Liang Chang and Jun Zhou

Sensors 2022, 22(16), 5992; https://doi.org/10.3390/s22165992 - 11 Aug 2022

Viewed by 2324

Abstract

Feature point matching is a key component in visual simultaneous localization and mapping (VSLAM). Recently, the neural network has been employed in the feature point matching to improve matching performance. Among the state-of-the-art feature point matching methods, the SuperGlue is one of the [...] Read more.

Feature point matching is a key component in visual simultaneous localization and mapping (VSLAM). Recently, the neural network has been employed in the feature point matching to improve matching performance. Among the state-of-the-art feature point matching methods, the SuperGlue is one of the top methods and ranked the first in the CVPR 2020 workshop on image matching. However, this method utilizes graph neural network (GNN), resulting in large computational complexity, which makes it unsuitable for resource-constrained devices, such as robots and mobile phones. In this work, we propose a lightweight feature point matching method based on the SuperGlue (named as AdaSG). Compared to the SuperGlue, the AdaSG adaptively adjusts its operating architecture according to the similarity of input image pair to reduce the computational complexity while achieving high matching performance. The proposed method has been evaluated through the commonly used datasets, including indoor and outdoor environments. Compared with several state-of-the-art feature point matching methods, the proposed method achieves significantly less runtime (up to 43× for indoor and up to 6× for outdoor) with similar or better matching performance. It is suitable for feature point matching in resource constrained devices. Full article

(This article belongs to the Special Issue Computer Vision and Sensor Technology)

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