Silicon-Based Nanostructures: Fabrication and Characterization

A special issue of Nanomaterials (ISSN 2079-4991). This special issue belongs to the section "Nanoelectronics, Nanosensors and Devices".

Deadline for manuscript submissions: closed (20 November 2023) | Viewed by 15346

Special Issue Editors


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Guest Editor
1. Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China
2. Guangdong Greater Bay Area Institute of Integrated Circuit and System, R&D Center of Optoelectronic Hybrid IC, Building A, No. 136 Kaiyuan Avenue, Development Zone, Guangzhou, China
3. Department of Electronics Design, Mid Sweden University, Holmgatan 10, 85170 Sundsvall, Sweden
Interests: nanomaterials; nanoelectronics; nanophotonics; device processing; defects; strain engineering; CMOS; characterization; epitaxy; device physics; photodetectors; lasers; modulators; infrared; waveguides
Special Issues, Collections and Topics in MDPI journals

E-Mail Website
Guest Editor
1. Beijing Superstring Academy of Memory Technology, Beijing 100176, China
2. Guangdong Greater Bay Area Institute of Integrated Circuit and System, R&D Center of Optoelectronic Hybrid IC, Building A, No. 136 Kaiyuan Avenue, Development Zone, Guangzhou, China
Interests: nanomaterials; semiconductor processing and device physics; memory devices; thin-film deposition and epitaxy; material characterization; microelectronics; heterostructures; strain engineering; atomic layer deposition
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

Dear Colleagues,

Si-based nanostructures attracted widespread attention during recent years due to their low power consumption and fast operation in electronics and photonics, as well as high sensitivity in sensors applications. As an example, following Moore’s law, CMOSs have undergone an evolution in design and architecture in integrated circuits. The current technology developments drive the design of devices towards 3D integration, and as we approach the end of the era of Moore’s law, a greater number of nanostructures are fabricated for nanodevices. We also face an the emergence of electronics and photonics, where the fabrication and characterization of nanostructures are strongly required. These designs will be our ultimate goals in the field of nanotechnology in the future.  Therefore, this Special Issue focuses on the following scientific fields:

  • The fabrication and characterization of group IV nanostructures, nanodevices and nanosensors;
  • Carrier transport in nanostructures and nanomaterials;
  • Optoelectronic materials and nanodevices using Si-based heterostructures and nanostructures;
  • The integration of nanostructures in photonics and electronics;
  • Strain band-gap engineering in nanostructures;
  • The characterization of Si-based nanostructures;
  • Nanostructures for life sciences and biosensor applications;
  • Defect engineering in nanostructures.

This Special Issue will present unique knowledge to its readers regarding nano-scale physics, as well as the design, fabrication and characterization of nanostructures used in many scientific fields.

Prof. Dr. Henry H. Radamson
Prof. Dr. Guilei Wang
Guest Editors

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Keywords

  • nanomaterials
  • nanodevices
  • CMOS
  • device processing
  • nanosensors
  • nanophotonics
  • defects
  • characterization
  • strain

Published Papers (6 papers)

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Research

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13 pages, 6568 KiB  
Article
Investigation of Reducing Interface State Density in 4H-SiC by Increasing Oxidation Rate
by Shuai Li, Jun Luo and Tianchun Ye
Nanomaterials 2023, 13(9), 1568; https://doi.org/10.3390/nano13091568 - 06 May 2023
Cited by 1 | Viewed by 1436
Abstract
Detailed investigations of the pre-oxidation phosphorus implantation process are required to increase the oxidation rate in 4H-SiC metal-oxide-semiconductor (MOS) capacitors. This study focuses on the SiO2/SiC interface characteristics of pre-oxidation using phosphorus implantation methods. The inversion channel mobility of a metal-oxide-semiconductor [...] Read more.
Detailed investigations of the pre-oxidation phosphorus implantation process are required to increase the oxidation rate in 4H-SiC metal-oxide-semiconductor (MOS) capacitors. This study focuses on the SiO2/SiC interface characteristics of pre-oxidation using phosphorus implantation methods. The inversion channel mobility of a metal-oxide-semiconductor field effect transistor (MOSFET) was decreased via a high interface state density and the coulomb-scattering mechanisms of the carriers. High-resolution transmission electron microscopy (HRTEM) and scanning transmission electron microscopy (STEM) were used to evaluate the SiO2/SiC interface’s morphology. According to the energy-dispersive X-ray spectrometry (EDS) results, it was found that phosphorus implantation reduced the accumulation of carbon at the SiO2/SiC interface. Moreover, phosphorus distributed on the SiO2/SiC interface exhibited a Gaussian profile, and the nitrogen concentration at the SiO2/SiC interface may be correlated with the content of phosphorus. This research presents a new approach for increasing the oxidation rate of SiC and reducing the interface state density. Full article
(This article belongs to the Special Issue Silicon-Based Nanostructures: Fabrication and Characterization)
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10 pages, 9857 KiB  
Article
Design of a Capacitorless DRAM Based on a Polycrystalline-Silicon Dual-Gate MOSFET with a Fin-Shaped Structure
by Hee Dae An, Sang Ho Lee, Jin Park, So Ra Min, Geon Uk Kim, Young Jun Yoon, Jae Hwa Seo, Min Su Cho, Jaewon Jang, Jin-Hyuk Bae, Sin-Hyung Lee and In Man Kang
Nanomaterials 2022, 12(19), 3526; https://doi.org/10.3390/nano12193526 - 09 Oct 2022
Cited by 6 | Viewed by 2499
Abstract
In this study, a capacitorless one-transistor dynamic random-access memory (1T-DRAM) cell based on a polycrystalline silicon dual-gate metal-oxide-semiconductor field-effect transistor with a fin-shaped structure was optimized and analyzed using technology computer-aided design simulation. The proposed 1T-DRAM demonstrated improved memory characteristics owing to the [...] Read more.
In this study, a capacitorless one-transistor dynamic random-access memory (1T-DRAM) cell based on a polycrystalline silicon dual-gate metal-oxide-semiconductor field-effect transistor with a fin-shaped structure was optimized and analyzed using technology computer-aided design simulation. The proposed 1T-DRAM demonstrated improved memory characteristics owing to the adoption of the fin-shaped structure on the side of gate 2. This was because the holes generated during the program operation were collected on the side of gate 2, allowing an expansion of the area where the holes were stored using the fin-shaped structure. Therefore, compared with other previously reported 1T-DRAM structures, the fin-shaped structure has a relatively high retention time due to the increased hole storage area. The proposed 1T-DRAM cell exhibited a sensing margin of 2.51 μA/μm and retention time of 598 ms at T = 358 K. The proposed 1T-DRAM has high retention time and chip density, so there is a possibility that it will replace DRAM installed in various applications such as PCs, mobile phones, and servers in the future. Full article
(This article belongs to the Special Issue Silicon-Based Nanostructures: Fabrication and Characterization)
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15 pages, 4936 KiB  
Article
Monolithic Integration of O-Band InAs Quantum Dot Lasers with Engineered GaAs Virtual Substrate Based on Silicon
by Buqing Xu, Guilei Wang, Yong Du, Yuanhao Miao, Ben Li, Xuewei Zhao, Hongxiao Lin, Jiahan Yu, Jiale Su, Yan Dong, Tianchun Ye and Henry H. Radamson
Nanomaterials 2022, 12(15), 2704; https://doi.org/10.3390/nano12152704 - 05 Aug 2022
Cited by 11 | Viewed by 2021
Abstract
The realization of high-performance Si-based III-V quantum-dot (QD) lasers has long attracted extensive interest in optoelectronic circuits. This manuscript presents InAs/GaAs QD lasers integrated on an advanced GaAs virtual substrate. The GaAs layer was originally grown on Ge as another virtual substrate on [...] Read more.
The realization of high-performance Si-based III-V quantum-dot (QD) lasers has long attracted extensive interest in optoelectronic circuits. This manuscript presents InAs/GaAs QD lasers integrated on an advanced GaAs virtual substrate. The GaAs layer was originally grown on Ge as another virtual substrate on Si wafer. No patterned substrate or sophisticated superlattice defect-filtering layer was involved. Thanks to the improved quality of the comprehensively modified GaAs crystal with low defect density, the room temperature emission wavelength of this laser was allocated at 1320 nm, with a threshold current density of 24.4 A/cm−2 per layer and a maximum single-facet output power reaching 153 mW at 10 °C. The maximum operation temperature reaches 80 °C. This work provides a feasible and promising proposal for the integration of an efficient O-band laser with a standard Si platform in the near future. Full article
(This article belongs to the Special Issue Silicon-Based Nanostructures: Fabrication and Characterization)
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17 pages, 4224 KiB  
Article
Investigation of the Integration of Strained Ge Channel with Si-Based FinFETs
by Buqing Xu, Guilei Wang, Yong Du, Yuanhao Miao, Yuanyuan Wu, Zhenzhen Kong, Jiale Su, Ben Li, Jiahan Yu and Henry H. Radamson
Nanomaterials 2022, 12(9), 1403; https://doi.org/10.3390/nano12091403 - 19 Apr 2022
Viewed by 2071
Abstract
In this manuscript, the integration of a strained Ge channel with Si-based FinFETs was investigated. The main focus was the preparation of high-aspect-ratio (AR) fin structures, appropriate etching topography and the growth of germanium (Ge) as a channel material with a highly compressive [...] Read more.
In this manuscript, the integration of a strained Ge channel with Si-based FinFETs was investigated. The main focus was the preparation of high-aspect-ratio (AR) fin structures, appropriate etching topography and the growth of germanium (Ge) as a channel material with a highly compressive strain. Two etching methods, the wet etching and in situ HCl dry etching methods, were studied to achieve a better etching topography. In addition, the selective epitaxial growth of Ge material was performed on a patterned substrate using reduced pressure chemical vapor deposition. The results show that a V-shaped structure formed at the bottom of the dummy Si-fins using the wet etching method, which is beneficial to the suppression of dislocations. In addition, compressive strain was introduced to the Ge channel after the Ge selective epitaxial growth, which benefits the pMOS transport characteristics. The pattern dependency of the Ge growth over the patterned wafer was measured, and the solutions for uniform epitaxy are discussed. Full article
(This article belongs to the Special Issue Silicon-Based Nanostructures: Fabrication and Characterization)
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15 pages, 9577 KiB  
Article
Growth and Strain Modulation of GeSn Alloys for Photonic and Electronic Applications
by Zhenzhen Kong, Guilei Wang, Renrong Liang, Jiale Su, Meng Xun, Yuanhao Miao, Shihai Gu, Junjie Li, Kaihua Cao, Hongxiao Lin, Ben Li, Yuhui Ren, Junfeng Li, Jun Xu and Henry H. Radamson
Nanomaterials 2022, 12(6), 981; https://doi.org/10.3390/nano12060981 - 16 Mar 2022
Cited by 17 | Viewed by 2882
Abstract
GeSn materials have attracted considerable attention for their tunable band structures and high carrier mobilities, which serve well for future photonic and electronic applications. This research presents a novel method to incorporate Sn content as high as 18% into GeSn layers grown at [...] Read more.
GeSn materials have attracted considerable attention for their tunable band structures and high carrier mobilities, which serve well for future photonic and electronic applications. This research presents a novel method to incorporate Sn content as high as 18% into GeSn layers grown at 285–320 °C by using SnCl4 and GeH4 precursors. A series of characterizations were performed to study the material quality, strain, surface roughness, and optical properties of GeSn layers. The Sn content could be calculated using lattice mismatch parameters provided by X-ray analysis. The strain in GeSn layers was modulated from fully strained to partially strained by etching Ge buffer into Ge/GeSn heterostructures . In this study, two categories of samples were prepared when the Ge buffer was either laterally etched onto Si wafers, or vertically etched Ge/GeSnOI wafers which bonded to the oxide. In the latter case, the Ge buffer was initially etched step-by-step for the strain relaxation study. Meanwhile, the Ge/GeSn heterostructure in the first group of samples was patterned into the form of micro-disks. The Ge buffer was selectively etched by using a CF4/O2 gas mixture using a plasma etch tool. Fully or partially relaxed GeSn micro-disks showed photoluminescence (PL) at room temperature. PL results showed that red-shift was clearly observed from the GeSn micro-disk structure, indicating that the compressive strain in the as-grown GeSn material was partially released. Our results pave the path for the growth of high quality GeSn layers with high Sn content, in addition to methods for modulating the strain for lasing and detection of short-wavelength infrared at room temperature. Full article
(This article belongs to the Special Issue Silicon-Based Nanostructures: Fabrication and Characterization)
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Review

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53 pages, 20150 KiB  
Review
Review of Ge(GeSn) and InGaAs Avalanche Diodes Operating in the SWIR Spectral Region
by Yuanhao Miao, Hongxiao Lin, Ben Li, Tianyu Dong, Chuangqi He, Junhao Du, Xuewei Zhao, Ziwei Zhou, Jiale Su, He Wang, Yan Dong, Bin Lu, Linpeng Dong and Henry H. Radamson
Nanomaterials 2023, 13(3), 606; https://doi.org/10.3390/nano13030606 - 02 Feb 2023
Cited by 9 | Viewed by 3581
Abstract
Among photodetectors, avalanche photodiodes (APDs) have an important place due to their excellent sensitivity to light. APDs transform photons into electrons and then multiply the electrons, leading to an amplified photocurrent. APDs are promising for faint light detection owing to this outstanding advantage, [...] Read more.
Among photodetectors, avalanche photodiodes (APDs) have an important place due to their excellent sensitivity to light. APDs transform photons into electrons and then multiply the electrons, leading to an amplified photocurrent. APDs are promising for faint light detection owing to this outstanding advantage, which will boost LiDAR applications. Although Si APDs have already been commercialized, their spectral region is very limited in many applications. Therefore, it is urgently demanded that the spectral region APDs be extended to the short-wavelength infrared (SWIR) region, which means better atmospheric transmission, a lower solar radiation background, a higher laser eye safety threshold, etc. Up until now, both Ge (GeSn) and InGaAs were employed as the SWIR absorbers. The aim of this review article is to provide a full understanding of Ge(GeSn) and InGaAs for PDs, with a focus on APD operation in the SWIR spectral region, which can be integrated onto the Si platform and is potentially compatible with CMOS technology. Full article
(This article belongs to the Special Issue Silicon-Based Nanostructures: Fabrication and Characterization)
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