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Memory Nanomaterials: Growth, Characterization and Device Fabrication
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Memory Nanomaterials: Growth, Characterization and Device Fabrication

A special issue of Nanomaterials (ISSN 2079-4991). This special issue belongs to the section "Nanoelectronics, Nanosensors and Devices".

Deadline for manuscript submissions: closed (30 September 2023) | Viewed by 17783

Special Issue Editors

Prof. Dr. Chao Zhao

E-Mail Website
Guest Editor
1. Beijing Superstring Academy of Memory Technology, Beijing 100176, China
2. School of Integrated Circuit Science and Engineering, Beihang University, Beijing 100191, China
Interests: nanomaterials; CMOS and DRAM processing and device physics; memory devices; atomic layer deposition; thin-film deposition; material characterization; microelectronics
Prof. Dr. Guilei Wang

E-Mail Website
Guest Editor
1. Beijing Superstring Academy of Memory Technology, Beijing 100176, China
2. Guangdong Greater Bay Area Institute of Integrated Circuit and System, R&D Center of Optoelectronic Hybrid IC, Building A, No. 136 Kaiyuan Avenue, Development Zone, Guangzhou, China
Interests: nanomaterials; semiconductor processing and device physics; memory devices; thin-film deposition and epitaxy; material characterization; microelectronics; heterostructures; strain engineering; atomic layer deposition
Special Issues, Collections and Topics in MDPI journals
Dr. Huihui Li

E-Mail Website
Guest Editor Assistant
Beijing Superstring Academy of Memory Technology, Beijing 100176, China
Interests: nanomaterials; information storage; semiconductor memory; semiconductor process and integration; magnetic recording; magnetic characterization; material characterization; electron imaging; magnetic sensor

Special Issue Information

Dear Colleagues,

The traditional semiconductor technology has gradually approached the physical limit, which makes it difficult to greatly improve the storage efficiency, reservoir performance. In order to make breakthrough progress, we must turn to innovative methods, find new principles, new materials, and new structures. At present, some emerging storage technologies for the 21st century are being studied and developed. The new materials and nanostructures that should be applied have brought hope for future information storage technology. Therefore, this Special Issue focuses on the following scientific fields:

  • Si-based heterostructures and nanostructures in DRAM;
  • Strained silicon materials in DRAM peripheral circuits;
  • The process and integration of nanostructures in DRAM;
  • Supercapacitor high-k materials for DRAM;
  • Growth and Characterization of IGZO material;
  • New materials in emerging DRAM architecture (2T0C, 2T1C…);
  • RRAM materials and devices;
  • MRAM materials and devices (STT-MRAM, SOT-MRAM, VCMA-MRAM, etc.);
  • FRAM materials and devices;
  • PCM materials and devices;
  • Reliability analysis and characterization of Memory;
  • Characterization of memory nanostructures;
  • Materials calculation and device simulation;
  • Logic-Memory 3D integration;
  • Emerging memory applications;

This Special Issue will provide unique knowledge on advanced memory in the materials growth, fabrication, and characterization of nanostructures applied in many fields.

Prof. Dr. Chao Zhao
Prof. Dr. Guilei Wang
Guest Editors

Dr. Huihui Li
Guest Editor Assistant

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Nanomaterials is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2900 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • memory nanomaterials
  • memory devices
  • DRAM processing
  • characterization
  • reliability
  • emerging memory

Published Papers (11 papers)

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Research

12 pages, 4547 KiB  
Article
Study of Selective Dry Etching Effects of 15-Cycle Si0.7Ge0.3/Si Multilayer Structure in Gate-All-Around Transistor Process
by Enxu Liu, Junjie Li, Na Zhou, Rui Chen, Hua Shao, Jianfeng Gao, Qingzhu Zhang, Zhenzhen Kong, Hongxiao Lin, Chenchen Zhang, Panpan Lai, Chaoran Yang, Yang Liu, Guilei Wang, Chao Zhao, Tao Yang, Huaxiang Yin, Junfeng Li, Jun Luo and Wenwu Wang
Nanomaterials 2023, 13(14), 2127; https://doi.org/10.3390/nano13142127 - 21 Jul 2023
Viewed by 1874
Abstract
Gate-all-around (GAA) structures are important for future logic devices and 3D-DRAM. Inner-spacer cavity etching and channel release both require selective etching of Si0.7Ge0.3. Increasing the number of channel-stacking layers is an effective way to improve device current-driving capability and [...] Read more.
Gate-all-around (GAA) structures are important for future logic devices and 3D-DRAM. Inner-spacer cavity etching and channel release both require selective etching of Si0.7Ge0.3. Increasing the number of channel-stacking layers is an effective way to improve device current-driving capability and storage density. Previous work investigated ICP selective etching of a three-cycle Si0.7Ge0.3/Si multilayer structure and the related etching effects. This study focuses on the dry etching of a 15-cycle Si0.7Ge0.3/Si multilayer structure and the associated etching effects, using simulation and experimentation. The simulation predicts the random effect of lateral etching depth and the asymmetric effect of silicon nanosheet damage on the edge, both of which are verified by experiments. Furthermore, the study experimentally investigates the influence and mechanism of pressure, power, and other parameters on the etching results. Research on these etching effects and mechanisms will provide important points of reference for the dry selective etching of Si0.7Ge0.3 in GAA structures. Full article
(This article belongs to the Special Issue Memory Nanomaterials: Growth, Characterization and Device Fabrication)
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9 pages, 2887 KiB  
Communication
Comprehensive Investigation of Constant Voltage Stress Time-Dependent Breakdown and Cycle-to-Breakdown Reliability in Y-Doped and Si-Doped HfO2 Metal-Ferroelectric-Metal Memory
by Ting-Yu Chang, Kuan-Chi Wang, Hsien-Yang Liu, Jing-Hua Hseun, Wei-Cheng Peng, Nicolò Ronchi, Umberto Celano, Kaustuv Banerjee, Jan Van Houdt and Tian-Li Wu
Nanomaterials 2023, 13(14), 2104; https://doi.org/10.3390/nano13142104 - 19 Jul 2023
Viewed by 915
Abstract
In this study, we comprehensively investigate the constant voltage stress (CVS) time-dependent breakdown and cycle-to-breakdown while considering metal-ferroelectric-metal (MFM) memory, which has distinct domain sizes induced by different doping species, i.e., Yttrium (Y) (Sample A) and Silicon (Si) (Sample B). Firstly, Y-doped and [...] Read more.
In this study, we comprehensively investigate the constant voltage stress (CVS) time-dependent breakdown and cycle-to-breakdown while considering metal-ferroelectric-metal (MFM) memory, which has distinct domain sizes induced by different doping species, i.e., Yttrium (Y) (Sample A) and Silicon (Si) (Sample B). Firstly, Y-doped and Si-doped HfO2 MFM devices exhibit domain sizes of 5.64 nm and 12.47 nm, respectively. Secondly, Si-doped HfO2 MFM devices (Sample B) have better CVS time-dependent breakdown and cycle-to-breakdown stability than Y-doped HfO2 MFM devices (Sample A). Therefore, a larger domain size showing higher extrapolated voltage under CVS time-dependent breakdown and cycle-to-breakdown evaluations was observed, indicating that the domain size crucially impacts the stability of MFM memory. Full article
(This article belongs to the Special Issue Memory Nanomaterials: Growth, Characterization and Device Fabrication)
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13 pages, 10307 KiB  
Article
High-Quality Recrystallization of Amorphous Silicon on Si (100) Induced via Laser Annealing at the Nanoscale
by Zhuo Chen, Huilong Zhu, Guilei Wang, Qi Wang, Zhongrui Xiao, Yongkui Zhang, Jinbiao Liu, Shunshun Lu, Yong Du, Jiahan Yu, Wenjuan Xiong, Zhenzhen Kong, Anyan Du, Zijin Yan and Yantong Zheng
Nanomaterials 2023, 13(12), 1867; https://doi.org/10.3390/nano13121867 - 15 Jun 2023
Viewed by 1406
Abstract
At sub-3 nm nodes, the scaling of lateral devices represented by a fin field-effect transistor (FinFET) and gate-all-around field effect transistors (GAAFET) faces increasing technical challenges. At the same time, the development of vertical devices in the three-dimensional direction has excellent potential for [...] Read more.
At sub-3 nm nodes, the scaling of lateral devices represented by a fin field-effect transistor (FinFET) and gate-all-around field effect transistors (GAAFET) faces increasing technical challenges. At the same time, the development of vertical devices in the three-dimensional direction has excellent potential for scaling. However, existing vertical devices face two technical challenges: “self-alignment of gate and channel” and “precise gate length control”. A recrystallization-based vertical C-shaped-channel nanosheet field effect transistor (RC-VCNFET) was proposed, and related process modules were developed. The vertical nanosheet with an “exposed top” structure was successfully fabricated. Moreover, through physical characterization methods such as scanning electron microscopy (SEM), atomic force microscopy (AFM), conductive atomic force microscopy (C-AFM) and transmission electron microscopy (TEM), the influencing factors of the crystal structure of the vertical nanosheet were analyzed. This lays the foundation for fabricating high-performance and low-cost RC-VCNFETs devices in the future. Full article
(This article belongs to the Special Issue Memory Nanomaterials: Growth, Characterization and Device Fabrication)
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10 pages, 5813 KiB  
Article
Investigation on Recrystallization Channel for Vertical C-Shaped-Channel Nanosheet FETs by Laser Annealing
by Zhuo Chen, Huilong Zhu, Guilei Wang, Qi Wang, Zhongrui Xiao, Yongkui Zhang, Jinbiao Liu, Shunshun Lu, Yong Du, Jiahan Yu, Wenjuan Xiong, Zhenzhen Kong, Anyan Du, Zijin Yan and Yantong Zheng
Nanomaterials 2023, 13(11), 1786; https://doi.org/10.3390/nano13111786 - 01 Jun 2023
Viewed by 1165
Abstract
Transistor scaling has become increasingly difficult in the dynamic random access memory (DRAM). However, vertical devices will be good candidates for 4F2 DRAM cell transistors (F = pitch/2). Most vertical devices are facing some technical challenges. For example, the gate length cannot [...] Read more.
Transistor scaling has become increasingly difficult in the dynamic random access memory (DRAM). However, vertical devices will be good candidates for 4F2 DRAM cell transistors (F = pitch/2). Most vertical devices are facing some technical challenges. For example, the gate length cannot be precisely controlled, and the gate and the source/drain of the device cannot be aligned. Recrystallization-based vertical C-shaped-channel nanosheet field-effect transistors (RC-VCNFETs) were fabricated. The critical process modules of the RC-VCNFETs were developed as well. The RC-VCNFET with a self-aligned gate structure has excellent device performance, and its subthreshold swing (SS) is 62.91 mV/dec. Drain-induced barrier lowering (DIBL) is 6.16 mV/V. Full article
(This article belongs to the Special Issue Memory Nanomaterials: Growth, Characterization and Device Fabrication)
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10 pages, 2877 KiB  
Article
Improved Endurance of Ferroelectric Hf0.5Zr0.5O2 Using Laminated-Structure Interlayer
by Meiwen Chen, Shuxian Lv, Boping Wang, Pengfei Jiang, Yuanxiang Chen, Yaxin Ding, Yuan Wang, Yuting Chen and Yan Wang
Nanomaterials 2023, 13(10), 1608; https://doi.org/10.3390/nano13101608 - 11 May 2023
Viewed by 1771
Abstract
In this article, the endurance characteristic of the TiN/HZO/TiN capacitor was improved by the laminated structure of a ferroelectric Hf0.5Zr0.5O2 thin film. Altering the HZO deposition ratio, the laminated-structure interlayer was formed in the middle of the HZO [...] Read more.
In this article, the endurance characteristic of the TiN/HZO/TiN capacitor was improved by the laminated structure of a ferroelectric Hf0.5Zr0.5O2 thin film. Altering the HZO deposition ratio, the laminated-structure interlayer was formed in the middle of the HZO film. Although small remanent polarization reduction was observed in the capacitor with a laminated structure, the endurance characteristic was improved by two orders of magnitude (from 106 to 108 cycles). Moreover, the leakage current of the TiN/HZO/TiN capacitor with the laminated-structure interlayer was reduced by one order of magnitude. The reliability enhancement was proved by the Time-Dependent Dielectric Breakdown (TDDB) test, and the optimization results were attributed to the migration inhibition and nonuniform distribution of oxygen vacancies. Without additional materials and a complicated process, the laminated-structure method provides a feasible strategy for improving HZO device reliability. Full article
(This article belongs to the Special Issue Memory Nanomaterials: Growth, Characterization and Device Fabrication)
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12 pages, 4536 KiB  
Article
Insight into over Repair of Hot Carrier Degradation by GIDL Current in Si p-FinFETs Using Ultra-Fast Measurement Technique
by Hao Chang, Guilei Wang, Hong Yang, Qianqian Liu, Longda Zhou, Zhigang Ji, Ruixi Yu, Zhenhua Wu, Huaxiang Yin, Anyan Du, Junfeng Li, Jun Luo, Chao Zhao and Wenwu Wang
Nanomaterials 2023, 13(7), 1259; https://doi.org/10.3390/nano13071259 - 03 Apr 2023
Viewed by 1547
Abstract
In this article, an experimental study on the gate-induced drain leakage (GIDL) current repairing worst hot carrier degradation (HCD) in Si p-FinFETs is investigated with the aid of an ultra-fast measurement (UFM) technique (~30 μs). It is found that increasing GIDL bias from [...] Read more.
In this article, an experimental study on the gate-induced drain leakage (GIDL) current repairing worst hot carrier degradation (HCD) in Si p-FinFETs is investigated with the aid of an ultra-fast measurement (UFM) technique (~30 μs). It is found that increasing GIDL bias from 3 V to 4 V achieves a 114.7% VT recovery ratio from HCD. This over-repair phenomenon of HCD by UFM GIDL is deeply discussed through oxide trap behaviors. When the applied gate-to-drain GIDL bias reaches 4 V, a significant electron trapping and interface trap generation of the fresh device with GIDL repair is observed, which greatly contributes to the approximate 114.7% over-repair VT ratio of the device under worst HCD stress (−2.0 V, 200 s). Based on the TCAD simulation results, the increase in the vertical electric field on the surface of the channel oxide layer is the direct cause of an extraordinary electron trapping effect accompanied by the over-repair phenomenon. Under a high positive electric field, a part of channel electrons is captured by oxide traps in the gate dielectric, leading to further VT recovery. Through the discharge-based multi-pulse (DMP) technique, the energy distribution of oxide traps after GIDL recovery is obtained. It is found that over-repair results in a 34% increment in oxide traps around the conduction energy band (Ec) of silicon, which corresponds to a higher stabilized VT shift under multi-cycle HCD-GIDL tests. The results provide a trap-based understanding of the transistor repairing technique, which could provide guidance for the reliable long-term operation of ICs. Full article
(This article belongs to the Special Issue Memory Nanomaterials: Growth, Characterization and Device Fabrication)
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11 pages, 2428 KiB  
Article
Comparative Study of Temperature Impact in Spin-Torque Switched Perpendicular and Easy-Cone MTJs
by Jingwei Long, Qi Hu, Zhengping Yuan, Yunsen Zhang, Yue Xin, Jie Ren, Bowen Dong, Gengfei Li, Yumeng Yang, Huihui Li and Zhifeng Zhu
Nanomaterials 2023, 13(2), 337; https://doi.org/10.3390/nano13020337 - 13 Jan 2023
Cited by 1 | Viewed by 1630
Abstract
The writing performance of the easy-cone magnetic tunnel junction (MTJ) and perpendicularly magnetized MTJ (pMTJ) under various temperatures was investigated based on the macrospin model. When the temperature is changed from 273 K to 373 K, the switching current density of the pMTJ [...] Read more.
The writing performance of the easy-cone magnetic tunnel junction (MTJ) and perpendicularly magnetized MTJ (pMTJ) under various temperatures was investigated based on the macrospin model. When the temperature is changed from 273 K to 373 K, the switching current density of the pMTJ changes by 56%, whereas this value is only 8% in the easy-cone MTJ. Similarly, the temperature-induced variation of the switching delay is more significant in the pMTJ. This indicates that the easy-cone MTJ has a more stable writing performance under temperature variations, resulting in a wider operating temperature range. In addition, these two types of MTJs exhibit opposite temperature dependence in the current overdrive and write error rate. In the easy cone MTJ, these two performance metrics will reduce as temperature is increased. The results shown in this work demonstrate that the easy-cone MTJ is more suitable to work at high temperatures compared with the pMTJ. Our work provides a guidance for the design of STT-MRAM that is required to operate at high temperatures. Full article
(This article belongs to the Special Issue Memory Nanomaterials: Growth, Characterization and Device Fabrication)
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10 pages, 3584 KiB  
Article
Resistive Switching Memory Cell Property Improvement by Al/SrZrTiO3/Al/SrZrTiO3/ITO with Embedded Al Layer
by Ke-Jing Lee, Wei-Shao Lin, Li-Wen Wang, Hsin-Ni Lin and Yeong-Her Wang
Nanomaterials 2022, 12(24), 4412; https://doi.org/10.3390/nano12244412 - 10 Dec 2022
Viewed by 1052
Abstract
The SrZrTiO3 (SZT) thin film prepared by sol-gel process for the insulator of resistive random-access memory (RRAM) is presented. Al was embedded in the SZT thin film to enhance the switching characteristics. Compared with the pure SZT thin-film RRAM, the RRAM with [...] Read more.
The SrZrTiO3 (SZT) thin film prepared by sol-gel process for the insulator of resistive random-access memory (RRAM) is presented. Al was embedded in the SZT thin film to enhance the switching characteristics. Compared with the pure SZT thin-film RRAM, the RRAM with the embedded Al in SZT thin film demonstrated outstanding device parameter improvements, such as a resistance ratio higher than 107, lower operation voltage (VSET = −0.8 V and VRESET = 2.05 V), uniform film, and device stability of more than 105 s. The physical properties of the SZT thin film and the embedded-Al SZT thin-film RRAM devices were probed. Full article
(This article belongs to the Special Issue Memory Nanomaterials: Growth, Characterization and Device Fabrication)
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8 pages, 2407 KiB  
Article
A Voltage-Modulated Nanostrip Spin-Wave Filter and Spin Logic Device Thereof
by Huihui Li, Bowen Dong, Qi Hu, Yunsen Zhang, Guilei Wang, Hao Meng and Chao Zhao
Nanomaterials 2022, 12(21), 3838; https://doi.org/10.3390/nano12213838 - 30 Oct 2022
Viewed by 1358
Abstract
A nanostrip magnonic-crystal waveguide with spatially periodic width modulation can serve as a gigahertz-range spin-wave filter. Compared with the regular constant-width nanostrip, the periodic width modulation creates forbidden bands (band gaps) at the Brillouin zone boundaries due to the spin-wave reflection by the [...] Read more.
A nanostrip magnonic-crystal waveguide with spatially periodic width modulation can serve as a gigahertz-range spin-wave filter. Compared with the regular constant-width nanostrip, the periodic width modulation creates forbidden bands (band gaps) at the Brillouin zone boundaries due to the spin-wave reflection by the periodic potential owing to the long-range dipolar interactions. Previous works have shown that there is a critical challenge in tuning the band structures of the magnonic-crystal waveguide once it is fabricated. In this work, using micromagnetic simulations, we show that voltage-controlled magnetic anisotropy can effectively tune the band structures of a ferromagnetic–dielectric heterostructural magnonic-crystal waveguide. A uniformly applied voltage of 0.1 V/nm can lead to a significant frequency shift of ~9 GHz. A spin-wave transistor prototype employing such a kind of spin-wave filter is proposed to realize various logical operations. Our results could be significant for future magnonic computing applications. Full article
(This article belongs to the Special Issue Memory Nanomaterials: Growth, Characterization and Device Fabrication)
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8 pages, 2920 KiB  
Article
Pt Modified Sb2Te3 Alloy Ensuring High−Performance Phase Change Memory
by Yang Qiao, Jin Zhao, Haodong Sun, Zhitang Song, Yuan Xue, Jiao Li and Sannian Song
Nanomaterials 2022, 12(12), 1996; https://doi.org/10.3390/nano12121996 - 10 Jun 2022
Cited by 3 | Viewed by 1502
Abstract
Phase change memory (PCM), due to the advantages in capacity and endurance, has the opportunity to become the next generation of general−purpose memory. However, operation speed and data retention are still bottlenecks for PCM development. The most direct way to solve this problem [...] Read more.
Phase change memory (PCM), due to the advantages in capacity and endurance, has the opportunity to become the next generation of general−purpose memory. However, operation speed and data retention are still bottlenecks for PCM development. The most direct way to solve this problem is to find a material with high speed and good thermal stability. In this paper, platinum doping is proposed to improve performance. The 10-year data retention temperature of the doped material is up to 104 °C; the device achieves an operation speed of 6 ns and more than 3 × 105 operation cycles. An excellent performance was derived from the reduced grain size (10 nm) and the smaller density change rate (4.76%), which are less than those of Ge2Sb2Te5 (GST) and Sb2Te3. Hence, platinum doping is an effective approach to improve the performance of PCM and provide both good thermal stability and high operation speed. Full article
(This article belongs to the Special Issue Memory Nanomaterials: Growth, Characterization and Device Fabrication)
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10 pages, 3283 KiB  
Article
Low-Temperature (≤500 °C) Complementary Schottky Source/Drain FinFETs for 3D Sequential Integration
by Shujuan Mao, Jianfeng Gao, Xiaobin He, Weibing Liu, Jinbiao Liu, Guilei Wang, Na Zhou, Yanna Luo, Lei Cao, Ran Zhang, Haochen Liu, Xun Li, Yongliang Li, Zhenhua Wu, Junfeng Li, Jun Luo, Chao Zhao, Wenwu Wang and Huaxiang Yin
Nanomaterials 2022, 12(7), 1218; https://doi.org/10.3390/nano12071218 - 05 Apr 2022
Viewed by 1835
Abstract
In this work, low-temperature Schottky source/drain (S/D) MOSFETs are investigated as the top-tier devices for 3D sequential integration. Complementary Schottky S/D FinFETs are successfully fabricated with a maximum processing temperature of 500 °C. Through source/drain extension (SDE) engineering, competitive driving capability and switching [...] Read more.
In this work, low-temperature Schottky source/drain (S/D) MOSFETs are investigated as the top-tier devices for 3D sequential integration. Complementary Schottky S/D FinFETs are successfully fabricated with a maximum processing temperature of 500 °C. Through source/drain extension (SDE) engineering, competitive driving capability and switching properties are achieved in comparison to the conventional devices fabricated with a standard high-temperature (≥1000 °C) process flow. Schottky S/D PMOS exhibits an ON-state current (ION) of 76.07 μA/μm and ON-state to OFF-state current ratio (ION/IOFF) of 7 × 105, and those for NMOS are 48.57 μA/μm and 1 × 106. The CMOS inverter shows a voltage gain of 18V/V, a noise margin for high (NMH) of 0.17 V and for low (NML) of 0.43 V, with power consumption less than 0.9 μW at VDD of 0.8 V. Full functionality of CMOS ring oscillators (RO) are further demonstrated. Full article
(This article belongs to the Special Issue Memory Nanomaterials: Growth, Characterization and Device Fabrication)
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