Search for Articles:
Title / Keyword
Author / Affiliation / Email
Journal
Article Type
 
 
Advanced Search
 
Section
Special Issue
Volume
Issue
Number
Page
 
7.4
5.3
Journals
Nanomaterials
Special Issues
Innovation in Nanoelectronic Semiconductor Devices and Materials
share announcement

Innovation in Nanoelectronic Semiconductor Devices and Materials

A special issue of Nanomaterials (ISSN 2079-4991). This special issue belongs to the section "Nanoelectronics, Nanosensors and Devices".

Deadline for manuscript submissions: closed (1 January 2024) | Viewed by 8459

Special Issue Editors

Dr. Wei-Tsu Tseng

E-Mail Website
Guest Editor
IBM Semiconductor Technology Research, Albany, NY 12203, USA
Interests: chemical mechanical planarization; Cu interconnects; dielectric materials
Dr. Victor Chan

E-Mail Website
Guest Editor
IBM Semiconductor Technology Research, Albany, NY 12203, USA
Interests: device characterization

Special Issue Information

Dear Colleagues,

From cell phone to mainframe computer, from precision surgery to autonomous driving, semiconductors have been playing pivotal roles in our daily lives, and in technological advancement. The continuous scaling by Moore’s law over the decades has enabled numerous innovations in materials and device architectures that enable new levels of performance. The emergence of 3D devices and heterogeneous integration brings forth opportunities to fulfill critical specifications. As semiconductors enter the nanotechnology sphere, stringent technical challenges require rigorous innovations in devices and materials.

This Special Issue aims to provide a forum for the most up-to-date, high-caliber research efforts in nanoelectronic semiconductor devices and materials. We invite both academic and industrial researchers to submit their works in order to foster the current progress on the subject, and to present new ideas for future applications and new technologies. Potential topics include, but are not limited to:

  • Novel FINFET and nanosheet device architectures and characterization.
  • Materials innovations in gate-all-around nanosheet devices.
  • SiGe and new strained layers for devices.
  • Gate materials and processing for nano devices.
  • Materials and processing issues for 3D NAND memories.
  • Electrode materials and characterization for PCM, MRAM, and other memory devices.
  • ALD and CVD materials for semiconductors.
  • Advanced BEOL interconnects and metallizations.
  • FCVD, SOG, and polymeric materials in advanced semiconductor devices.

Dr. Wei-Tsu Tseng
Dr. Victor Chan
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Nanomaterials is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2900 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • semiconductors
  • nanodevices
  • nanomaterials
  • microelectronics
  • nanoelectronic

Published Papers (5 papers)

Download All Papers
Order results
Result details
Show export options expand_more Show export options expand_less
Select all
Export citation of selected articles as:

Research

Jump to: Review

9 pages, 2517 KiB  
Communication
Temperature-Dependent Feedback Operations of Triple-Gate Field-Effect Transistors
by Taeho Park, Kyoungah Cho and Sangsig Kim
Nanomaterials 2024, 14(6), 493; https://doi.org/10.3390/nano14060493 - 9 Mar 2024
Viewed by 636
Abstract
In this study, we examine the electrical characteristics of triple-gate feedback field-effect transistors (TG FBFETs) over a temperature range of −200 °C to 280 °C. With increasing temperature from 25 °C to 280 °C, the thermally generated charge carriers increase in the channel [...] Read more.
In this study, we examine the electrical characteristics of triple-gate feedback field-effect transistors (TG FBFETs) over a temperature range of −200 °C to 280 °C. With increasing temperature from 25 °C to 280 °C, the thermally generated charge carriers increase in the channel regions such that a positive feedback loop forms rapidly. Thus, the latch-up voltage shifts from −1.01 V (1.34 V) to −11.01 V (10.45 V) in the n-channel (p-channel) mode. In contrast, with decreasing temperature from 25 °C to −200 °C, the thermally generated charge carriers decrease, causing a shift in the latch-up voltage in the opposite direction to that of the increasing temperature case. Despite the shift in the latch-up voltage, the TG FBFETs exhibit ideal switching characteristics, with subthreshold swings of 6.6 mV/dec and 7.2 mV/dec for the n-channel and p-channel modes, respectively. Moreover, the memory window widens with increasing temperature. Specifically, at temperatures above 85 °C, the memory windows are wider than 3.05 V and 1.42 V for the n-channel and p-channel modes, respectively. Full article
(This article belongs to the Special Issue Innovation in Nanoelectronic Semiconductor Devices and Materials)
►▼ Show Figures

Figure 1

11 pages, 5155 KiB  
Article
Photoelectrochemical UV Detector Based on High-Temperature Resistant ITO Nanowire Network Transparent Conductive Electrodes: Both the Response Range and Responsivity Are Improved
by Ying Xiang, Baoping Li, Yitao Fan, Miaomiao Zhang, Wenxuan Wu, Ze Wang, Minghui Liu, Hu Qiao and Youqing Wang
Nanomaterials 2023, 13(14), 2086; https://doi.org/10.3390/nano13142086 - 17 Jul 2023
Viewed by 702
Abstract
UV transparent conductive electrodes based on transferable ITO nanowire networks were prepared to solve the problem of low UV light utilization in conventional photoelectrochemical UV detectors. The mutually cross-linked ITO nanowire network achieved good electrical conductivity and light transmission, and the novel electrode [...] Read more.
UV transparent conductive electrodes based on transferable ITO nanowire networks were prepared to solve the problem of low UV light utilization in conventional photoelectrochemical UV detectors. The mutually cross-linked ITO nanowire network achieved good electrical conductivity and light transmission, and the novel electrode had a transmission rate of more than 80% throughout the near-UV and visible regions. Compared to Ag nanowire electrodes with similar functionality, the chemical stability of the ITO nanowire transparent conductive electrode ensured that the device worked stably in iodine-based electrolytes. More importantly, ITO electrodes composed of oxides could withstand temperatures above 800 °C, which is extremely critical for photoelectrochemical devices. After the deposition of a TiO2 active layer using the high-temperature method, the response range of the photoelectrochemical UV detector was extended from a peak-like response between 300–400 nm to a plateau-like response between 200–400 nm. The responsivity was significantly increased to 56.1 mA/W. The relationship between ITO nanowire properties and device performance, as well as the reasons for device performance enhancement, were intensively investigated. Full article
(This article belongs to the Special Issue Innovation in Nanoelectronic Semiconductor Devices and Materials)
►▼ Show Figures

Figure 1

14 pages, 8698 KiB  
Article
Simulation of Capacitorless DRAM Based on the Polycrystalline Silicon Nanotube Structure with Multiple Grain Boundaries
by Jin Park, Sang-Ho Lee, Ga-Eon Kang, Jun-Hyeok Heo, So-Ra Jeon, Min-Seok Kim, Seung-Ji Bae, Jeong-Woo Hong, Jae-won Jang, Jin-Hyuk Bae, Sin-Hyung Lee and In-Man Kang
Nanomaterials 2023, 13(13), 2026; https://doi.org/10.3390/nano13132026 - 7 Jul 2023
Cited by 3 | Viewed by 1376
Abstract
In this study, a capacitorless one-transistor dynamic random-access memory (1T-DRAM), based on polycrystalline silicon (poly-Si) nanotube structure with a grain boundary (GB), is designed and analyzed using technology computer-aided design (TCAD) simulation. In the proposed 1T-DRAM, the 1T-DRAM cell exhibited a sensing margin [...] Read more.
In this study, a capacitorless one-transistor dynamic random-access memory (1T-DRAM), based on polycrystalline silicon (poly-Si) nanotube structure with a grain boundary (GB), is designed and analyzed using technology computer-aided design (TCAD) simulation. In the proposed 1T-DRAM, the 1T-DRAM cell exhibited a sensing margin of 422 μA/μm and a retention time of 213 ms at T = 358 K with a single GB. To investigate the effect of random GBs, it was assumed that the number of GB is seven, and the memory characteristics depending on the location and number of GBs were analyzed. The memory performance rapidly degraded due to Shockley–Read–Hall recombination depending on the location and number of GBs. In the worst case, when the number of GB is 7, the mean of the sensing margin was 194 µA/µm, and the mean of the retention time was 50.4 ms. Compared to a single GB, the mean of the sensing margin and the retention time decreased by 59.7% and 77.4%, respectively. Full article
(This article belongs to the Special Issue Innovation in Nanoelectronic Semiconductor Devices and Materials)
►▼ Show Figures

Figure 1

14 pages, 2838 KiB  
Article
Anisotropic Resistivity Size Effect in Epitaxial Mo(001) and Mo(011) Layers
by Atharv Jog, Pengyuan Zheng, Tianji Zhou and Daniel Gall
Nanomaterials 2023, 13(6), 957; https://doi.org/10.3390/nano13060957 - 7 Mar 2023
Cited by 7 | Viewed by 2137
Abstract
Mo(001) and Mo(011) layers with thickness d = 4–400 nm are sputter-deposited onto MgO(001) and α-Al2O3(112¯0) substrates and their resistivity is measured in situ and ex situ at room temperature and 77 K in order to [...] Read more.
Mo(001) and Mo(011) layers with thickness d = 4–400 nm are sputter-deposited onto MgO(001) and α-Al2O3(112¯0) substrates and their resistivity is measured in situ and ex situ at room temperature and 77 K in order to quantify the resistivity size effect. Both Mo(001) and Mo(011) layers are epitaxial single crystals and exhibit a resistivity increase with decreasing d due to electron surface scattering that is well described by the classical Fuchs and Sondheimer model. Data fitting yields room temperature effective electron mean free paths λ*= 14.4 ± 0.3 and 11.7 ± 0.3 nm, respectively, indicating an anisotropy with a smaller resistivity size effect for the Mo(011) orientation. This is attributed to a smaller average Fermi velocity component perpendicular to (011) surfaces, causing less surface scattering and a suppressed resistivity size effect. First-principles electronic structure calculations in combination with Boltzmann transport simulations predict an orientation dependent transport with a more pronounced resistivity increase for Mo(001) than Mo(011). This is in agreement with the measurements, confirming the effect of the Fermi surface shape on the thin-film resistivity. The predicted anisotropy λ001*/λ011* = 1.57 is in reasonable agreement with 1.66 and 1.23 measured at 77 and 295 K. The overall results indicate that the resistivity size effect in Mo is relatively small, with a measured product of the bulk resistivity times the effective electron mean free path ρoλ* = (7.7 ± 0.3) and (6.2 ± 0.2) × 10−16 Ωm2 for Mo(001) and Mo(011) layers. The latter value is in excellent agreement with the first-principles-predicted ρoλ = 5.99 × 10−16 Ωm2 and is 10% and 40% smaller than the reported measured ρoλ for Cu and W, respectively, indicating the promise of Mo as an alternate conductor for narrow interconnects. Full article
(This article belongs to the Special Issue Innovation in Nanoelectronic Semiconductor Devices and Materials)
►▼ Show Figures

Graphical abstract

Review

Jump to: Research

19 pages, 12000 KiB  
Review
Cu-Based Thermocompression Bonding and Cu/Dielectric Hybrid Bonding for Three-Dimensional Integrated Circuits (3D ICs) Application
by Yuan-Chiu Huang, Yu-Xian Lin, Chien-Kang Hsiung, Tzu-Heng Hung and Kuan-Neng Chen
Nanomaterials 2023, 13(17), 2490; https://doi.org/10.3390/nano13172490 - 4 Sep 2023
Viewed by 2831
Abstract
Advanced packaging technology has become more and more important in the semiconductor industry because of the benefits of higher I/O density compared to conventional soldering technology. In advanced packaging technology, copper–copper (Cu-Cu) bonding has become the preferred choice due to its excellent electrical [...] Read more.
Advanced packaging technology has become more and more important in the semiconductor industry because of the benefits of higher I/O density compared to conventional soldering technology. In advanced packaging technology, copper–copper (Cu-Cu) bonding has become the preferred choice due to its excellent electrical and thermal properties. However, one of the major challenges of Cu-Cu bonding is the high thermal budget of the bonding process caused by Cu oxidation, which can result in wafer warpage and other back-end-of-line process issues in some cases. Thus, for specific applications, reducing the thermal budget and preventing Cu oxidation are important considerations in low-temperature hybrid bonding processes. This paper first reviews the advancements in low-temperature Cu-based bonding technologies for advanced packaging. Various low-temperature Cu-Cu bonding techniques such as surface pretreatment, surface activation, structure modification, and orientation control have been proposed and investigated. To overcome coplanarity issues of Cu pillars and insufficient gaps for filling, low-temperature Cu-Cu bonding used, but it is still challenging in fine-pitch applications. Therefore, low-temperature Cu/SiO2, Cu/SiCN, and Cu/polymer hybrid bonding have been developed for advanced packaging applications. Furthermore, we present a novel hybrid bonding scheme for metal/polymer interfaces that achieves good flatness and an excellent bonding interface without the need for the chemical mechanical polishing (CMP) process. Full article
(This article belongs to the Special Issue Innovation in Nanoelectronic Semiconductor Devices and Materials)
►▼ Show Figures

Figure 1

Show export options expand_more Show export options expand_less
Select all
Export citation of selected articles as:
 
Displaying articles 1-5
Back to TopTop