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Micromachines
Special Issues
Advancements in MOSFET and Field Effect Devices
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Advancements in MOSFET and Field Effect Devices

A special issue of Micromachines (ISSN 2072-666X). This special issue belongs to the section "D1: Semiconductor Devices".

Deadline for manuscript submissions: closed (15 April 2023) | Viewed by 5787

Special Issue Editor

Prof. Dr. Chettypalayam (Selva) Selvakumar

E-Mail Website
Guest Editor
Department of Electrical and Computer Engineering, University of Waterloo, 200 University Ave W, Waterloo, ON N2L 3G1, Canada
Interests: novel MOSFET design, simulation and reliability; junctionless transistor; exploratory beyond CMOS devices; solar cells and nanotechnology

Special Issue Information

Dear Colleagues,

MOSFET had been the workhorse of the Integrated Circuits for close to 50 years and, starting from late 1980s, the state-of-the-art MOSFET structure moved away from the planar structure, which was one of the foundational features of the Integrated Circuits. The evolution from Multigate, DELTA to FinFETs, GAAFET, Nanowire and junctionless transistors have ushered in a new era. The 3D Transistor structure has advanced to channel lengths as small as 3 nm and projected to progress to 2 nm. The 3D transistor structure had been extended to high mobility Ge-FinFETs and to III-V compound transistors. Numerous challenges exist in the reliable fabrication and integration of these advanced devices as well as modeling and understanding the nanoscale transport properties, the role of ballistic transport, channel quantization, dopant distribution, charge trapping, scaling issues and degradation factors. In this Special Issue the progress made in the theoretical and experimental aspects of the advanced Silicon and non-Silicon MOSFETs will be presented.

Prof. Dr. Chettypalayam (Selva) Selvakumar
Guest Editor

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Micromachines is an international peer-reviewed open access monthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2600 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • silicon and III-V FinFETs
  • FinFET design
  • semiconductor device physics
  • FinFET process
  • FinFET simulation
  • FinFET reliability
  • 3D transistor
  • junctionless transistors
  • tunnel FETs
  • silicon nanowire

Published Papers (2 papers)

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Research

8 pages, 26320 KiB  
Article
Simulation Study: The Impact of Structural Variations on the Characteristics of a Buried-Channel-Array Transistor (BCAT) in DRAM
by Minjae Sun, Hyoung Won Baac and Changhwan Shin
Micromachines 2022, 13(9), 1476; https://doi.org/10.3390/mi13091476 - 5 Sep 2022
Cited by 1 | Viewed by 3214
Abstract
As the physical dimensions of cell transistors in dynamic random-access memory (DRAM) have been aggressively scaled down, buried-channel-array transistors (BCATs) have been adopted in industry to suppress short channel effects and to achieve a better performance. In very aggressively scaled-down BCATs, the impact [...] Read more.
As the physical dimensions of cell transistors in dynamic random-access memory (DRAM) have been aggressively scaled down, buried-channel-array transistors (BCATs) have been adopted in industry to suppress short channel effects and to achieve a better performance. In very aggressively scaled-down BCATs, the impact of structural variations on the electrical characteristics can be more significant than expected. Using a technology computer-aided design (TCAD) tool, the structural variations in BCAT (e.g., the aspect ratio of the BCAT recess-to-gate length, BCAT depth, junction depth, fin width, and fin fillet radius) were simulated to enable a quantitative understanding of its impact on the device characteristics, such as the input/output characteristics, threshold voltage, subthreshold swing, on-/off-current ratio, and drain-induced barrier lowering. This work paves the road for the design of a variation-robust BCAT. Full article
(This article belongs to the Special Issue Advancements in MOSFET and Field Effect Devices)
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14 pages, 6515 KiB  
Article
Comprehensive Power Gain Assessment of GaN-SOI-FinFET for Improved RF/Wireless Performance Using TCAD
by Ajay Kumar, Neha Gupta, Amit Kumar Goyal and Yehia Massoud
Micromachines 2022, 13(9), 1418; https://doi.org/10.3390/mi13091418 - 28 Aug 2022
Cited by 5 | Viewed by 1652
Abstract
In this work, we present a radio frequency (RF) assessment of the nanoscale gallium nitride-silicon-on-insulator fin field-effect transistor (GaN-SOI-FinFET). All the performances of the device were compared with GaN-FinFET and conventional FinFET (Conv. FinFET) simultaneously. All the results show that the power gains [...] Read more.
In this work, we present a radio frequency (RF) assessment of the nanoscale gallium nitride-silicon-on-insulator fin field-effect transistor (GaN-SOI-FinFET). All the performances of the device were compared with GaN-FinFET and conventional FinFET (Conv. FinFET) simultaneously. All the results show that the power gains significantly improved in terms of Gma, Gms, Stern stability factor (SS), GMT, and intrinsic delay in comparison with conventional FinFET. Current gain and unilateral power gain were also evaluated for the extraction of fT (cut-off frequency) and fMAX, respectively. fT and fMAX were enhanced by 88.8% and 94.6%, respectively. This analysis was performed at several THz frequencies. Further, the parametric assessment was also performed in terms of gate length and oxide thickness to find the optimized value of gate length and oxide thickness. The implementation of GaN in the channel reduces the parasitic capacitance and paves the way for high-performance RF applications. Full article
(This article belongs to the Special Issue Advancements in MOSFET and Field Effect Devices)
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