Search for Articles:
Title / Keyword
Author / Affiliation / Email
Journal
Article Type
 
 
Advanced Search
 
Section
Special Issue
Volume
Issue
Number
Page
 
4.7
3.4
Journals
Micromachines
Special Issues
Extremely-Low-Power Devices and Their Applications
share announcement

Extremely-Low-Power Devices and Their Applications

A special issue of Micromachines (ISSN 2072-666X). This special issue belongs to the section "A：Physics".

Deadline for manuscript submissions: closed (30 April 2020) | Viewed by 37437

Special Issue Editor

Prof. Dr. Woo Young Choi

E-Mail Website
Guest Editor
Department of Electronic Engineering, Sogang University, Seoul, Korea
Interests: CMOS/CMOS-compatible novel devices; nano-electromechanical devices; memory devices; monolithic-3D integration and neuromorphic computing devices

Special Issue Information

Dear Colleagues,

Over the past 60 years, the size reduction of electron devices has increased the density and speed of semiconductor chips exponentially. However, as the end of Moore’s law approaches, power-consumption issues are becoming more critical in terms of energy efficiency, reliability, density and even performance. For example, it is expected that the ICT industry will use 20% of all electricity and emit up to 5.5% of the world’s carbon emissions by 2025. Thus, extremely-low-power electronic systems are indispensable to the future of the ICT industry and various pioneering ideas have been proposed, including sharp-switching devices, M/NEMS devices, extremely-low-power memory/sensors, reconfigurable computing devices, neuromorphic devices and so forth. This Special Issue on extremely-low-power devices and their applications will cover the timely topics of pioneering semiconductors, M/NEMS and sensor devices for dramatic power saving and boosting energy efficiency.

Potential topics include, but are not necessarily limited to:

  • Sharp-switching devices (e.g. tunnel FETs, negative capacitance   FETs, impact-ionization MOS, latch-mode SOI MOSFETs, etc.)
  • Micro-/nano-electromechanical devices including relays, memory cells and sensors
  • Extremely-low-power memory
  • Extremely-low-power sensors
  • Reconfigurable computing devices
  • Neuromorphic devices
  • Applications of extremely-low-power devices

Prof. Dr. Woo Young Choi
Guest Editor

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Micromachines is an international peer-reviewed open access monthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2600 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • Sharp-switching devices (e.g. tunnel FETs, negative capacitance FETs, impact-ionization MOS, latch-mode SOI MOSFETs, etc.)
  • Micro-/nano-electromechanical devices including relays, memory cells and sensors
  • Extremely-low-power memory
  • Extremely-low-power sensors
  • Reconfigurable computing devices
  • Neuromorphic devices
  • Applications of extremely-low-power devices

Published Papers (10 papers)

Download All Papers
Order results
Result details
Show export options expand_more Show export options expand_less
Select all
Export citation of selected articles as:

Research

11 pages, 2707 KiB  
Article
Negative Capacitance Vacuum Channel Transistors for Low Operating Voltage
by Woo Young Choi
Micromachines 2020, 11(6), 543; https://doi.org/10.3390/mi11060543 - 27 May 2020
Cited by 4 | Viewed by 3498
Abstract
This study proposes negative capacitance vacuum channel transistors. The proposed negative capacitance vacuum channel transistors in which a ferroelectric capacitor is connected in series to the gate of the vacuum channel transistors have the following two advantages: first, adding a ferroelectric capacitor in [...] Read more.
This study proposes negative capacitance vacuum channel transistors. The proposed negative capacitance vacuum channel transistors in which a ferroelectric capacitor is connected in series to the gate of the vacuum channel transistors have the following two advantages: first, adding a ferroelectric capacitor in series with a gate capacitor makes the turn-on voltage lower and on–off transition steeper without causing hysteresis effects. Second, the capacitance matching between a ferroelectric capacitor and a vacuum channel transistor becomes simplified because the capacitance of a vacuum channel transistor as seen from a ferroelectric capacitor is constant. Full article
(This article belongs to the Special Issue Extremely-Low-Power Devices and Their Applications)
►▼ Show Figures

Figure 1

11 pages, 4094 KiB  
Article
Alpha Particle Effect on Multi-Nanosheet Tunneling Field-Effect Transistor at 3-nm Technology Node
by Jungmin Hong, Jaewoong Park, Jeawon Lee, Jeonghun Ham, Kiron Park and Jongwook Jeon
Micromachines 2019, 10(12), 847; https://doi.org/10.3390/mi10120847 - 04 Dec 2019
Cited by 5 | Viewed by 3024
Abstract
The radiation effects on a multi-nanosheet tunneling-based field effect transistor (NS-TFET) were investigated for a 3-nm technology node using a three-dimensional (3D) technology computer-aided design (TCAD) simulator. An alpha particle was injected into a field effect transistor (FET), which resulted in a drain [...] Read more.
The radiation effects on a multi-nanosheet tunneling-based field effect transistor (NS-TFET) were investigated for a 3-nm technology node using a three-dimensional (3D) technology computer-aided design (TCAD) simulator. An alpha particle was injected into a field effect transistor (FET), which resulted in a drain current fluctuation and caused the integrated circuit to malfunction as the result of a soft-error-rate (SER) issue. It was subsequently observed that radiation effects on NS-TFET were completely different from a conventional drift-diffusion (DD)-based FET. Unlike a conventional DD-based FET, when an alpha particle enters the source and channel areas in the current scenario, a larger drain current fluctuation occurs due to a tunneling mechanism between the source and the channel, and this has a significant effect on the drain current. In addition, as the temperature increases, the radiation effect increases as a result of a decrease in silicon bandgap energy and a resultant increase in band-to-band generation. Finally, the radiation effect was analyzed according to the energy of the alpha particle. These results can provide a guideline by which to design a robust integrated circuit for radiation that is totally different from the conventional DD-FET approach. Full article
(This article belongs to the Special Issue Extremely-Low-Power Devices and Their Applications)
►▼ Show Figures

Figure 1

10 pages, 2202 KiB  
Article
F-Shaped Tunnel Field-Effect Transistor (TFET) for the Low-Power Application
by Seunghyun Yun, Jeongmin Oh, Seokjung Kang, Yoon Kim, Jang Hyun Kim, Garam Kim and Sangwan Kim
Micromachines 2019, 10(11), 760; https://doi.org/10.3390/mi10110760 - 09 Nov 2019
Cited by 19 | Viewed by 3959
Abstract
In this report, a novel tunnel field-effect transistor (TFET) named ‘F-shaped TFET’ has been proposed and its electrical characteristics are analyzed and optimized by using a computer-aided design simulation. It features ultra-thin and a highly doped source surrounded by lightly doped regions. As [...] Read more.
In this report, a novel tunnel field-effect transistor (TFET) named ‘F-shaped TFET’ has been proposed and its electrical characteristics are analyzed and optimized by using a computer-aided design simulation. It features ultra-thin and a highly doped source surrounded by lightly doped regions. As a result, it is compared to an L-shaped TFET, which is a motivation of this work, the F-shaped TFET can lower turn-on voltage (VON) maintaining high on-state current (ION) and low subthreshold swing (SS) with the help of electric field crowding effects. The optimized F-shaped TFET shows 0.4 V lower VON than the L-shaped TFET with the same design parameter. In addition, it shows 4.8 times higher ION and 7 mV/dec smaller average SS with the same VON as that for L-shaped TFET. Full article
(This article belongs to the Special Issue Extremely-Low-Power Devices and Their Applications)
►▼ Show Figures

Figure 1

9 pages, 4322 KiB  
Article
Investigation on Ambipolar Current Suppression Using a Stacked Gate in an L-shaped Tunnel Field-Effect Transistor
by Junsu Yu, Sihyun Kim, Donghyun Ryu, Kitae Lee, Changha Kim, Jong-Ho Lee, Sangwan Kim and Byung-Gook Park
Micromachines 2019, 10(11), 753; https://doi.org/10.3390/mi10110753 - 03 Nov 2019
Cited by 9 | Viewed by 3778
Abstract
L-shaped tunnel field-effect transistor (TFET) provides higher on-current than a conventional TFET through band-to-band tunneling in the vertical direction of the channel. However, L-shaped TFET is disadvantageous for low-power applications because of increased off-current due to the large ambipolar current. In this paper, [...] Read more.
L-shaped tunnel field-effect transistor (TFET) provides higher on-current than a conventional TFET through band-to-band tunneling in the vertical direction of the channel. However, L-shaped TFET is disadvantageous for low-power applications because of increased off-current due to the large ambipolar current. In this paper, a stacked gate L-shaped TFET is proposed for suppression of ambipolar current. Stacked gates can be easily implemented using the structural features of L-shaped TFET, and on- and off-current can be controlled separately by using different gates located near the source and the drain, respectively. As a result, the suppression of ambipolarity is observed with respect to work function difference between two gates by simulation of the band-to-band tunneling generation. Furthermore, the proposed device suppresses ambipolar current better than existing ambipolar current suppression methods. In particular, low drain resistance is achieved as there is no need to reduce drain doping, which leads to a 7% enhanced on-current. Finally, we present the fabrication method for a stacked gate L-shaped TFET. Full article
(This article belongs to the Special Issue Extremely-Low-Power Devices and Their Applications)
►▼ Show Figures

Figure 1

9 pages, 2624 KiB  
Article
Design and Optimization of Germanium-Based Gate-Metal-Core Vertical Nanowire Tunnel FET
by Won Douk Jang, Young Jun Yoon, Min Su Cho, Jun Hyeok Jung, Sang Ho Lee, Jaewon Jang, Jin-Hyuk Bae and In Man Kang
Micromachines 2019, 10(11), 749; https://doi.org/10.3390/mi10110749 - 31 Oct 2019
Cited by 5 | Viewed by 3371
Abstract
In this paper, a germanium-based gate-metal-core vertical nanowire tunnel field effect transistor (VNWTFET) has been designed and optimized using the technology computer-aided design (TCAD) simulation. In the proposed structure, by locating the gate-metal as a core of the nanowire, a more extensive band-to-band [...] Read more.
In this paper, a germanium-based gate-metal-core vertical nanowire tunnel field effect transistor (VNWTFET) has been designed and optimized using the technology computer-aided design (TCAD) simulation. In the proposed structure, by locating the gate-metal as a core of the nanowire, a more extensive band-to-band tunneling (BTBT) area can be achieved compared with the conventional core–shell VNWTFETs. The channel thickness (Tch), the gate-metal height (Hg), and the channel height (Hch) were considered as the design parameters for the optimization of device performances. The designed gate-metal-core VNWTFET exhibits outstanding performance, with an on-state current (Ion) of 80.9 μA/μm, off-state current (Ioff) of 1.09 × 10−12 A/μm, threshold voltage (Vt) of 0.21 V, and subthreshold swing (SS) of 42.8 mV/dec. Therefore, the proposed device was demonstrated to be a promising logic device for low-power applications. Full article
(This article belongs to the Special Issue Extremely-Low-Power Devices and Their Applications)
►▼ Show Figures

Figure 1

11 pages, 3585 KiB  
Article
Design and Investigation of the High Performance Doping-Less TFET with Ge/Si0.6Ge0.4/Si Heterojunction
by Tao Han, Hongxia Liu, Shupeng Chen, Shulong Wang and Wei Li
Micromachines 2019, 10(6), 424; https://doi.org/10.3390/mi10060424 - 24 Jun 2019
Cited by 11 | Viewed by 2661
Abstract
A high performance doping-less tunneling field effect transistor with Ge/Si0.6Ge0.4/Si heterojunction (H-DLTFET) is proposed in this paper. Compared to the conventional doping-less tunneling field effect transistor (DLTFET), the source and channel regions of H-DLTFET respectively use the germanium and [...] Read more.
A high performance doping-less tunneling field effect transistor with Ge/Si0.6Ge0.4/Si heterojunction (H-DLTFET) is proposed in this paper. Compared to the conventional doping-less tunneling field effect transistor (DLTFET), the source and channel regions of H-DLTFET respectively use the germanium and Si0.6Ge0.4 materials to get the steeper energy band, which can also increase the electric field of source/channel tunneling junction. Meanwhile, the double-gate process is used to improve the gate-to-channel control. In addition, the effects of Ge content, electrode work functions, and device structure parameters on the performance of H-DLTFET are researched in detail, and then the above optimal device structure parameters can be obtained. Compared to the DLTFET, the simulation results show that the maximum on-state current, trans-conductance, and output current of H-DLTFET are all increased by one order of magnitude, whereas the off-state current is reduced by two orders of magnitude, so the switching ratio increase by three orders of magnitude. At the same time, the cut-off frequency and gain bandwidth product of H-DLTFET increase from 1.75 GHz and 0.23 GHz to 23.6 GHz and 4.69 GHz, respectively. Therefore, the H-DLTFET is more suitable for the ultra-low power integrated circuits. Full article
(This article belongs to the Special Issue Extremely-Low-Power Devices and Their Applications)
►▼ Show Figures

Figure 1

9 pages, 2167 KiB  
Article
A Technology-Computer-Aided-Design-Based Reliability Prediction Model for DRAM Storage Capacitors
by Woo Young Choi, Gyuhan Yoon, Woo Young Chung, Younghoon Cho, Seongun Shin and Kwang Ho Ahn
Micromachines 2019, 10(4), 256; https://doi.org/10.3390/mi10040256 - 17 Apr 2019
Cited by 4 | Viewed by 4632
Abstract
A full three-dimensional technology-computer-aided-design-based reliability prediction model was proposed for dynamic random-access memory (DRAM) storage capacitors. The model can be used to predict the time-dependent dielectric breakdown as well as leakage current of a state-of-the-art DRAM storage capacitor with a complex three-dimensional structure. [...] Read more.
A full three-dimensional technology-computer-aided-design-based reliability prediction model was proposed for dynamic random-access memory (DRAM) storage capacitors. The model can be used to predict the time-dependent dielectric breakdown as well as leakage current of a state-of-the-art DRAM storage capacitor with a complex three-dimensional structure. Full article
(This article belongs to the Special Issue Extremely-Low-Power Devices and Their Applications)
►▼ Show Figures

Figure 1

10 pages, 2396 KiB  
Article
Design Optimization of Double-Gate Isosceles Trapezoid Tunnel Field-Effect Transistor (DGIT-TFET)
by Hwa Young Gu and Sangwan Kim
Micromachines 2019, 10(4), 229; https://doi.org/10.3390/mi10040229 - 30 Mar 2019
Viewed by 3818
Abstract
Recently, tunnel field-effect transistors (TFETs) have been regarded as next-generation ultra-low-power semi-conductor devices. To commercialize the TFETs, however, it is necessary to improve an on-state current caused by tunnel-junction resistance and to suppress a leakage current from ambipolar current (IAMB). [...] Read more.
Recently, tunnel field-effect transistors (TFETs) have been regarded as next-generation ultra-low-power semi-conductor devices. To commercialize the TFETs, however, it is necessary to improve an on-state current caused by tunnel-junction resistance and to suppress a leakage current from ambipolar current (IAMB). In this paper, we suggest a novel TFET which features double gate, vertical, and trapezoid isosceles channel structure to solve the above-mentioned technical issues. The device design is optimized by examining its electrical characteristics with the help of technology computer-aided design (TCAD) simulation. As a result, double-gate isosceles trapezoid (DGIT) TFET shows a much better performance than the conventional TFET in terms of ON-state current (ION), IAMB, and gate-to-drain capacitance (CGD). It is confirmed that an inverter composed of DGIT-TFETs can operate with less than 1 ns intrinsic delay time and negligible voltage overshoot. Full article
(This article belongs to the Special Issue Extremely-Low-Power Devices and Their Applications)
►▼ Show Figures

Figure 1

8 pages, 3829 KiB  
Article
High On-Current Ge-Channel Heterojunction Tunnel Field-Effect Transistor Using Direct Band-to-Band Tunneling
by Garam Kim, Jaehong Lee, Jang Hyun Kim and Sangwan Kim
Micromachines 2019, 10(2), 77; https://doi.org/10.3390/mi10020077 - 24 Jan 2019
Cited by 19 | Viewed by 4829
Abstract
The main challenge for tunnel field-effect transistors (TFETs) is achieving high on-current (Ion) and low subthreshold swing (SS) with reasonable ambipolar characteristics. In order to address these challenges, Ge-channel heterostructure TFET with Si source and drain region is proposed, and [...] Read more.
The main challenge for tunnel field-effect transistors (TFETs) is achieving high on-current (Ion) and low subthreshold swing (SS) with reasonable ambipolar characteristics. In order to address these challenges, Ge-channel heterostructure TFET with Si source and drain region is proposed, and its electrical characteristics are compared to other TFET structures. From two-dimensional (2-D) device simulation results, it is confirmed that the Si/Ge heterostructure source junction improves Ion and SS characteristics by using the direct band-to-band tunneling current. Furthermore, the proposed structure shows suppressed ambipolar behavior since the Ge/Si heterostructure is used at the drain junction. Full article
(This article belongs to the Special Issue Extremely-Low-Power Devices and Their Applications)
►▼ Show Figures

Figure 1

10 pages, 5145 KiB  
Article
Demonstration of Fin-Tunnel Field-Effect Transistor with Elevated Drain
by Jang Hyun Kim, Hyun Woo Kim, Garam Kim, Sangwan Kim and Byung-Gook Park
Micromachines 2019, 10(1), 30; https://doi.org/10.3390/mi10010030 - 07 Jan 2019
Cited by 22 | Viewed by 3396
Abstract
In this paper, a novel tunnel field-effect transistor (TFET) has been demonstrated. The proposed TFET features a SiGe channel, a fin structure and an elevated drain to improve its electrical performance. As a result, it shows high-level ON-state current (ION) [...] Read more.
In this paper, a novel tunnel field-effect transistor (TFET) has been demonstrated. The proposed TFET features a SiGe channel, a fin structure and an elevated drain to improve its electrical performance. As a result, it shows high-level ON-state current (ION) and low-level OFF-state current (IOFF); ambipolar current (IAMB). In detail, its ION is enhanced by 24 times more than that of Si control group and by 6 times more than of SiGe control group. The IAMB can be reduced by up to 900 times compared with the SiGe control group. In addition, technology computer-aided design (TCAD) simulation is performed to optimize electrical performance. Then, the benchmarking of ON/OFF current is also discussed with other research group’s results. Full article
(This article belongs to the Special Issue Extremely-Low-Power Devices and Their Applications)
►▼ Show Figures

Figure 1

Show export options expand_more Show export options expand_less
Select all
Export citation of selected articles as:
 
Displaying articles 1-10
Back to TopTop