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Micromachines
Special Issues
Semiconductor Power Devices: Reliability and Applications
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Semiconductor Power Devices: Reliability and Applications

A special issue of Micromachines (ISSN 2072-666X). This special issue belongs to the section "D1: Semiconductor Devices".

Deadline for manuscript submissions: closed (28 February 2023) | Viewed by 6690

Special Issue Editor

Dr. Andrea N. Tallarico

E-Mail Website
Guest Editor
Department of Electrical, Electronic, and Information Engineering “Guglielmo Marconi”, Advanced Research Center on Electronic System “Ercole De Castro”, University of Bologna, Campus of Cesena, 47521 Cesena, Italy
Interests: reliability characterization; modeling of semiconductor power devices and circuits

Special Issue Information

Dear Colleagues,

The growing need to reduce CO2 emission requires the urgent development of increasingly efficient power electronic applications based on innovative semiconductor material and power device architectures. The transport, smart mobility, digital industry, and energy sectors massively employ power devices and related complex circuits and systems. These must be performant, cheap and, most importantly, reliable. Consequently, there is a strong need to fabricate new power device technologies, improve their reliability, and develop new circuits capable of exploiting their characteristics.

In these contexts, this Special Issue on “Semiconductor Power Devices: Reliability and Applications” aims to advance the state of the art of power devices, from technology reliability to its application in discrete and integrated power circuits.

Papers are solicited in, but not limited to, the following areas:

  • Semiconductor power device reliability:
    • FEOL: bias temperature instability; threshold voltage hysteresis; hot carrier phenomena; dielectric wear-out and breakdown; charge trapping; time-dependent breakdown; self-heating effects and thermal issues; etc.
    • BEOL: electromigration; stress migration; thermal management; dielectric breakdown; etc.
  • Simulation of power devices and circuits:
    • TCAD, empirical and compact modeling: power device characteristics; reliability; degradation and failure mechanisms; lifetime prediction;
  • Techniques for reliability, health, and failure monitoring and/or prediction: from device (chip, package, module) to circuit (integrated, discrete) level:
    • condition monitoring; AI-based approaches; sensors and data fusion techniques; etc.
  • Applications: design and development of smart power integrated and/or discrete circuits implemented by, but not limited to, emerging technologies, such as GaN and SiC; design for reliability; assessment of components lifetime operating in power circuits/systems.

Dr. Andrea N. Tallarico
Guest Editor

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Micromachines is an international peer-reviewed open access monthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2600 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • power devices
  • silicon and wide bandgap semiconductors
  • discrete and integrated power circuits
  • reliability

Published Papers (4 papers)

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Research

12 pages, 6065 KiB  
Article
A Performance Optimized CSTBT with Low Switching Loss
by Hang Xu, Tianyang Feng, Wenrong Cui, Yafen Yang and David Wei Zhang
Micromachines 2023, 14(5), 1039; https://doi.org/10.3390/mi14051039 - 12 May 2023
Cited by 1 | Viewed by 1247
Abstract
A novel Performance Optimized Carrier Stored Trench Gate Bipolar Transistor (CSTBT) with Low Switching Loss has been proposed. By applying a positive DC voltage to the shield gate, the carrier storage effect is enhanced, the hole blocking capability is improved and the conduction [...] Read more.
A novel Performance Optimized Carrier Stored Trench Gate Bipolar Transistor (CSTBT) with Low Switching Loss has been proposed. By applying a positive DC voltage to the shield gate, the carrier storage effect is enhanced, the hole blocking capability is improved and the conduction loss is reduced. The DC biased shield gate naturally forms inverse conduction channel to speed up turn-on period. Excess holes are conducted away from the device through the hole path to reduce turn-off loss (Eoff). In addition, other parameters including ON-state voltage (Von), blocking characteristic and short circuit performance are also improved. Simulation results demonstrate that our device exhibits a 35.1% and 35.9% decrease in Eoff and turn-on loss (Eon), respectively, in comparison with the conventional shield CSTBT (Con-SGCSTBT). Additionally, our device achieves a short-circuit duration time that is 2.48 times longer. In high-frequency switching applications, device power loss can be reduced by 35%. It should be noted that the additional DC voltage bias is equivalent to the output voltage of the driving circuit, enabling an effective and feasible approach towards high-performance power electronics applications. Full article
(This article belongs to the Special Issue Semiconductor Power Devices: Reliability and Applications)
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11 pages, 3107 KiB  
Article
Impact Ionization Coefficient Prediction of a Lateral Power Device Using Deep Neural Network
by Jingyu Cui, Linglin Ma, Yuxian Shi, Jinan Zhang, Yuxiang Liang, Jun Zhang, Haidong Wang, Qing Yao, Haonan Lin, Mengyang Li, Jiafei Yao, Maolin Zhang, Jing Chen, Man Li and Yufeng Guo
Micromachines 2023, 14(3), 522; https://doi.org/10.3390/mi14030522 - 23 Feb 2023
Viewed by 1171
Abstract
Nowadays, the impact ionization coefficient in the avalanche breakdown theory is obtained using 1-D PN junctions or SBDs, and is considered to be a constant determined by the material itself only. In this paper, the impact ionization coefficient of silicon in a 2D [...] Read more.
Nowadays, the impact ionization coefficient in the avalanche breakdown theory is obtained using 1-D PN junctions or SBDs, and is considered to be a constant determined by the material itself only. In this paper, the impact ionization coefficient of silicon in a 2D lateral power device is found to be no longer a constant, but instead a function of the 2D coupling effects. The impact ionization coefficient of silicon that considers the 2D depletion effects in real-world devices is proposed and extracted in this paper. The extracted impact ionization coefficient indicates that the conventional empirical impact ionization in the Fulop equation is not suitable for the analysis of 2D lateral power devices. The veracity of the proposed impact ionization coefficient is validated by the simulations obtained from TCAD tools. Considering the complexity of direct modeling, a new prediction method using deep neural networks is proposed. The prediction method demonstrates 97.67% accuracy for breakdown location prediction and less than 6% average error for the impact ionization coefficient prediction compared with the TCAD simulation. Full article
(This article belongs to the Special Issue Semiconductor Power Devices: Reliability and Applications)
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8 pages, 4213 KiB  
Article
Integrating a Soft Body Diode in the Super-Junction MOSFET by Using an n−/n+-Buffer Layer
by Zhi Lin, Wei Zeng, Da Wang, Ping Li and Shengdong Hu
Micromachines 2022, 13(12), 2193; https://doi.org/10.3390/mi13122193 - 10 Dec 2022
Cited by 1 | Viewed by 1437
Abstract
In this paper, a novel silicon super-junction (SJ) MOSFET embedded with a soft reverse recovery body diode is proposed and studied by numerical simulation. The device introduces an n+-buffer layer between the n−-buffer layer and the n+-substrate [...] Read more.
In this paper, a novel silicon super-junction (SJ) MOSFET embedded with a soft reverse recovery body diode is proposed and studied by numerical simulation. The device introduces an n+-buffer layer between the n−-buffer layer and the n+-substrate to improve the reverse recovery behaviour of its body diode. The n+-buffer layer provides residual carriers during the reverse recovery process, reduces the overshoot voltage, and suppresses oscillation. Simulated results demonstrate that the increment of the on-resistance and the drain-to-source overshoot voltage can be respectively kept below 5% and 20 V, if a 10 μm n+-buffer layer whose impurity concentration ranges from 4 × 1015 cm−3 to 6 × 1016 cm−3 is used. In addition, the fabrication process is the same as that of the conventional SJ-MOSFET. These features make the proposed SJ-MOSFET suitable for inverter applications. Full article
(This article belongs to the Special Issue Semiconductor Power Devices: Reliability and Applications)
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12 pages, 5694 KiB  
Article
Investigation of a 4H-SiC Trench MOSFET with Back-Side Super Junction
by Lili Zhang, Yuxuan Liu, Junpeng Fang and Yanjuan Liu
Micromachines 2022, 13(10), 1770; https://doi.org/10.3390/mi13101770 - 18 Oct 2022
Cited by 1 | Viewed by 2064
Abstract
In this paper, a 4H-SiC trench gate MOSFET, featuring a super junction layer located on the drain-region side, is presented to enhance the breakdown voltage and the figures of merit (FOM). The proposed structure is investigated and compared with the conventional structure with [...] Read more.
In this paper, a 4H-SiC trench gate MOSFET, featuring a super junction layer located on the drain-region side, is presented to enhance the breakdown voltage and the figures of merit (FOM). The proposed structure is investigated and compared with the conventional structure with a 2D numerical simulator—ATLAS. The investigation results have demonstrated that the breakdown voltage in the proposed structure is enhanced by 21.2%, and the FOM is improved by 39.6%. In addition, the proposed structure has an increased short-circuit capability. Full article
(This article belongs to the Special Issue Semiconductor Power Devices: Reliability and Applications)
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