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Electronics
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Artificial Intelligence and Signal Processing: Circuits and Systems
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Artificial Intelligence and Signal Processing: Circuits and Systems

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Artificial Intelligence".

Deadline for manuscript submissions: 15 August 2024 | Viewed by 996

Special Issue Editor

Dr. Sergey Y. Yurish

E-Mail Website
Guest Editor
International Frequency Sensor Association (IFSA), 08860 Castelldefels, Spain
Interests: smart sensors; optical sensors; frequency measurements
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

Dear Colleagues,

This Special Issue contains extended papers from the 6th International Conference on Advances in Signal Processing and Artificial Intelligence (ASPAI' 2024), 17–19 April 2024, Funchal (Madeira Island), Portugal (https://aspai-conference.com). Advances in artificial intelligence (AI) and signal processing are driving the growth of the artificial intelligence market as improved appropriate technologies are critical to offer enhanced drones, self-driving cars, robotics, etc. Today, more and more sensor manufacturers are using machine learning to sensors and signal data for analysis. Hardware is becoming smaller and sensors are becoming cheaper, making Internet of things devices widely available for a variety of applications ranging from predictive maintenance to user behavior monitoring.  The artificial intelligence market size was USD 428.00 billion in 2022 and is projected to grow from USD 515.31 billion in 2023 to USD 2025.12 billion by 2030, exhibiting a CAGR of 21.6% However, the increased number of sensors in devices will inherently generate higher data throughput, which poses a serious challenge in managing and processing the tremendous amount of sensory information. Furthermore, traditional processing techniques in conventional sensing devices are no longer suitable for systematically labeling, processing, and analyzing the exuberant amount of information. The publication of the journal’s Special Issue will fill in this gap and help to answer to the coming challenges.

You may choose our Joint Special Issue in Algorithms.

Dr. Sergey Y. Yurish
Guest Editor

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • artificial intelligence
  • signal processing
  • microelectronics
  • industrial electronics

Published Papers (1 paper)

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Research

17 pages, 6522 KiB  
Article
Design of a Convolutional Neural Network Accelerator Based on On-Chip Data Reordering
by Yang Liu, Yiheng Zhang, Xiaoran Hao, Lan Chen, Mao Ni, Ming Chen and Rong Chen
Electronics 2024, 13(5), 975; https://doi.org/10.3390/electronics13050975 - 04 Mar 2024
Viewed by 819
Abstract
Convolutional neural networks have been widely applied in the field of computer vision. In convolutional neural networks, convolution operations account for more than 90% of the total computational workload. The current mainstream approach to achieving high energy-efficient convolution operations is through dedicated hardware [...] Read more.
Convolutional neural networks have been widely applied in the field of computer vision. In convolutional neural networks, convolution operations account for more than 90% of the total computational workload. The current mainstream approach to achieving high energy-efficient convolution operations is through dedicated hardware accelerators. Convolution operations involve a significant amount of weights and input feature data. Due to limited on-chip cache space in accelerators, there is a significant amount of off-chip DRAM memory access involved in the computation process. The latency of DRAM access is 20 times higher than that of SRAM, and the energy consumption of DRAM access is 100 times higher than that of multiply–accumulate (MAC) units. It is evident that the “memory wall” and “power wall” issues in neural network computation remain challenging. This paper presents the design of a hardware accelerator for convolutional neural networks. It employs a dataflow optimization strategy based on on-chip data reordering. This strategy improves on-chip data utilization and reduces the frequency of data exchanges between on-chip cache and off-chip DRAM. The experimental results indicate that compared to the accelerator without this strategy, it can reduce data exchange frequency by up to 82.9%. Full article
(This article belongs to the Special Issue Artificial Intelligence and Signal Processing: Circuits and Systems)
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