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Electronics
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Design Tools and Architectures for Coarse-Grained Reconfigurable Computing
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Design Tools and Architectures for Coarse-Grained Reconfigurable Computing

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Computer Science & Engineering".

Deadline for manuscript submissions: closed (1 May 2022) | Viewed by 9583

Special Issue Editors

Prof. Dr. Mário Véstias

E-Mail Website
Guest Editor
Department of Electronics, Telecommunications and Computer Engineering, Polytechnic of Lisbon, 1500-310 Lisboa, Portugal
Interests: reconfigurable computing; embedded high-performance computing; reconfigurable architectures for deep learning; computer arithmetic
Special Issues, Collections and Topics in MDPI journals
Prof. Dr. José Teixeira de Sousa

E-Mail Website
Guest Editor
INESC-ID, Instituto Superior Técnico, Universidade de Lisboa, 1049-001 Lisbon, Portugal
Interests: digital systems design; computer architecture; reconfigurable computing

Special Issue Information

Dear Colleagues,

Emerging applications are pushing the limits of computing platforms. The scalability of integrated circuit technology has slowed down because of the power wall and the cost wall. Performance is no longer the main metric driving the design of computing platforms, being replaced by energy efficiency and cost. On the other side, emergent applications have a fast-evolving cycle, which reduces the lifecycle of application-specific integrated circuits, increasing their cost.

Reconfigurable computing offers good tradeoffs between cost, energy efficiency, and performance, compared to other computing platforms (GPP, GPU, DSP, etc.). Field-programmable gate arrays are the most used reconfigurable devices. Their fine granularity offers a very flexible hardware device but they are difficult to program and high-density FPGAs are expensive. ASICs have a high non-recurring engineering (NRE) cost that is difficult to support with the new emergent applications with a short lifecycle.

Coarse-grained reconfigurable architectures (CGRAs) offer performance and energy efficiency close to those of ASICs and a programmability level closer to application software, offering a good trade-off between NRE and device cost. However, CGRAs have not yet been widely adopted because of a lack of mature architectures and programming tools.

The objective of this Special Issue is to bring together the latest advances in coarse-grained reconfigurable computing (CGRC), including design tools, architectures, and applications.

CGRC topics include, but are not limited to:

  • Coarse-grained reconfigurable architectures;
  • Fine-grained versus coarse-grained computing;
  • Spatial and temporal computation in CGRA;
  • Run-time reconfiguration/adaptation of CGRA;
  • Models of computation for CGRA;
  • Programming tools and compilers for CGRA;
  • Energy-aware compilation for CGRA;
  • Simulation tools for CGRA;
  • CGRA for domain-specific applications (image processing, deep-learning, network processing, etc.);
  • Edge computing and high-performance computing with CGRA.
Prof. Dr. Mário Véstias
Prof. Dr. José Teixeira de Sousa
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • Reconfigurable architectures
  • Coarse-grained reconfigurable computing
  • Hardware acceleration
  • Temporal computation
  • Deep learning with CGRA
  • Image processing with CGRA
  • Edge computing with CGRA
  • Energy-aware reconfigurable architectures

Published Papers (4 papers)

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28 pages, 919 KiB  
Article
CHiPReP—A Compiler for the HiPReP High-Performance Reconfigurable Processor
by Markus Weinhardt, Mohamed Messelka and Philipp Käsgen
Electronics 2021, 10(21), 2590; https://doi.org/10.3390/electronics10212590 - 23 Oct 2021
Cited by 4 | Viewed by 1508
Abstract
This article presents CHiPReP, a C compiler for the HiPReP processor, which is a high-performance Coarse-Grained Reconfigurable Array employing Floating-Point Units. CHiPReP is an extension of the LLVM and CCF compiler frameworks. Its main contributions are (i) a Splitting Algorithm for Data Dependence [...] Read more.
This article presents CHiPReP, a C compiler for the HiPReP processor, which is a high-performance Coarse-Grained Reconfigurable Array employing Floating-Point Units. CHiPReP is an extension of the LLVM and CCF compiler frameworks. Its main contributions are (i) a Splitting Algorithm for Data Dependence Graphs, which distributes the computations of a C loop to Address-Generator Units and Processing Elements; (ii) a novel instruction clustering and scheduling heuristic; and (iii) an integrated placement, pipeline balancing and routing optimization method based on Simulated Annealing. The compiler was verified and analyzed using a cycle-accurate HiPReP simulation model. Full article
(This article belongs to the Special Issue Design Tools and Architectures for Coarse-Grained Reconfigurable Computing)
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18 pages, 36122 KiB  
Article
Reconfigurable Morphological Processor for Grayscale Image Processing
by Bin Zhang
Electronics 2021, 10(19), 2429; https://doi.org/10.3390/electronics10192429 - 07 Oct 2021
Cited by 3 | Viewed by 1938
Abstract
Grayscale morphology is a powerful tool in image, video, and visual applications. A reconfigurable processor is proposed for grayscale image morphological processing. The architecture of the processor is a combination of a reconfigurable grayscale processing module (RGPM) and peripheral circuits. The RGPM, which [...] Read more.
Grayscale morphology is a powerful tool in image, video, and visual applications. A reconfigurable processor is proposed for grayscale image morphological processing. The architecture of the processor is a combination of a reconfigurable grayscale processing module (RGPM) and peripheral circuits. The RGPM, which consists of four grayscale computing units, conducts grayscale morphological operations and implements related algorithms of more than 100 f/s for a 1024 × 1024 image. The periphery circuits control the entire image processing and dynamic reconfiguration process. Synthesis results show that the proposed processor can provide 43.12 GOPS and achieve 8.87 GOPS/mm2 at a 220-MHz system clock. The simulation and experimental results show that the processor is suitable for high-performance embedded systems. Full article
(This article belongs to the Special Issue Design Tools and Architectures for Coarse-Grained Reconfigurable Computing)
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27 pages, 1095 KiB  
Article
Similarity-Aware Architecture/Compiler Co-Designed Context-Reduction Framework for Modulo-Scheduled CGRA
by Zhongyuan Zhao, Weiguang Sheng, Jinchao Li, Pengfei Ye, Qin Wang and Zhigang Mao
Electronics 2021, 10(18), 2210; https://doi.org/10.3390/electronics10182210 - 09 Sep 2021
Cited by 2 | Viewed by 1848
Abstract
Modulo-scheduled coarse-grained reconfigurable array (CGRA) processors have shown their potential for exploiting loop-level parallelism at high energy efficiency. However, these CGRAs need frequent reconfiguration during their execution, which makes them suffer from large area and power overhead for context memory and context-fetching. To [...] Read more.
Modulo-scheduled coarse-grained reconfigurable array (CGRA) processors have shown their potential for exploiting loop-level parallelism at high energy efficiency. However, these CGRAs need frequent reconfiguration during their execution, which makes them suffer from large area and power overhead for context memory and context-fetching. To tackle this challenge, this paper uses an architecture/compiler co-designed method for context reduction. From an architecture perspective, we carefully partition the context into several subsections and only fetch the subsections that are different to the former context word whenever fetching the new context. We package each different subsection with an opcode and index value to formulate a context-fetching primitive (CFP) and explore the hardware design space by providing the centralized and distributed CFP-fetching CGRA to support this CFP-based context-fetching scheme. From the software side, we develop a similarity-aware tuning algorithm and integrate it into state-of-the-art modulo scheduling and memory access conflict optimization algorithms. The whole compilation flow can efficiently improve the similarities between contexts in each PE for the purpose of reducing both context-fetching latency and context footprint. Experimental results show that our HW/SW co-designed framework can improve the area efficiency and energy efficiency to at most 34% and 21% higher with only 2% performance overhead. Full article
(This article belongs to the Special Issue Design Tools and Architectures for Coarse-Grained Reconfigurable Computing)
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23 pages, 510 KiB  
Article
Coarse-Grained Reconfigurable Computing with the Versat Architecture
by João D. Lopes, Mário P. Véstias, Rui Policarpo Duarte , Horácio C. Neto and José T. de Sousa 
Electronics 2021, 10(6), 669; https://doi.org/10.3390/electronics10060669 - 12 Mar 2021
Cited by 3 | Viewed by 3285
Abstract
Reconfigurable computing architectures allow the adaptation of the underlying datapath to the algorithm. The granularity of the datapath elements and data width determines the granularity of the architecture and its programming flexibility. Coarse-grained architectures have shown the right balance between programmability and performance. [...] Read more.
Reconfigurable computing architectures allow the adaptation of the underlying datapath to the algorithm. The granularity of the datapath elements and data width determines the granularity of the architecture and its programming flexibility. Coarse-grained architectures have shown the right balance between programmability and performance. This paper provides an overview of coarse-grained reconfigurable architectures and describes Versat, a Coarse-Grained Reconfigurable Array (CGRA) with self-generated partial reconfiguration, presented as a case study for better understanding these architectures. Unlike most of the existing approaches, which mainly use pre-compiled configurations, a Versat program can generate and apply myriads of on-the-fly configurations. Partial reconfiguration plays a central role in this approach, as it speeds up the generation of incrementally different configurations. The reconfigurable array has a complete graph topology, which yields unprecedented programmability, including assembly programming. Besides being useful for optimising programs, assembly programming is invaluable for working around post-silicon hardware, software, or compiler issues. Results on core area, frequency, power, and performance running different codes are presented and compared to other implementations. Full article
(This article belongs to the Special Issue Design Tools and Architectures for Coarse-Grained Reconfigurable Computing)
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