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Electronics
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Emerging Technologies for Computer Architecture and Parallel Systems
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Emerging Technologies for Computer Architecture and Parallel Systems

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Computer Science & Engineering".

Deadline for manuscript submissions: closed (31 December 2023) | Viewed by 4880

Special Issue Editors

Dr. Minas Dasygenis

E-Mail Website
Guest Editor
Department of Electrical and Computer Engineering, University of Western Macedonia, 50131 Kozani, Greece
Interests: computer architecture; parallelization techniques; embedded systems; computer vision; accelerators; big data
Dr. Athanasios Kakarountas

E-Mail Website
Guest Editor
Department of Computer Science and Biomedical Informatics, University of Thessaly, GR-35131 Lamia, Greece
Interests: computer architecture; embedded systems; hardware accelerators; IoT; hardware security; digital systems; low-power design; design-for-testability
Special Issues, Collections and Topics in MDPI journals
Prof. Dr. Savvas A. Chatzichristofis

E-Mail Website
Guest Editor
Department of Computer Science, Neapolis University Pafos, Pafos 8042, Cyprus
Interests: artificial intelligence; computer vision; educational robotics; image retrieval
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

Dear Colleagues,

Even though research on computer architecture spans a continuous period of over eighty years, it is a vivid area of research because it encompasses a multitude of research topics and its breakthroughs have a substantial impact on individuals, society, and humankind. It is not a stretch to say that computer architecture is prevalent everywhere, affecting our lives. Computer architecture addresses all design and implementation challenges from the single small embedded microprocessor to the high-performance multi-CPU multi-computer cluster. Furthermore, application domains like robotics, autonomous driving, big data, blockchains, machine learning, and others have to keep raising the bar of requirements, vehemently piquing the interest of researchers. Even though the insatiable performance and energy optimization demands are always at the epicenter of novel computer architectures, we can see that new goals have started to surface, like sustainable computer architectures, heterogenous computing, big data, accelerators, approximate computing, and others. All these emerging topics for computer architecture have motivated researchers to present methodologies, tools, and technologies to alleviate the hurdles and move forward with the existing knowledge.

This Special Issue aims to gather contributions on the emerging issues, technologies, approaches, techniques, and applications of homogenous or heterogenous computer architecture (CA) and parallel systems. The topics of interest include, but are not limited to:

Design methodologies for computer architectures;

CAD support for new computer architectures;

Modeling of computer architectures;

Application specific computer architectures;

Heterogenous computing;

Approximate computing;

High performance computing;

Adaptive and reconfigurable computing;

High level synthesis tools and applications;

Evaluation for computer architectures;

Improved memory architectures;

IoT, mobile and embedded computer architecture;

Cloud computer architecture;

Parallelism in instruction, threads, execution units, coprocessors and data;

Multicore or multicomputer architectures;

Optimized input/output computer architectures;

Quantum computing architectures;

Computer architectures and memristors;

CPU interconnectivity and network on chips;

Computer architecture security and resiliency;

Fast prototyping computer architectures;

Verification, evaluation and test of computer architectures

Dr. Minas Dasygenis
Dr. Athanasios Kakarountas
Dr. Savvas A. Chatzichristofis
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • heterogenous systems
  • high performance computers
  • design methodologies
  • accelerators
  • reconfigurable computing
  • parallel computing
  • distributed computing
  • computer architecture
  • hardware security
  • embedded computing

Published Papers (4 papers)

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Research

16 pages, 585 KiB  
Article
Exploring Hardware Fault Impacts on Different Real Number Representations of the Structural Resilience of TCUs in GPUs
by Robert Limas Sierra, Juan-David Guerrero-Balaguera, Josie E. Rodriguez Condia and Matteo Sonza Reorda
Electronics 2024, 13(3), 578; https://doi.org/10.3390/electronics13030578 - 31 Jan 2024
Cited by 1 | Viewed by 613
Abstract
The most recent generations of graphics processing units (GPUs) boost the execution of convolutional operations required by machine learning applications by resorting to specialized and efficient in-chip accelerators (Tensor Core Units or TCUs) that operate on matrix multiplication tiles. Unfortunately, modern cutting-edge semiconductor [...] Read more.
The most recent generations of graphics processing units (GPUs) boost the execution of convolutional operations required by machine learning applications by resorting to specialized and efficient in-chip accelerators (Tensor Core Units or TCUs) that operate on matrix multiplication tiles. Unfortunately, modern cutting-edge semiconductor technologies are increasingly prone to hardware defects, and the trend to highly stress TCUs during the execution of safety-critical and high-performance computing (HPC) applications increases the likelihood of TCUs producing different kinds of failures. In fact, the intrinsic resiliency to hardware faults of arithmetic units plays a crucial role in safety-critical applications using GPUs (e.g., in automotive, space, and autonomous robotics). Recently, new arithmetic formats have been proposed, particularly those suited to neural network execution. However, the reliability characterization of TCUs supporting different arithmetic formats was still lacking. In this work, we quantitatively assessed the impact of hardware faults in TCU structures while employing two distinct formats (floating-point and posit) and using two different configurations (16 and 32 bits) to represent real numbers. For the experimental evaluation, we resorted to an architectural description of a TCU core (PyOpenTCU) and performed 120 fault simulation campaigns, injecting around 200,000 faults per campaign and requiring around 32 days of computation. Our results demonstrate that the posit format of TCUs is less affected by faults than the floating-point one (by up to three orders of magnitude for 16 bits and up to twenty orders for 32 bits). We also identified the most sensible fault locations (i.e., those that produce the largest errors), thus paving the way to adopting smart hardening solutions. Full article
(This article belongs to the Special Issue Emerging Technologies for Computer Architecture and Parallel Systems)
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18 pages, 2315 KiB  
Article
A Conceptual Framework for Developing Intelligent Services (a Platform) for Transport Enterprises: The Designation of Key Drivers for Action
by Maria Sartzetaki, Aristi Karagkouni and Dimitrios Dimitriou
Electronics 2023, 12(22), 4690; https://doi.org/10.3390/electronics12224690 - 18 Nov 2023
Viewed by 1119
Abstract
In the digital era, effective business management relies on dynamic risk analysis and real-time data integration, particularly amid the evolving landscape shaped by technological advancements and external factors such as climate change and global health crises. This study delves into the specific demands [...] Read more.
In the digital era, effective business management relies on dynamic risk analysis and real-time data integration, particularly amid the evolving landscape shaped by technological advancements and external factors such as climate change and global health crises. This study delves into the specific demands for digital services within the transportation sector, focusing on the crucial task of identifying an optimal data-driven management system (platform) to bolster transportation decision-making processes. The paper revolves around the formulation of a comprehensive conceptual framework for the development of intelligent services and platforms tailored explicitly to transport enterprises. Methodologically, a thorough analysis of critical infrastructure-related challenges was conducted, emphasizing the integration of a service-oriented approach to enhance overall functionality. Central to the paper’s approach is the careful navigation of conflicting user requirements, resource constraints, and the imperative of maintaining adaptability in service implementation. Additionally, a robust data flow analysis framework is presented, encompassing data collection, model building, and model extrapolation, which enables the generation of reliable outputs essential for informed decision-making. Notably, the study underscores the pivotal role played by the EN.I.R.I.S.S.T. research infrastructure in delivering essential services to the transportation domain, offering accessible data, user-friendly interfaces, and data analysis tools. The findings highlight the enthusiastic reception of the diverse services among potential users, indicating a strong willingness to engage and benefit from the proposed solutions. By emphasizing the integration of intelligent services, the paper seeks to present a systematic approach aimed at enhancing the efficiency, productivity, and competitive edge of transport enterprises through the strategic deployment of advanced technological solutions and proactive planning. This paper ultimately contributes cutting-edge research insights, empowering transportation managers, planners, and decision-makers with valuable resources for informed business intelligence and corporate strategy. Full article
(This article belongs to the Special Issue Emerging Technologies for Computer Architecture and Parallel Systems)
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23 pages, 4531 KiB  
Article
Evaluation and Benefit of Imprecise Value Prediction for Certain Types of Instructions
by Uroš Radenković, Marko Mićović and Zaharije Radivojević
Electronics 2023, 12(17), 3568; https://doi.org/10.3390/electronics12173568 - 24 Aug 2023
Viewed by 931
Abstract
Based on branch prediction, value prediction has emerged as a solution for problems caused by true data dependencies in pipelined processors. While branch predictors have binary outcomes (taken/not taken), value predictors face a challenging task as their outcomes can take any value. Because [...] Read more.
Based on branch prediction, value prediction has emerged as a solution for problems caused by true data dependencies in pipelined processors. While branch predictors have binary outcomes (taken/not taken), value predictors face a challenging task as their outcomes can take any value. Because of that, coverage is reduced to enhance high accuracy and minimise costly recovery from misprediction. This paper evaluates value prediction, focusing on instruction execution with imprecisely predicted operands whose result can still be correct. Two analytical models are introduced to represent instruction execution with value prediction. One model focuses on correctly predicted operands, while the other allows for imprecisely predicted operands as long as the instruction results remain correct. A trace-driven simulator was developed for simulation purposes, implementing well-known predictors and some of the predictors presented at the latest Championship Value Prediction. The gem5 simulator was upgraded to generate program traces of SPEC and EEMBC benchmarks that were used in simulations. Based on the simulation result, proposed analytical models were compared to reveal the conditions under which a model with imprecisely predicted operands, but still correct results, achieved better execution time than a model with correctly predicted operands. Analysis revealed that the accuracy of the correct instruction result based on the predicted operand, even when the predicted operand is imprecise, is higher than the accuracy of the correctly predicted operand. The accuracy improvement ranges from 0.8% to 44%, depending on the specific predictor used. Full article
(This article belongs to the Special Issue Emerging Technologies for Computer Architecture and Parallel Systems)
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18 pages, 638 KiB  
Article
Fine-Grained CPU Power Management Based on Digital Frequency Divider
by Fan Jia and Longbing Zhang
Electronics 2023, 12(2), 407; https://doi.org/10.3390/electronics12020407 - 13 Jan 2023
Viewed by 1563
Abstract
Dynamic voltage and frequency scaling (DVFS) is a widely used method to improve the energy efficiency of the CPU. Reducing the voltage and frequency during memory-intensive workloads can minimize power consumption without affecting performance, thereby improving overall energy efficiency. A finer-grained DVFS strategy [...] Read more.
Dynamic voltage and frequency scaling (DVFS) is a widely used method to improve the energy efficiency of the CPU. Reducing the voltage and frequency during memory-intensive workloads can minimize power consumption without affecting performance, thereby improving overall energy efficiency. A finer-grained DVFS strategy leads to better energy efficiency. However, due to the limitation of voltage regulators, the implementation granularity of the current DVFS strategies is 100 μs or more. This paper proposes that managing the CPU’s power through a more fine-grained load-aware approach can improve CPU energy efficiency, even with limitations of the voltage regulators. This paper adds a more fine-grained dynamic frequency divider to the DVFS system. This mechanism can improve the processor’s energy efficiency in scenarios where DVFS does not take effect. This paper also proposes a DVFS management strategy based on finer-grained sampling. In order to improve the accuracy of performance estimation, we enhanced the state-of-the-art CRIT method to complete accurate memory time estimation in a shorter interval. The power management strategy was verified on the ChampSim and McPAT simulating platforms. In the SPEC CPU 2017 benchmark, this work saves an average of 16.36% energy consumption and improves energy efficiency by 13.57%. Compared with the state-of-the-art CRIT of 9.77% and 6.79%, this work improved energy consumption and efficiency by 6.20% and 6.35%, respectively. This method brings a 2.04% performance reduction, only a 0.16% drop in performance compared to CRIT. Full article
(This article belongs to the Special Issue Emerging Technologies for Computer Architecture and Parallel Systems)
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