Analysis of the Multi-Steps Package (MSP) for Series-Connected SiC-MOSFETs
, Pierre Lefranc, Pierre-Olivier Jeannin, Benoit Sarrazin and Jean-Christophe Crebier *
Round 1
Reviewer 1 Report
This manuscript presents an analysis on multi-step package and also provides experimental results from prototypes. Overall, this manuscript is well-written, and this reviewer is satisfied with the contents of the manuscript. Here are this reviewer's comments:
- If the conventional approach suffers from the unequal parasitic capacitance across the stacked devices, but the proposed approach relaxes the impact, this reviewer would wonder if integrating the stacked devices in a single chip, instead of stacking multiple chips, will be an eventual solution. Please comment.
- Basically this manuscript is an extension of the authors' previous works. Although this reviewer feels this manuscript contains sufficient amount of new materials over the authors' previous publications, it is concerning that some materials are completely reused (e.g. Figure 7). This reviewer strongly suggests revising such materials.
Author Response
- If the conventional approach suffers from the unequal parasitic capacitance across the stacked devices, but the proposed approach relaxes the impact, this reviewer would wonder if integrating the stacked devices in a single chip, instead of stacking multiple chips, will be an eventual solution. Please comment.
Reply:
Thank you for this question ! Stacking devices would have some benefits and some drawbacks, as usual. From the driver point of view, even if stacked, the gate and source terminals of each power devices would have to be accessed, making parasitc paths for currents to flow under increasing dv/dt. From the packaging point of view, stacking devices would bring a great benefit since there will be no more drain/source potentials with parasitic propagation paths to ground. However, a very strong issue would rise with respect to thermal management. Stacking the devices would concentrate the total losses over a reduced cross section since all devices still produce losses and they are now one on top of the other. In addition, the heat produced by each power device would have to cross the devices below, increasing the temperature rise.
Introducing a cooling layer between each power device in the stack would be benefic from the thermal management point of view but it would rise up a parasitic path through that cooling layer, unless it is totally disconnected from ground.
At the end, the idea is interesting. It is another option to be studied and compared to see how advantages balance drawbacks
- Basically this manuscript is an extension of the authors' previous works. Although this reviewer feels this manuscript contains sufficient amount of new materials over the authors' previous publications, it is concerning that some materials are completely reused (e.g. Figure 7). This reviewer strongly suggests revising such materials.
Reply: Thank you for your comments. As suggested, we modified the reused figures. Please, see below the list of figures that have been modified. In fact those figure are quite traditional and generic figures. Its is like a schematic in topologies. And it is difficult not to reuse similar drawings. We have tried to introduce modifications while keeping the added value of the figures for the reader.
Page 2, Figures 1.
Page 7, Figure 7.
Page 9, Figure 9.
Author Response File: 
Author Response.docx
Reviewer 2 Report
The manuscript presents a multi-step packaging theory for series-connected SiC-MOSFETs. This reviewer's main concern is focused on the results. The authors talked about theoretical and experimental results, but it is unclear how these results compare.
The authors should make a clear comparison of their theoretical and experimental results and explain how the results relate to the present state-of-the-art.
In the "abstract", line 13, the authors should delete the word "novel" as the work presented in the manuscript is not new.
Author Response
The manuscript presents a multi-step packaging theory for series-connected SiC-MOSFETs. This reviewer's main concern is focused on the results. The authors talked about theoretical and experimental results, but it is unclear how these results compare. The authors should make a clear comparison of their theoretical and experimental results and explain how the results relate to the present state-of-the-art.
Reply: Thank you for your suggestion. We added in the revised paper some comments comparing the theoretical analyses with the experimental ones. Please see:
Page 14, lines 392-406 and lines 412-415.
Pages 14-15, lines 423-427, lines 434-435 and lines 440-446.
In the "abstract", line 13, the authors should delete the word "novel" as the work presented in the manuscript is not new.
Reply: Thank you for your remarque. As suggested, we deleted the word “novel” in the abstract. Please, see:
Page 1, lines 13 and 19.
Additionally, we propose to modify the title of the article to reflect more the fact that we are not presenting the MSP concept but we are going to analyze its characteristics.
The paper title would become : Analysis of the Multi Steps Package (MSP) for Series-Connected SiC-MOSFETs.
Author Response File: 
Author Response.pdf
Round 2
Reviewer 2 Report
The paper has been improved but some diagrams re-used from the authors previous work (e.g. Fig.7) needs to be referenced.
Author Response
Comments from reviewer 2:
- The paper has been improved but some diagrams re-used from the authors previous work (e.g. Fig.7) needs to be referenced.
Reply: Thank you for your comments. As suggested, the re-used diagrams have been referenced in the new version of the paper. Please, see:
Page 2, Figures 1.
Page 7, Figure 7.
Page 9, Figure 9.
