Analysis of Cross-Connected Half-Bridges Multilevel Inverter for STATCOM Application

Abstract

This paper suggested a single-phase cross-connected half-bridges multilevel inverter (cchb-mli) topology for static synchronous compensator (statcom) applications. The proposed mli structure consists of cross-connected multilevel cells connected in series with a more optimized number of devices to synthesize a higher number of voltage steps. Each cell in the structure consists of a set of switches and a dc-capacitor. Typically, when several dc-capacitors are used in an inverter, the dc voltages fluctuation occurs due to tolerance between passive element and asymmetric switch losses. A dual-loop control technique has been proposed with level-shifted pulse width modulation pwm to overcome these issues. The proposed methodology balances the dc-voltages using a proportional-integral controller by adjusting the switch duty cycle. The control method helps offset the issue of aggravated fluctuation while preserving the delivered reactive power distributed equally among the dc-capacitors at the same time. A thorough comparison is made between the proposed inverter concerning the number of components and efficiency to demonstrate the effectiveness of previous topologies. Moreover, a simulation model built in simulink and experimental results take from laboratory prototype to confirm the effectiveness of proposed structure and its control technique.

1. Introduction

Multilevel inverters (mlis) technology has become an important developing field in power electronics and has now become a preferred choice for a several medium and high-power applications [1]. The rise in the output voltage steps is one major driving force behind this development. The shape of the voltage waveform approaches a sinusoidal wave if the output voltage steps increases, leading to the depletion of the harmonics in the inverter output voltage. This leads to different power inverters’ performance improvements, such as high-power density, reduction of voltage stress, lower emissions of electromagnetic interference (emi), higher efficiency, long-term reliability, and reduced switching losses [2,3].

Mlis consists of multiple dc sources (such as batteries or capacitors) and switching devices (i.e., igcts or igbts). Many strategies have been taken by scientists to strengthen the efficiency of mlis. Most of these attempts were based on synthesizing higher ac output voltages in the form of staircases by connecting power switches to dc sources and/or dc capacitors [4]. The switch voltage rating and the operating frequency are bound for high power applications. It is an overwhelming challenge and a significant prerequisite to boost the operating frequency by decreasing the switch’s power rating while still retaining viable power quality [5].

The voltage source multilevel inverter (vs-mli) is extensively investigated in the literature for different power converter applications. Over the past few decades, vs-mlis have been widely used in dc-ac or ac-dc conversions, motor drives, battery-powered systems, such as electric vehicle fast-charging stations, and submarine propulsion. Mli has also been considered with the increasing industrial emergence of grid-connected applications such as uninterrupted power supplies (ups), photovoltaic (pv), static synchronous compensator (statcom), and wind power conversion systems [6].

The statcom used vs-mli to control the grid voltage, improve the power factor, control and/or manage reactive power, and stabilize the power system. When the mli for statcom is used, it should be fitted with galvanically isolated dc-capacitors, excluding any dc source. This results in eliminating the use of heavy, bulky, and costly line-side transformers. In addition, an ac inductor should be installed to help to discern the voltage between statcom and the grid. The use of the isolated dc capacitors in an inverter also contributes to an exacerbation of voltage fluctuations in the dc-voltage of statcom [7].

The Dc-voltage fluctuation issue caused the following:

• nonlinear and/or reactive loads
• asymmetric switching/conduction losses produced by switches
• non-ideal passive components
• voltage and current sensors accuracy

Statcom inverters may be narrowly split into two groups in terms of dc capacitors’ voltage ratings, namely symmetric and asymmetric mlis. When similar voltage rating capacitors are used in an inverter, such an inverter is recognized as an symmetric mli. Non-identical voltage rating capacitors, on the other hand, result in an asymmetrical mli [8]. In recent years, both types of topologies have been studied, and several reports have been published in the literature as a consequence. Designers try to investigate the above challenges by posing different new systems with the least number of possible switches.

With several dc sources and/or dc capacitors’ contribution, contemporary, reduced switch structures of the established vs-mli topologies are proposed in [1,4,6,8,9,10,11,12,13,14,15]. While these evolved inverters have numerous advantages over conventional inverters, using the aforementioned traditional structure of inverter requires more devices. This leads to increased circuit size, expense, and design complexity. Moreover, capacitor voltages tend to diverge, resulting in the need for voltage balancing control schemes.

Evidently, by increasing the voltage steps, the performance of mli increases. The number of devices used in an inverter is thus increasing. Consequently, mlis with asymmetric dc sources/capacitors are designed to accomplish a more significant number of voltage steps and reduce the number of devices [16]. In order to synthesize the higher voltage steps with lease number of active and passive components, Ounejjar and Al-Haddad suggested asymmetric packed u-cells (puc) mli in [17]. Packed u-cell topology shows a similarity with the configuration of the flying capacitor (fc) and cascaded H-bridge mli due to the use of isolated dc sources. Although puc-mli has many advantages over conventional topologies, there are also many undesirable features of puc topology.

The limitations in the puc topology are the asymmetrical configuration of the inverter, which cannot made the summation of the dc voltages on the output, while an increase in the voltage levels result in the need for different voltage rating capacitors. The switch power rating is a significant problem for high-power applications that leads to limitations on the inverter’s functionality, and expanding the inverter voltages is not straightforward. Asymmetric packaged u-cell topology is not possible for medium-power grid-connected applications because of these limitations. A modular structure mli composed of a simple module or cells that can easily split the desired voltage is a potential solution [18].

To achieve the required efficiency and resolve the deficiencies described above, Andres et al. introduced a cross-connected half-bridge structure in [19]. This results in the mitigation of individual switch stress, ease of dc voltage balancing control, and intrinsic dc fault tolerance capacity relative to certain other topologies. This topology’s main benefits are that it is more practical due to its simple structure, high reliability, modularity, and efficient to any number of voltage levels. The mli cross-connected half-bridges are well-suited for medium-power grid-connected applications based on these advantages. As for previous literature, it is essential to realize that the cross-connected half-bridge (cchb) application did not appear as a grid-connected (statcom) application candidate.

Mlis-based statcom suffer from harmonic emission, reactive power, and voltage imbalance problems due to multiple dc-capacitors uses. To mitigate harmonics, compensate for reactive power, and regulate the voltage imbalance, different researchers have made significant contributions in this area. Numerous strategies have been developed for active voltage control, highlighting the critical contributions based on proportional resonant, deadbeat and balanced integral control, etc. [20,21,22,23]. By reducing the steady-state uncertainty related to ac signal, the proportional-resonant (pr) controller achieved dominance [20]. However, numerous demerits also exist, such as the sensitivity to slight frequency shifts, the need to handle the difficult task of tuning several resonant frequencies, and the expectation of margins of instability due to the sensors’ phase shift [21]. Deadbeat control shows a good dynamic response. However, this control technique exhibits model indeterminacy sensitivity, parameter inconsistency sensitivity, and noise [22]. A two-stage control method that is a redundant switching state selection (rss) active voltage control is given in [23], where each dc capacitor voltage is compared with the reference value. To change the modulation index to match voltages, the voltage steady-state error is compensated by the proportional and integral (pi) controller for each dc capacitor. However, in the current literature, the cchb-mli dc-capacitor voltage balancing solution is not discussed.

In light of the above, for the statcom application in the current study, a new simple modular structure of five-level cross-connected half-bridges mli is implemented. High power efficiency and an essential decrease in the number of active switches are given by the mli cross-connected half-bridges. By expanding the number of module cells or cascading more modules into the inverter, the voltage rating of the cchb inverter can be easily extended. During startup, it has the advantages of equal capacitor uses and self-balancing. For balancing the voltage capacitor, two-stage voltage balance methods are used. The primary approach is to control feedback dependent upon the proportional-integral, and the second method is to achieve a dc voltage equalization based on the rss method associated with the level-shifted pwm. The voltage-equalization efficiency was analyzed. Although the proposed approach has been applied to five-level cross-connected half-bridges inverter, it can be extended to any number of voltage steps of cchb-mli with relative ease. Furthermore, with minimal steady-state errors, the dynamic response of the voltage balancing is very good. The outcomes of the five-level cchb-mli are validated through the simulated and experimental results that achieved from matlab model and the laboratory prototypes, respectively. Under the same operating conditions, the experimental waveform is measured and compared to that obtained through simulation.

The majority of this paper is organized in the following way. The structure and operating theory are presented in Section 2. Switching losses and the switching scheme are provided in Section 3. Section 4 addresses the control scheme for the proposed topology. The comparison with conventional cascaded H-bridge topology is contrasted in Section 5. The simulated results achieved in the format of performed in Matlab and Simulink and the experimental results achieved from the actual prototype implementation of the proposed topology, were discussed in Section 6. Eventually, the conclusions from the study are provided in Section 7.

2. Five-Level cchb-mli

The fundamental structure of a five-level statcom-based cchb-mli shown in Figure 1. It consists of two dc-capacitors and six active switches. The potentially higher terminal of previous dc-capacitor is linked via active switches to the next dc-link capacitor’s lower potential terminal, and vice versa. Active switches used in the inverter are igbts with an antiparallel diode. Each switch has bi-directional current conduction capability, and the capacitors have unidirectional current conduction ability. The active switches are connected in an alternate direction to each other. Between these active switches, the dc-link capacitor is clamped in. The output voltage has five dc-levels, $\pm 2V_{\mathrm{DC}},\pm V_{\mathrm{DC}}$, and 0. In cchb-mli, due to a series of connected capacitors, the voltages are added through power switches. The total number of output voltage steps ($V_{steps}$) can be expressed as;

$$V_{steps}=2j+1.$$

(1)

The operating principle of five-level cchb-mli is described with $j=2$ identical dc-link capacitors $C_1=C_2=V_{\mathrm{DC}}$. There are eight valid operating modes achieved by $j+1=3$ complementary pairs of switches $S_k,{\overline{S}}_k(k\in \{1,2,3\})$, as mentioned in

Table 1. Switching states of five-level cchb-mli.

Modes	Switching States			Power	Effect on ${\mathit{V}}_{{\mathit{C}}_{\mathit{j}}}$	${\mathit{v}}_{\mathbf{INV}}$
	$S_1$	$S_2$	$S_3$	P	$V_{C_1},V_{C_2}$	$V_{ab}$
1	1	1	1	$P>0$	$\downarrow (V_{C_1}+V_{C_2})$	0
2	0	0	0	$P<0$	$\downarrow (V_{C_1}+V_{C_2})$	0
3	0	1	1	$P>0$	$\uparrow V_{C_1},\downarrow V_{C_2}$	$V_{\mathrm{DC}}$
4	1	0	0	$P<0$	$\uparrow V_{C_1},\downarrow V_{C_2}$	$-V_{\mathrm{DC}}$
5	1	1	0	$P>0$	$\uparrow V_{C_2},\downarrow V_{C_1}$	$V_{\mathrm{DC}}$
6	0	0	1	$P<0$	$\uparrow V_{C_2},\downarrow V_{C_1}$	$-V_{\mathrm{DC}}$
7	0	1	0	$P>0$	$\uparrow (V_{C_1}+V_{C_2})$	$2V_{\mathrm{DC}}$
8	1	0	1	$P<0$	$\downarrow (V_{C_1}+V_{C_2})$	$-2V_{\mathrm{DC}}$

. Figure 2 indicated the possible output voltage levels and conduction paths. Gating signals ${\overline{S}}_k$ are generated by inverting $S_k$. The following equation can easily obtain the voltage stress on each switch $S_{\mathrm{VOLT\; STRESS}\left(j\right)}$:

$$S_{\mathrm{VOLT\; STRESS}\left(j\right)}=V_{C(j-1)}+V_{Cj}.$$

(2)

Due to similar capacitors for voltage rating i.e., $V_{C_1}=V_{C_2}=V_{\mathrm{DC}}$, the voltage stresses appearing on the switch pairs ($S_1,{\overline{S}}_1$,) and ($S_{k+1},{\overline{S}}_{k+1}$,) are equal to $V_{\mathrm{DC}}$. The voltage stress on remaining switches becomes equivalent to $2V_{\mathrm{DC}}$ each.

The voltage ($v_{ab}$ [$\mathrm{V}$]) and the inverter current ($i_{\mathrm{INV}}$ [$\mathrm{A}$]), in relation with dc-link capacitors and the switching function of the cchb inverter can be obtained as follows:

$$v_{ab}=\sum _{k=1}^{j+1}{v}_k.$$

(3)

Here $v_k$ [$\mathrm{V}$] is nodal voltage:

$$v_k={(-1)}^{k+1}(1-S_k)(V_{C\left(k\right)}+V_{C(k-1)}).$$

(4)

Combining (3) and (4), we obtain:

$$v_{ab}=\sum _{k=1}^{j+1}\left[{(-1)}^{k+1}(1-S_k)(V_{C\left(k\right)}+V_{C(k-1)})\right]$$

(5)

$$i_k={(-1)}^{k+1}(S_k-S_{k+1})\times i_{\mathrm{INV}}.$$

(6)

3. Switch Losses and Switching Scheme

3.1. Switch Losses

A significant method for designing an mli is the estimation of device losses. Each switching system consists of an antiparallel diode power switch inside the cchb inverter. The direction of the switching mechanism (switch or diode) depends on the inverter’s current direction. For instance, if the current direction is from a to b, in mode 3, the diodes $\overline{S_1}$ and $S_2$ will conduct, while the $S_3$ switch will conduct as shown in Figure 3a. If indeed the current direction is from b to a, then $\overline{S_1}$ and $S_2$ switches will conduct and $S_3$ diode will conduct as shown in Figure 3b. Analytical analysis of switching, conduct and total losses is performed for the proposed inverter. The system referred to in the power loss calculation in [24], which is based on the extrapolation of the producer’s data sheet, is used. sk60gal123 (Semikron) with a rating of 1200 V, and 50 A is the switching power unit used for the study. For the loss calculation, simulation of current through each system and its data on voltage blocking shall be considered. The total power loss in the mli is mainly due to losses from switching and losses from conduction. Owing to the delay associated with the transition from on to off, the switching failure is inherent and vice versa, as shown in Figure 4. Overall, the distribution of losses shown in Figure 4a shows that in high-frequency switches, the highest loss occurs. The switching losses in $S_2-{\overline{S}}_2$ are minimal since these switches operate at the fundamental frequency, as shown in Figure 4b. Figure 5a depicts the overall switching losses $P_{\mathrm{SW\; LOSSES}}$ [$\mathrm{W}$], which can be expressed as follows:

$$P_{\mathrm{SW\; LOSSES}}=\frac{1}{T}\sum _{j=1}^n(E_{\mathrm{ON}\left(j\right)}+E_{\mathrm{OFF}\left(j\right)}+E_{rr\left(j\right)})$$

(7)

here, n is the number of transitions in a fundamental period T, $E_{\mathrm{ON}}$ and $E_{\mathrm{OFF}}$ are the energy required to turn -on and -off the igbt, respectively.

The conduction loss occurs after the switch is on. The loss of conduction for the on-state resistance and the forward voltage drop across the switch and body diode. Figure 5b shows the conduction losses $P_{\mathrm{COND\; LOSSES}}$ [$\mathrm{W}$] of the switching device (igbt or diode) and can be expressed by the following equation [25]:

$$P_{\mathrm{COND\; LOSSES}}=\frac{1}{T}{\int }_0^T(V_F+R_{\mathrm{ON}}\times i_F)i_{F}dt.$$

(8)

Here, T is the time period of the fundamental frequency, $V_F$ is the on-state forward voltage drop, $R_{\mathrm{ON}}$ is the on-state resistance, and $i_F$ is the forward current through the device.

Figure 6 shows the total losses $\left(P_{\mathrm{T}}\left[\mathrm{W}\right]\right)$ of the inverter, which can be obtained by combining the conduction losses and the switching losses of the switch.

$$P_{\mathrm{T}}=P_{\mathrm{COND\; LOSSES}}+P_{\mathrm{SW\; LOSSES}}.$$

(9)

For statcom application, as discussed earlier in Section 1, the inverter is fitted with dc-capacitors. In inductive mode of operation, these capacitors are connected in parallel with the grid. Ripple losses develop the distinction between dc-capacitor voltages and grid voltage. Therefore, the leakage loss $P_{C_{\mathrm{LEAKAGE}}}$ [$\mathrm{W}$] caused by capacitor leakage current $I_{C_{\mathrm{LEAKAGE}}}$ is [26]:

$$P_{C_{\mathrm{LEAKAGE}}}=I_{C_{\mathrm{LEAKAGE}}}\times V_C.$$

(10)

The esr power loss is equal to:

$$P_{\mathrm{ESR}}=I_{C_{\mathrm{RIPPLE}}}^2\times R_{\mathrm{ESR}}.$$

(11)

$$R_{\mathrm{ESR}}=\frac{tan\varphi }{2\pi f_{s}C}.$$

(12)

Here, $R_{\mathrm{ESR}}$ is the capacitor equivalent resistance, and $I_{C\left(\mathrm{RIPPLE}\right)}$ is the ripple current of the capacitor. $R_{\mathrm{ESR}}$ has the relation Equation (12) with the dissipation factor $tan\varphi$.

The total loss of capacitor is expressed as:

$$P_{C\left(\mathrm{LOSS}\right)}=P_{C\left(\mathrm{LEAKAGE}\right)}+P_{\mathrm{ESR}}.$$

(13)

The loss of inductors can be calculated in the same manner. However the inductor current $i_L$ is sinusoidal, hence considering the equivalent resistant $R_L$ of the inductor. The loss of the filter inductor $P_{L\left(\mathrm{LOSS}\right)}$ [$\mathrm{W}$] is:

$$P_{L\left(\mathrm{LOSS}\right)}=\frac{1}{T}{\int }_0^T{i}_{L\left(\mathrm{RMS}\right)}^2{R}_{L}dt.$$

(14)

However, estimates of power losses lead to designing the necessary heat sinks for effective thermal management. The simulated inverter’s performance for the different current ratings is shown in Figure 7, while, based on measurements, the efficiency of the developed model is 99.12%.

3.2. Proposed Switching Pattern

The suggested topology is based on the modulation technique of the level-shifted carrier. This approach is also spectrally superior to other carrier layouts because, at such unique frequencies, it produces high harmonic concentrations that cancel the output voltage, thus minimizing their overall harmonic distortion. However, if ls-pwm is applied to the cchb inverter, it is important to link each carrier to a specific cell; otherwise, the capacitor’s voltage balancing usual cannot be achieved. This is because the reference signal crosses the carrier at any sampling point and so only the cell connected with the carrier is changed. Consequently, the voltages in the modules will increase or decrease continuously according to the direction of the current $i_{\mathrm{INV}}$, which will differ from their reference values. Therefore, the voltage balance approach is usually slow and relies on the charging conditions. Therefore, to regulate fc voltages at their required dynamic levels, an active balancing method is needed, particularly in transient conditions and unbalanced linear/non-linear loads. Shifted carriers have the same frequency, phase, and magnitude relative to the sine wave reference signal. As shown in the Figure 8, the signal obtained is used for the gating pulse corresponding to the particular voltage levels. The number of level-shifted carriers ($N_{\mathrm{CARRIER}}$) that are required to achieve the required output voltage levels ($V_{\mathrm{VLEVEL}}$) is found through the following:

$$N_{\mathrm{CARRIER}}=V_{\mathrm{LEVEL}}-1.$$

(15)

The center switches ($S_2$ and ${\overline{S}}_2$) are operated by fundamental frequency, while outer switches ($S_1,{\overline{S}}_1$) and ($S_3,{\overline{S}}_3$) switches are operated at high switching frequency.

4. Control Scheme

This section presents the two-stage voltage balancing technique of the cross-connected half-bridges mli. The pi controller minimizes the average dc voltage error at the first step and the level-shifted modulation technique with the redundant switch state selection (rss) method implemented at the second stage. In equalizing dc-link capacitor voltages, cchb-mli redundant switching modes may play an important role.

Noticing Table 1, mode 1, and 2 are redundant states to obtain a zero-voltage level. To achieve $V_{\mathrm{DC}}$, a possible combination of redundant switching states is mode 3 and 5. Similarly, mode 4 and 6 can generate $-V_{\mathrm{DC}}$.

The proposed control scheme is divided into three parts,

• Total capacitor voltage control,
• Statcom current control, and
• Swapping based capacitor voltage control.

4.1. Total Capacitor Voltages Control

The goal is to equalize the mean dc voltage to the value relationship of the dc voltage. Comprehensive capacitor voltage control. We follow a simple traditional proportional and integral control system, as shown in Figure 9. The pi controller normalizes the overall the dc-link capacitor error. To originate the total voltage command, the output value is subtracted from the total dc-link capacitor voltage references ($v_C^{\mathrm{REF}}$). The instantaneous current reference $i_{\mathrm{INV}}^{*}$ is accomplished from the output of the voltage regulator.

$$\begin{array}{cc}\hfill i_{\mathrm{INV}}^{*}& =\left(v_C^{\mathrm{REF}}-\sum _{j=1,2}{v}_{Cj}\right)\left(k_p+K_i\int dt\right)sin\theta \hfill \\ \hfill & =\Delta v_C\times K_{1}sin\theta \hfill \end{array}$$

(16)

4.2. STATCOM Current Control

Statcom’s current control is shown in Figure 9. The current loop control aims to control the reactive power of statcom and to control the inverter current. The current statcom power is expressed in the following equations in theoretical terms:

$$\begin{array}{cc}\hfill v_{\mathrm{INV}}^{*}& =\left(i_{\mathrm{INV}}^{*}-i_{\mathrm{INV}}\right)K_2\hfill \\ \hfill & =\Delta i_{\mathrm{INV}}\times K_2.\hfill \end{array}$$

(17)

Feedback to ls-pwm for the generation of the modulating signal is the output signal. In the next section, the swapping method is suggested and discussed to charge and discharge capacitors equally.

4.3. Swapping Technique

Switching dc-link voltage balancing is the last stage of control in this scheme. This control aims to exchange energy to balance the individual capacitor voltage between the two capacitors. By using redundant switching, the $\pm v$ and 0 voltage levels can be achieved in several ways. The modification rule of the dc-link voltages, in short, can be written as follows

• When ($i_{\mathrm{INV}}\times v_{C_1})<0$, if $v_{C_1}<v_{C_2}$, then $C_1$ will start charging.
• When ($i_{\mathrm{INV}}\times v_{C_2})>0$, if $v_{C_2}<v_{C_1}$, then $C_2$ will start charging.

Using this relation, the $\pm V_{\mathrm{DC}}$ states of the inverter output which can be redundantly selected, is utilized to control the charging or discharging of the dc-capacitors without altering the level shifted pwm.

5. Comparative Study

In this section, conventional topologies are compared to the symmetric fc topology. In

Table 2. Comparison of traditional multilevel inverters with cchb.

Topologies	npc [27]	chb [28]	fc [23]	cchb
Main switches	2 $(n-1)$	2 $(n-1)$	2 $(n-1)$	$(n+1)$
Main diodes	2 $(n-1)$	2 $(n-1)$	2 $(n-1)$	$(n+1)$
Clamping diodes	$(n-1)$$(n-2)$	0	0	0
Dc-sources	$(n-1)$	$(n-1)/2$	$(n-1)$	$(n-1)/2$
Flying capacitors	0	0	$(n-1)$$(n-2)/2$	0
Dc-sources stress	$(n-1)V_{\mathrm{DC}}$	$(n-1)V_{\mathrm{DC}}/2$	$(n-1)V_{\mathrm{DC}}$	$(n-1)V_{\mathrm{DC}}/2$
Pwm scheme	pd-pwm	ps-pwm	pd-pwm	pd-pwm

, the components needed for different traditional single-phase configuration topologies are shown. Among conventional mlis, due to sufficient higher-voltage operation without series devices and its modular design, the cascaded h-Bridge mli topology has been widely used for medium-voltage high-power applications. Therefore, control of dc-link capacitor voltages involves a greater range of voltage sensors, significantly enhancing the cost of the inverter and the statcom system’s complexities. In this section, a comparative study of chb-mli and the proposed topology is discussed. The comparison is performed in terms of the number of devices required, power switches cost, and switch losses. For comparison, both topologies are considered an equal number (n) of input voltage sources ($V_{\mathrm{DC}}$). The input voltage sources are symmetric according to voltage rating, $V_{C_1}=V_{C_2}=V_{\mathrm{DC}}$.

In this section, the traditional topologies are compared with symmetric fc topology. The components required of various traditional topologies for single phase configuration are listed in Table 2. Among conventional mlis, the cascaded h-Bridge mli topology has been widely utilized for medium voltage high power applications, due to the adequate high operating voltage without series devices and its modular layout. To control dc-link capacitor voltages, a huge number of voltage sensors are needed, which significantly increase the cost of the inverter and the complication of statcom system.

5.1. Component Count

A major factor in comparing mli topologies is the number of switches. Not only does a higher range of mli topologies make it costly and more extensive, but it directly affects the performance and reliability. As a result, fewer switches to mli topologies have given rise to considerable importance in academia and industry.

To compare switches, the same chb-mli output voltage levels and proposed topology are considered. Figure 10 shows the number of switches over the inverter voltage levels. For the traditional chb-mli, each percentage of the appropriate voltage level ($V_{\mathrm{LEVEL}}$) according to the number of switches ($S_n$) is given:

$$\begin{array}{cc}\hfill V_{\mathrm{LEVEL\; CHB}}& =2^{S_n/4}+1.\hfill \end{array}$$

(18)

Similarly for proposed topology:

$$V_{\mathrm{LEVEL\; PT}}=S_n-1.$$

(19)

The gain (G) in term of voltage levels ($V_{\mathrm{LEVEL}}$) against number of switches is calculated in the following equation:

$$G_{V_{\mathrm{LEVEL}}}=S_n-2^{S_n/4}.$$

(20)

In percentage, the gain ($G_p$) can be express as:

$$G_p=\frac{S_n-2^{S_n/4}}{2^{S_n/4}+1}\times 100.$$

(21)

The difference between the number of devices is considerably higher by raising the range of output voltage levels of an inverter in the single and three-phase systems.

5.2. Switch Cost

In determining the cost of mlis, power ratings of switches play the most important role. The current of each switch in the proposed topology is the same as the source current due to the series connection. The different switch voltages are not equal to each other. As a result, relative to different topologies, the total switch voltage blocking can be considered a significant index. One of the most important benefits of the mli is the low blocking voltage of switches. The proposed topology is composed of high and low blocking voltage switches. If the cost of low blocking voltage switch $V_x$ is k units, then for $2V_x$ voltage rated switch with the same current rating, the cost will be $\xi k$ units, where $\xi$ can be expressed as:

$$\xi =\frac{\cos \mathrm{t}\mathrm{of}2V_x}{\cos \mathrm{t}\mathrm{of}{V}_x}.$$

(22)

It may be noticed that $\xi$ can vary over a wide range.

The price per unit for the proposed topology (pt) and chb-mli can be found as:

$$\begin{array}{cc}\hfill S_{p\left(\mathrm{CHB}\right)}& =2(V_{\mathrm{LEVEL}}-1)\times k\hfill \end{array}$$

(23)

$$\begin{array}{cc}\hfill S_{p\left(\mathrm{PT}\right)}& =\left((V_{\mathrm{LEVEL}}-3)\xi +4\right)\times k.\hfill \end{array}$$

(24)

Here, $S_p$ is the total price of the switches and p is the unit price. It should also be remembered that as switches are decreased, the number of gate drives can also be decreased, lowering the actual system’s area and weight. Notably, the cost per unit of the proposed and cascaded h-Bridge inverters switches is shown in Figure 11.

5.3. Switching Losses

The proposed topology’s switching losses in this subsection are contrasted with the cascaded h-bridge for the same degree of the output voltage, as explained previously in Section 3.1. The average switching losses $P_{\mathrm{SW\; LOSSES}}$ is defined as:

$$P_{\mathrm{SW\; LOSSES}}=\frac{1}{6}{v}_{b\left(j\right)}\times i\times (t_{\mathrm{ON}}+t_{\mathrm{OFF}})f_j.$$

(25)

Let’s assume that $\delta =\frac{1}{6}i(t_{\mathrm{ON}}+t_{\mathrm{OFF}})$. Then, Equation (25) is rewritten as:

$$P_{\mathrm{SW\; LOSSES}}=\delta \times v_{b\left(j\right)}\times f_j.$$

(26)

Compared to chb, the proposed topology has fewer switches. All of the eight switches of five-level chb will operate at a high switching frequency. The power losses are given by:

$$P_{\mathrm{SW}\_\mathrm{CHB}}=8\times \delta V_{\mathrm{DC}}{f}_s.$$

(27)

The proposed topology (six switches) power losses are defined as:

$$P_{\mathrm{SW}\left(\mathrm{PT}\right)}=\delta [2\left(2V_{\mathrm{DC}}\right)f_{\mathrm{LOW}}+4V_{\mathrm{DC}}\times f_{\mathrm{HIGH}}].$$

(28)

As we know, that four switches in the proposed topology operate with high switching frequency $\left(f_{\mathrm{HIGH}}\right)$ and it switched at $V_{\mathrm{DC}}$ voltage, while two power switches are controlled by low frequency $\left(f_{\mathrm{LOW}}\right)$ and switched at $2V_{\mathrm{DC}}$ voltage. Hence:

$$P_{\mathrm{SW}\left(\mathrm{PT}\right)}=4\times \delta V_{\mathrm{DC}}(f_{\mathrm{HIGH}}+f_{\mathrm{LOW}}).$$

(29)

Considering that $f_{\mathrm{LOW}}$ is much lower than $f_{\mathrm{HIGH}}$, the switching losses can be equal to:

$$P_{\mathrm{SW}\left(\mathrm{PT}\right)}\approx 4\times \delta V_{\mathrm{DC}}\times f_{\mathrm{HIGH}}.$$

(30)

From Equations (27) and (30), it is clearly shown that proposed topology switching losses are much lower than chb, as shown in Figure 7; this is almost half.

6. Results and Discussion

Simulation model using matlab and simulink and laboratory prototype cchb-mli was developed to validate the proposed concept. The voltage balance and current controllers referred to in Figure 9 of Section 4 were simulated and applied. In

Table 3. System Parameters of cchb inverter.

Parameter	Simulation Model	Experimental Prototype
Inductance	$0.7$ mH	$0.7$ mH
Dc-Capacitors	20 mF	20 mF
Switching Frequency	$3.2$ kHz	$3.2$ kHz
Reference Capacitor Voltage	100 V	100 V
Reference dc-link Voltage	200 V	200 V
Grid Voltage (RMS)	100 V	100 V
$k_i\left(p\right)$	1	0.97
$k_v\left(p\right)/k_v\left(i\right)$	1/0.5	1.1/0.7
Control board (dsc)		tms320c28346
Cpld		Altera max II (epm570)

, the experimental prototype parameters are shown in Figure 12. There are two sets of findings to illustrate the validity of the proposed topology and controlling strategy. The cchb-mli is configured in stand-alone mode at the start to analyze the behavior and output waveforms, and no actual and imaginary forces are transferred to the grid, listed in Figure 13. Constant dc-sources are commonly used alone to achieve a five-level output in the inverter.

Consequently, to test the proposed dc-link capacitor voltage balancing technique’s effectiveness under transient and stable state conditions, the second part of the results will be carried out in a grid-connected mode. As statcom is placed into capacitive operation, Figure 14 shows the output voltages and the statcom present. The statcom current $i_{\mathrm{INV}}$ phase angle leads the output voltage $v_{\mathrm{INV}}$ by $\pi /2$ rad.

This transient response is mention in Figure 15. Therefore, the statcom and the grid voltage-current were in quadrature, indicating a more robust dynamic response to the current loop control.

The dc voltage waveforms are highlighted in order to observe the validation of the voltage loop regulation. By enforcing the proposed control, dc voltages stay constant toward the reference value within an acceptable range under reactive power changes. A good balance of the capacitor voltage increases the efficiency of the ac-side waveform. Subsequently, to confirm the necessity of this control, the swapping strategy becomes intentionally disabled. The differences are more considerable, and capacitor voltage $V_{C_1}$ starts to increase before enabling the swapping technique, and $V_{C_2}$ begins to decrease, resulting in statcom voltage imbalance. The imbalance issues cause distortions in the statcom current $i_{\mathrm{INV}}$. However, by enabling the swapping algorithm, the problem of divergence has been resolved. Figure 16 evident that a capacitor voltage converges to the reference value, i.e., 100 V in simulation and experimental waveforms. To evaluate the proposed control dynamic response, the imulated load voltage regulation results are performed. statcom operates in steady-state mode initially, while no load is attached, as shown in Figure 17. The load is linked to the common coupling point (pcc) after a certain time interval, which dispatch in Figure 17. When operating conditions are changed, statcom compensates the current and maintains their respective reference values.

Moreover, the system’s dynamic output is also verified, as shown in Figure 18. Initially, there is no reactive power exchange among statcom and the utility grid, while it works as a steady-state. At $t=40ms$, the reactive load 70.7 $i_{L\left(\mathrm{RMS}\right)}$ is increased at the point of common coupling (pcc). When the transient occurs, the statcom is activated and the load current is compensated over a few cycles. The compensated reactive current becomes stable afterward—see Figure 18. To ensure unit power factor at the load terminals when the grid contribution is zero, statcom supplied reactive power to the load. The offset currents will also be updated dynamically following the new reference. The $v_{\mathrm{INV}}$ and the compensating current $i_{\mathrm{INV}}$ will finally become stable. The findings in Figure 18 show the diverse system output with and without statcom.

Figure 19 demonstrates the simulated waveforms when reactive power $q^{*}$ was increased to 8%, kept constant for 3 $\mathrm{s}$, and again decreased to 8%. Figure 19a shows that statcom does not supply reactive power due to intentionally disabled reactive control. The offsets in the line voltage are compensated in several cycles after enabling statcom control, as shown in Figure 19b. The proposed control might obtain quick reactive power control without delay time. A variation in the $i_{\mathrm{INV}}^{*}$ inverter current command is the purpose of such a voltage decrease.

7. Conclusions

In this paper, the cchb-mli-based statcom is presented. The proposed structure possesses extended capability remarkably. A comprehensive comparison is made between the proposed cchb-mli against well-developed topologies regarding their cost, losses, and efficiency. It is noted that the proposed topology has several merits (i.e., reduced switches, volume, and number of gate drivers) over conventional topologies. Active switch loss estimation and switching logic show that the efficiency of the proposed cchb-mli is significant for high-power applications. The simulated results for the five-level cchb-mli were theoretically predicted and implemented experimentally. With a level-shifted pwm, the proposed dual-loop control makes dc voltages balanced and retained to the reference value. As a consequence, due to asymmetric power losses, aggravated fluctuations and divergence issues are prevented. Finally, the results verified that the cchb-mli topology is a good candidate with good performance in the statcom topology family.