Analysis of DC-Side Snubbers for SiC Devices Application

Abstract

Due to parasitic parameters existing in Silicon Carbide (SiC) devices application, SiC devices have poor turn-off performances. SiC diode and SiC MOSFET have severe turn-off overvoltage and oscillation. The DC-side snubber is one simple suppressing method. The simplest circuit is the high-frequency decoupling capacitor in parallel with the bridge leg. However, choosing the component value is empirical. Based on the turn-off terminal impedances of the SiC diode and the SiC MOSFET, the suppressing mechanism of this DC-side snubber is analyzed. The guideline selection for the component value is provided. Furthermore, the DC-side snubber with a damping resistor is analyzed based on the terminal impedances. The design principles are provided. Finally, the validity and effectiveness of the DC-side snubbers were proven based on the double-pulse test platform.

1. Introduction

In recent years, Silicon Carbide (SiC) devices have emerged as a kind of promising candidates for high-performance power conversion [1,2]. Compared with state-of-the-art silicon devices, they are featured with higher switching speeds and lower switching loss [3,4]. Therefore, the switching frequency of the power electronic equipment with SiC devices has been continuously pushed up to reduce the size of passive components, which realizes the high-power density [5,6]. However, due to parasitic parameters existing in SiC devices application, SiC devices have poor turn-off performances [7]. SiC diode and SiC MOSFET will have severe turn-off overvoltage and oscillation [8,9]. To avoid damaging the devices, the voltage rating must be enough, which will increase the system cost [10,11,12].

The turn-off terminal impedance is used to analyze the mechanism of the turn-off voltage and oscillation of the SiC MOSFET [13,14]. The parasitic capacitors of the SiC MOSFET and the loop parasitic inductors resonate, which amplifies the component of the excitation source and results in the turn-off overvoltage and oscillation [15,16]. The turn-off terminal impedance analysis method can be performed to provide the suppressing guidelines.

The suppressing methods for the turn-off overvoltage and oscillation on devices can be classified into two categories. One method is to reduce the switching speed of devices, which can be implemented by increasing the gate resistor. However, poor switching performances will be attained, including the switching delay time and the switching loss [17,18]. Another method is to add snubbers to the circuit. One type of snubber is connected directly to the devices, such as the R¬–C snubber [19,20] and the R–C–D snubber [21,22]. By these device snubbers, the turn-off overvoltage can be decreased, but the turn-on overcurrent and the loss can be increased. Furthermore, the suppressing effectiveness can be weakened by the added parasitic inductors owning to device snubbers. Therefore, device snubbers are used less in high-speed SiC devices application. Another type of snubber is the DC-side snubber, which is one simple suppressing method. The simplest circuit is the high-frequency decoupling capacitor in parallel with the bridge leg [23]. By DC-side snubbers, a portion of parasitic inductors can be decoupled from the switching power loop. However, choosing the component value is empirical. Moreover, the suppressing effectiveness is not good when the bulk of the decoupling capacitor leads large parasitic inductors to the switching power loop. In a silicon IGBT application, a damping resistor is in series with the high-frequency decoupling capacitor to suppress the turn-off overvoltage [24]. However, the effectiveness will be decreased if parameters are not designed appropriately. Another DC-side snubber in [25] is the high-frequency decoupling capacitor in parallel with the capacitor-damping-resistor branch. The capacitor-damping-resistor branch is used to suppress the low-frequency oscillation on the turn-off voltage. Nevertheless, the low-frequency oscillation cannot be fully eliminated.

Based on previous considerations, this paper aims to design an effective DC-side snubber to suppress the turn-off overvoltage and oscillation for SiC devices application. One contribution from this paper is that the turn-off terminal impedances of the SiC diode and the SiC MOSFET were deduced. By these turn-off terminal impedances, the suppressing mechanisms and design principles of DC-side snubbers can be investigated. Another contribution of this paper is the guideline design for the DC-side snubbers is presented, which can provide the theoretical, not the empirical, design.

The rest of this paper is organized as follows. First, the suppressing mechanism of the simplest DC-side snubber is discussed in detail. Then, the DC-side snubber with the damping resistor is analyzed. Finally, the validity and effectiveness of the DC-side snubbers are verified by experimental results.

2. Suppressing Mechanism of DC-Side Snubber C_DE

In a phase-leg configuration, such as boost, buck-boost, half-bridge, and full-bridge, the active switch makes current communication with the freewheeling diode during the turn-on and turn-off transition of the active switch. The basic cell is shown in Figure 1, with one branch being the output current, I_o, one branch being the freewheeling diode, and one branch being the active switch, which was chosen to study. The input voltage source, V_DC, is constant. The output current, I_o, is constant. C_DC is the DC bulk capacitor. C_DE is the DC-side snubber capacitor. The switch, Q, is driven by the double pulse signal. The switching of Q causes current commutation with the external circuit and the diode, D. However, the parasitic elements existing in the circuit need to be considered due to the high-speed switching SiC MOSFET. The parasitic elements in Figure 1 are the gate–source capacitance (C_GS), the gate–drain capacitance (C_GD), the drain–source capacitance (C_DS), the gate inductance (L_G), the drain inductance (L_D), the source inductance (L_S) of the Q and the junction capacitance (C_F), the cathode inductance (L_C1), and the anode inductance (L_A1) of the diode (D). A SiC diode is employed as the freewheeling diode, which does not have the reverse recovery charge (Q_rr) and has a low voltage drop. L′_bus1, L′_bus2, L′′_bus1, and L′′_bus2 represent the interconnection parasitic inductors of the PCB traces. L_CS are the common source inductances shared by the switching power loop and the gate drive loop. R_G represents the external gate drive resistance. v_P is the gate signal for the SiC MOSFET.

The turn-on switching transition of the SiC MOSFET can be divided into four stages [26], which are the Turn-on Delay Time (Stage 1: t₁–t₂), Current Rising Time (Stage 2: t₂–t₃), Voltage Falling Time (Stage 3: t₃–t₄), and Gate Remaining Charging Time (Stage 4: t₄–t₅). The turn-off switching transition of the SiC MOSFET can be divided into four stages [26], which are the Turn-off Delay Time (Stage 5: t₅–t₆), Voltage Rising Time (Stage 6: t₆–t₇), Current Falling Time (Stage 7: t₇–t₈), and Gate Remaining Discharging Time (Stage 8: t₈–t₉). Figure 2 shows the switching waveforms of the SiC diode and the SiC MOSFET. During Stage 4, the turn-off overvoltage and oscillation of the SiC diode occur. During Stage 7 and Stage 8, the turn-off overvoltage and oscillation of the SiC MOSFET occur.

2.1. Analysis of Stage 4

At t₄, the voltage of the SiC diode, v_F, reaches the input voltage, V_DC. Then the turn-off overvoltage and oscillation on the SiC diode occurs. In this stage, the SiC MOSFET is equivalent to the on-state resistor (R_{DS_on}). Figure 3a shows the equivalent circuit at this stage, in which L′_P is the sum of L_C, L_A, L_D, L_CS, L′′_bus1, and L′′_bus2. L′_bus is the sum of L′_bus1 and L′_bus2. The parasitic capacitors of the SiC MOSFET are neglected because the SiC MOSFET is in the on-state. The terminal impedance Z_{d_1} is calculated as Equation (1), as the following,

$$Z_{\mathrm{d}\_1}(s)=\frac{N_{\mathrm{d}\_1}\left(s\right)}{D_{\mathrm{d}\_1}\left(s\right)},$$

(1)

where N_{d_1}(s) and D_{d_1}(s) are shown in Appendix A. The amplitude–frequency curves of the terminal impedance Z_{d_1} are shown in Figure 4a, based on the parameters in

Table 1. Parameters for drawing the amplitude–frequency curve.

Parameter	Value	Parameter	Value
RDS_on	0.2 Ω	L′P	50 nH
CGD	7.6 pF	L′bus	150 nH
CDS	75 pF	RG	15 Ω
CF	67 pF

. To be consistent with the experimental verification in Section 4, parameters of the SiC MOSFET C2M0080120D and the SiC diode C4D20120A were used. Based on Figure 4a, there are two resonant peaks existing on the terminal impedance Z_{d_1}. The resonant frequencies are expressed as Equations (2) and (3),

$$f_{d\_1\_1}\approx \frac{1}{2\pi \sqrt{L_P^{\prime }\left(\frac{C_{\mathrm{D}\mathrm{E}}{C}_{\mathrm{F}}}{C_{\mathrm{D}\mathrm{E}}+C_{\mathrm{F}}}\right)}},$$

(2)

$$f_{d\_1\_2}\approx \frac{1}{2\pi \sqrt{L_{\mathrm{b}\mathrm{u}\mathrm{s}}^{\prime }\left(C_{\mathrm{D}\mathrm{E}}+{\mathrm{C}}_{\mathrm{F}}\right)}},$$

(3)

where f_{d_1_1} represents the high-resonance frequency of the terminal impedance Z_{d_1}, and f_{d_1_2} represents the low-resonance frequency of the terminal impedance Z_{d_1}. The peak resonant impedances of the terminal impedance Z_{d_1} amplify the excitation source at the resonant frequencies and result in two oscillations overlaying on the turn-off voltage of the SiC diode.

2.2. Analysis of Stage 7 and Stage 8

At t₇, the SiC diode and the SiC MOSFET make a current commutation, and the turn-off overvoltage of the SiC MOSFET occurs. At t₈, the current commutation comes to an end, and the oscillation on the turn-off voltage of the SiC MOSFET occurs. Figure 3b shows the equivalent circuit at these two stages. The capacitor of the SiC diode is neglected because the SiC diode is in the on-state. The terminal impedance Z_{m2_1} is calculated as Equation (4),

$$Z_{\mathrm{m}2\_1}(s)=\frac{N_{\mathrm{m}2\_1}\left(s\right)}{D_{\mathrm{m}2\_1}\left(s\right)},$$

(4)

where N_{m2_1}(s) and D_{m2_1}(s) are shown in Appendix A. The amplitude–frequency curves of the terminal impedance, Z_{m2_1}, are based on the parameters in Table 1, as shown in Figure 4b. In Figure 4b, there are two resonant peaks existing on the terminal impedance Z_{m2_1}, which is the same as the terminal impedance Z_{d_1}. The resonant frequencies are expressed as Equations (2) and (3),

$$f_{\mathrm{m}2\_1\_1}\approx \frac{1}{2\pi \sqrt{L_{\mathrm{P}}^{\prime }\left(\frac{C_{\mathrm{DE}}{C}_{\mathrm{oss}}}{C_{\mathrm{DE}}+C_{\mathrm{oss}}}\right)}},$$

(5)

$$f_{\mathrm{m}2\_1\_2}\approx \frac{1}{2\mathsf{\pi }\sqrt{L_{\mathrm{bus}}^{\prime }\left(C_{\mathrm{DE}}+C_{\mathrm{oss}}\right)}},$$

(6)

where f_{m2_1_1} represents the high-resonance frequency of the terminal impedance Z_{m2_1} and f_{m2_1_2} represents the low-resonance frequency of the terminal impedance Z_{m2_1}, and C_oss = C_GD + C_DS. The peak resonant impedances of the terminal impedance Z_{m2_1} amplify the excitation source at the resonant frequencies and result in two oscillations overlaying on the turn-off voltage of the SiC MOSFET.

2.3. Guideline Selection for Capacitor C_DE

To realize the decouple of the inductor L′_bus from the switching power loop and make inductor L′_bus and parasitic capacitors C_F, C_GD, and C_DS no resonance, capacitor C_DE must be much larger than the parasitic capacitors C_F, C_GD, and C_DS according to Equations (1)–(6). In addition, the impedance Z_{L_1} of the paralleling branches L′_bus and C_DE at the high-resonance frequency f_{d1_1_1} and the high-resonance frequency f_{m2_1_1} should be much lower than the impedance of inductor L′_P. In general, the capacitor C_DE satisfies the inequality in Equation (7). It is considered that capacitor C_DE is large enough than parasitic capacitors C_F, C_GD, and C_DS.

$$C_{\mathrm{DE}}\ge \max (100C_{oss},100C_{\mathrm{F}}).$$

(7)

The impedance Z_{L_1} of the paralleling branches L′_bus and C_DE can be expressed as Equation (8). In addition, Equation (9) should be satisfied and simplified as Equation (10).

$$Z_{\mathrm{L}\_1}(s)=\frac{L_{\mathrm{bus}}^{\prime }s}{C_{\mathrm{DE}}{L}_{\mathrm{bus}}^{\prime }{s}^2+1}.$$

(8)

$$\left\{\begin{array}{l}\left|j2\pi f_{{}_{\mathrm{d}\_1\_1}}{L}_{\mathrm{P}}^{\prime }\right|\gg \left|\frac{j2\pi f_{{}_{\mathrm{d}\_1\_1}}{L}_{\mathrm{bus}}^{\prime }}{{(j2\pi f_{{}_{\mathrm{d}\_1\_1}})}^2{C}_{\mathrm{DE}}{L}_{\mathrm{bus}}^{\prime }+1}\right|\\ \left|j2\pi f_{{}_{\mathrm{m}2\_1\_1}}{L}_{\mathrm{P}}^{\prime }\right|\gg \left|\frac{j2\pi f_{{}_{\mathrm{m}2\_1\_1}}{L}_{\mathrm{bus}}^{\prime }}{{(j2\pi f_{{}_{\mathrm{m}2\_1\_1}})}^2{C}_{\mathrm{DE}}{L}_{\mathrm{bus}}^{\prime }+1}\right|\end{array}\right..$$

(9)

Assuming that L′_bus = nL′_P. Equation (9) can be simplified as Equation (10),

$$C_{\mathrm{DE}}\gg \max \left(\left(1+\frac{1}{n}\right)C_{\mathrm{F}},\left(1+\frac{1}{n}\right)C_{\mathrm{oss}}\right).$$

(10)

As simplified steps of Equation (7), Equation (11) represents that capacitor C_DE satisfies Equation (10).

$$C_{\mathrm{DE}}\ge \max \left(100\left(1+\frac{1}{n}\right)C_{\mathrm{F}},100\left(1+\frac{1}{n}\right)C_{\mathrm{oss}}\right).$$

(11)

In Figure 4, capacitor C_DE is set to none, 0.1 nF, 1 nF, 10 nF, 100 nF, and 1000 nF, respectively. When capacitor C_DE is larger than 10nF, the peak impedances on the terminal impedances, Z_{d_1} and Z_{m2_1}, are obviously smaller than without the capacitor C_DE. In addition, the high-resonance frequencies are scarcely affected by capacitor C_DE. However, the low-frequency resonances are still affected by the capacitor C_DE. Based on Equations (3) and (6), the low-frequency resonances are caused by the capacitor C_DE and inductor L′_bus. The voltage fluctuation, ∆v_CDE, on capacitor C_DE can be calculated as Equation (12). Assuming that the limitation of the voltage fluctuation is ∆V_CDE, capacitor C_DE also needs to satisfy Equation (13).

$$\Delta v_{\mathrm{CDE}}=I_{\mathrm{o}}\sqrt{\frac{L_{\mathrm{bus}}^{\prime }}{C_{\mathrm{DE}}}}\sin \left(\frac{t}{\sqrt{L_{\mathrm{bus}}^{\prime }{C}_{\mathrm{DE}}}}\right).$$

(12)

$$C_{\mathrm{DE}}\ge \frac{4I_{\mathrm{o}}^2}{\Delta V_{\mathrm{CDE}}^2}{L}_{\mathrm{bus}}^{\prime }.$$

(13)

In summary, the DC-side snubber C_DE needs to satisfy Equation (14), and the decoupling of the parasitic inductor L′_bus and the suppression for the low-frequency oscillation on the turn-off voltage can be realized.

$$C_{\mathrm{DE}}\ge \max (100C_{\mathrm{F}},100C_{oss},100\left(1+\frac{1}{n}\right)C_{\mathrm{F}},100\left(1+\frac{1}{n}\right)C_{\mathrm{oss}},\frac{4I_{\mathrm{o}}^2}{\Delta V_{\mathrm{CDE}}^2}{L}_{\mathrm{bus}}^{\prime }).$$

(14)

2.4. Analyzation for the Suppressing Effectiveness of Capacitor C_DE

Assume the peak impedances, Z_{d_1_H_P} and Z_{m2_1_H_P}, of the SiC diode and SiC MOSFET with the capacitor C_DE are 1/ρ times the peak impedances, Z_{d_H_P} and Z_{m2_H_P}, without the capacitor C_DE. Equations (15)–(18) express the peak impedances without and with the capacitor C_DE.

$$Z_{\mathrm{d}\_\mathrm{H}\_\mathrm{P}}=\frac{L_{\mathrm{P}}^{\prime }+L_{\mathrm{b}\mathrm{u}\mathrm{s}}^{\prime }}{R_{\mathrm{D}\mathrm{S}\_\mathrm{o}\mathrm{n}}{C}_{\mathrm{F}}},$$

(15)

$$Z_{\mathrm{m}2\_\mathrm{H}\_\mathrm{P}}=\frac{\left(L_{\mathrm{P}}^{\prime }+L_{\mathrm{b}\mathrm{u}\mathrm{s}}^{\prime }\right)C_{oss}}{R_{\mathrm{G}}{C}_{\mathrm{G}\mathrm{D}}^2},$$

(16)

$$Z_{\mathrm{d}\_1\_\mathrm{H}\_\mathrm{P}}=\frac{L_{\mathrm{P}}^{\prime }}{R_{\mathrm{D}\mathrm{S}\_\mathrm{o}\mathrm{n}}{C}_{\mathrm{F}}},$$

(17)

$$Z_{\mathrm{m}2\_1\_\mathrm{H}\_\mathrm{P}}=\frac{L_{\mathrm{P}}^{\prime }{C}_{oss}}{R_{\mathrm{G}}{C}_{\mathrm{G}\mathrm{D}}^2}.$$

(18)

Therefore, Equation (19) can be derived based on the relations between the peak impedances Z_{d_H_P}, Z_{m2_H_P} and Z_{d_1_H_P}, Z_{m2_1_H_P}.

$$\rho \le n+1.$$

(19)

Figure 5 presents the amplitude–frequency curves of terminal impedances, Z_{d_1} and Z_{m2_1}, with different n values based on parameters in Table 1. Inductors L′_bus and L′_P are set to 50 nH, 150 nH or 100 nH, 100 nH, respectively, which means n = 3 or n = 1. Based on Figure 5, the larger n is, the smaller L′_P is, which represents that the capacitor C_DE is closer to the devices, the lower the peak impedance is. Compared to without C_DE, the peak impedance of terminal impedances, Z_{d_1} and Z_{m2_1}, with C_DE is reduced nearly n/(n + 1) times.

3. Analyzation for DC-Side Snubber with Damping Resistor C_DE–R_DE

When the DC-side snubber C_DE cannot be selected large enough to avoid the low-frequency oscillation on the turn-off voltage, the suppressing effectiveness is not good owning to the bigger capacitor with parasitic inductors added to the switching power loop. The DC-side snubber with a damping resistor can be used to solve this problem, which is the high-frequency decoupling capacitor in series with a damping resistor. Figure 6 shows the equivalent circuits with this DC-side snubber. Capacitor C_DE is to decouple the parasitic inductor L′_bus, and resistor R_DE is to dampen the low-frequency oscillation on the turn-off voltage.

If capacitor C_DE satisfies Equation (7) and Equation (11) and realizes the decoupling of the inductor L′_bus from the switching power loop, the low-frequency resonance is only caused by the capacitor C_DE and inductor L′_bus. The impedance Z_{L_2} of the paralleling branches L′_bus and C_DE-R_DE can be calculated as Equation (20),

$$Z_{\mathrm{L}\_2}(s)=\frac{(C_{\mathrm{DE}}{R}_{\mathrm{DE}}s+1)L_{\mathrm{bus}}^{\prime }s}{C_{\mathrm{DE}}{L}_{\mathrm{bus}}^{\prime }{s}^2+C_{\mathrm{DE}}{R}_{\mathrm{DE}}s+1}.$$

(20)

Due to the damping resistor R_DE that is in series with capacitor C_DE, the impedance Z_{L_2} at the high-resonance frequency f_{d1_1_1} and the high-resonance frequency f_{m2_1_1} should be much lower than the impedance of inductor L′_P. The relations can be expressed as Equation (21),

$$\left\{\begin{array}{l}\left|j2\pi f_{{}_{\mathrm{d}\_1\_1}}{L}_{\mathrm{P}}^{\prime }\right|\gg \left|\frac{(j2\pi f_{{}_{\mathrm{d}\_1\_1}}{C}_{\mathrm{DE}}{R}_{\mathrm{DE}}+1)j2\pi f_{{}_{\mathrm{d}\_1\_1}}{L}_{\mathrm{bus}}^{\prime }}{{(j2\pi f_{{}_{\mathrm{d}\_1\_1}})}^2{C}_{\mathrm{DE}}{L}_{\mathrm{bus}}^{\prime }+j2\pi f_{{}_{\mathrm{d}\_1\_1}}{C}_{\mathrm{DE}}{R}_{\mathrm{DE}}+1}\right|\\ \left|j2\pi f_{{}_{\mathrm{m}2\_1\_1}}{L}_{\mathrm{P}}^{\prime }\right|\gg \left|\frac{(j2\pi f_{{}_{\mathrm{m}2\_1\_1}}{C}_{\mathrm{DE}}{R}_{\mathrm{DE}}+1)j2\pi f_{{}_{\mathrm{m}2\_1\_1}}{L}_{\mathrm{bus}}^{\prime }}{{(j2\pi f_{{}_{\mathrm{m}2\_1\_1}})}^2{C}_{\mathrm{DE}}{L}_{\mathrm{bus}}^{\prime }+j2\pi f_{{}_{\mathrm{m}2\_1\_1}}{C}_{\mathrm{DE}}{R}_{\mathrm{DE}}+1}\right|\end{array}\right..$$

(21)

Assuming that C_DE = m₁C_F and C_DE = m₂C_oss, Equation (21) can be simplified as

$$\left\{\begin{array}{l}{R}_{\mathrm{DE}}\ll R_{\mathrm{DE}1}\\ R_{\mathrm{DE}}\ll R_{\mathrm{DE}2}\end{array}\right.,$$

(22)

where R_DE1 = ((1 − nm₁)² − n²)/((n² − 1)(n + 1)m₁))^1/2((L′_bus + L′_P)/C_DE)^1/2 and R_DE2 = (((1 − nm₂)² − n²)/((n² − 1)(n + 1) m₂))^1/2((L′_bus + L′_P)/C_DE)^1/2. To reduce the scale of the damping resistor R_DE, Equation (22) can be simplified as,

$$R_{\mathrm{DE}}\le \min (\frac{1}{5}{R}_{\mathrm{DE}1},\frac{1}{5}{R}_{\mathrm{DE}2}).$$

(23)

Due to its discriminant of Equation (20), the low-frequency resonances on the terminal impedances, Z_{d_1} and Z_{m2_1}, of the SiC diode and SiC MOSFET can be cancelled completely when the damping resistor R_DE satisfies Equation (24).

$$R_{\mathrm{DE}}\ge R_{\mathrm{DE}3},$$

(24)

where R_DE3 = 2(n/(n + 1))^1/2((L′_bus + L′_P)/C_DE)^1/2. According to Equations (23) and (24), Figure 7 shows the range of the damping resistor R_DE. The larger n is, the smaller the range of the damping resistor R_DE is.

According to Figure 7, the terminal impedances, Z_{d_2} and Z_{m2_2}, of the SiC diode and SiC MOSFET can be calculated as Equations (25) and (26),

$$Z_{\mathrm{d}\_2}(s)=\frac{N_{\mathrm{d}\_2}\left(s\right)}{D_{\mathrm{d}\_2}\left(s\right)},$$

(25)

$$Z_{\mathrm{m}2\_2}(s)=\frac{N_{\mathrm{m}2\_2}\left(s\right)}{D_{\mathrm{m}2\_2}\left(s\right)}.$$

(26)

where N_{d_2}(s), D_{d_2}(s), N_{m2_2}(s), and D_{m2_2}(s) are shown in Appendix A. The amplitude–frequency curves of Z_{d_2} and Z_{m2_2}, based on Table 1, are shown in Figure 8. From Figure 8, the low-frequency peak impedances of Z_{d_2} and Z_{m2_2} are eliminated, which indicates this DC-side snubber can effectively suppress the low-frequency oscillation on turn-off voltage. In addition, if resistor R_DE satisfies its range requirement, the high-resonance frequency of the terminal impedance, Z_{d_2} and Z_{m2_2}, is scarcely affected, and the high-frequency peak impedances are reduced. It is indicated that inductor L′_bus can be decoupled from the switching power loop, and resistor R_DE has suppressing effectiveness on the turn-off overvoltage.

4. Experimental Results

To verify the suppressing effectiveness of DC-side snubbers, experiments using the 1200V SiC MOSFET C2M0080120D and the SiC diode C4D20120A by Cree Inc. are marked based on the double-pulse-test circuit. Figure 9 presents the testing platform, and

Table 2. Test equipment used in the platform.

Model	Type	Bandwidth
Tektronix TCP0030A	Current probe	120 M
Tektronix DPO4054B	Oscilloscope	500 M
CP3308R	Passive probe	300 M
SSDN-10	Coaxial Shunt	2000 M

shows the test equipment used in the platform.

Figure 10 shows the experimental waveforms without and with capacitor C_DE, in which capacitor C_DE is the multilayer ceramic capacitor and C_DE = 100 nF. In Figure 10a,b, the turn-off voltage of the SiC diode is presented. In Figure 10c,d, the turn-off voltage of the SiC MOSFET is presented. Compared to results in Figure 10a,c, without capacitor C_DE, the turn-off overvoltage of the SiC diode and SiC MOSFET reduces obviously in Figure 10b,d. However, it is shown that the low-frequency oscillation overlays the high-frequency oscillation on the turn-off voltage of the SiC diode and SiC MOSFET.

Figure 11 shows the experimental waveforms with capacitor C_DE and resistor R_DE, in which C_DE = 100 nF and R_DE = 2.5 Ω or R_DE = 5 Ω. In Figure 11a,b, the turn-off voltage of the SiC diode is presented. In Figure 11c,d, the turn-off voltage of the SiC MOSFET is presented. Compared to the results in Figure 10b,d, the low-frequency oscillations on the turn-off voltage of the SiC diode and SiC MOSFET are suppressed effectively. In addition, the turn-off overvoltage of the SiC diode and SiC MOSFET are reduced in Figure 11a,c, in which resistor R_DE = 2.5 Ω. Comparing Figure 11a,c with Figure 11b,d, the turn-off overvoltage of the SiC diode and SiC MOSFET were obviously increased when R_DE = 5 Ω.

Figure 12 presents the turn-off overvoltage of the SiC diode and the SiC MOSFET at different I_o, V_DC, and R_G. From Figure 12, although the higher I_o, higher V_DC, and lower R_G make the turn-off overvoltage higher, DC-side snubbers have effective suppression on the turn-off overvoltage of the SiC diode and SiC MOSFET. Moreover, the DC-side snubber with the damping resistor C_DE-R_DE is the most effective. Figure 13 presents the effect of DC-side snubbers on the switching losses of the SiC MOSFET at different I_o and V_DC. Figure 13 employs the switching losses of the SiC MOSFET without the snubber as a reference quantity and transforms the switching losses with DC-side snubbers into per-unit. The turn-on loss of the SiC MOSFET with DC-side snubbers increases, and the turn-off loss of the SiC MOSFET decrease, because a portion of parasitic inductors is decoupled from the power switching loop. Figure 14 presents the efficiency of a 1.1kW buck converter with DC-side snubbers. The tested conditions of the buck converter are presented in

Table 3. Efficiency-tested conditions of the buck converter.

Parameter	Value	Parameter	Value
Input voltage	600 V	Switching frequency	50 kHz
Output voltage	150 V	Output inductor	100 µH
Output power	700 W~1100 W	Output capacitor	220 µF

, and the efficiency is tested under open-loop control. From Figure 14, it is observed that the efficiency of the buck converter with C_DE = 100 nF, R_DE = 2.5 Ω is a little lower than with C_DE = 100 nF, which is owning to the loss of R_DE.

5. Conclusions

This paper designs effective DC-side snubbers to suppress the turn-off overvoltage and oscillation for SiC devices application. By the turn-off terminal impedances of the SiC diode and SiC MOSFET, the suppressing mechanisms and design principles of DC-side snubbers are investigated. Based on the above analysis and experimental results, the following conclusions can be drawn:

(1)

According to the guideline design for DC-side snubbers, the turn-off overvoltage and oscillation of the SiC diode and the SiC MOSFET can be suppressed effectively.

(2)

Capacitor C_DE is closer to devices, which represents the parasitic inductors in the switching power loop are lower, which means the lower the peak impedance is and the lower the turn-off overvoltage is.

(3)

The DC-side snubber with the damping resistor C_DE-R_DE can not only eliminate the low-frequency oscillation on the turn-off voltage but also can reduce the turn-off overvoltage.