A Low-Power, Fully Integrated SC DC–DC Step-Up Converter with Phase-Reduced Soft-Charging Technique for Fully Implantable Neural Interfaces

Round 1

Reviewer 1 Report

This paper presents a high power conversion efficiency (PCE) on-chip switched-capacitor (SC) dc-9 dc step-up converter for a fully implantable neural interface operating with less than a few tens μW 10 from energy harvesting. I have some minor comments:

1. Please distinguish the power line and communication line in Figure 1. How does the module MPPT work with the battery and the converter?

2.  Page 2, line 79, no space is needed between "80" and "%".

3. Page 4, Line 123, the comma is not needed before the word "where".

4. All the variables and parameters in formulas should be claimed formally.

5. A space is needed between "12nm", "8V", where they should be revised as  "12 nm" and "8 V". Please correct all kinds of typos in Table 1 and Figure 8.

6. The advantages of the proposed on-chip structure should be highlighted in the Introduction.

 

Author Response

I'm very pleased for your reviewing this paper despite your busy schedule. Here is a reply to your comments.

1 : Thanks for a good point. To describe the role of the line and that of MPPT clearly, figure 1 was modified and the below sentence was inserted in line 65-68.
(The MPPT module sensing the condition of input or output according to the type of their algorithm allows the dc-dc converter to operate at a point where it can produce maximum power and if necessary, a battery is used to store excess energy.)

2, 3, 5 : Modified it as you told. 

4 : The variables and parameters are claimed in figure 2 and the former description before introducing formulas.

6 : To highlight the advantages of the proposed on-chip structure, the last paragraph of the introduction mainly described it. 

A revised manuscript is attached.

Thank you again for your review.

Author Response File: Author Response.docx

Reviewer 2 Report

1.      Summary

In this paper, authors have presented a switched-capacitor(SC) based step-up converter with a high power conversion efficiency (PCE).  The authors have implemented the design on a chip using 180nm CMOS technology. The proposed technique received a PCE of 80%.

2.      General comments

I believe the authors wrote the abstract appropriately. The abstract would have looked better if they had stated the issue they are addressing through this paper in the initial couple of sentences.

The introduction section was meticulously written. Section 2 and 3, was appropriately presented. Section 4, describing the measurement results, was appropriate and accepted. On the positive side, I really like the way authors compared their findings with other published work. The conclusion section was appropriate

3.      Improvements that you could suggest on the paper

Major Improvement:

·         None

Minor Improvement:

·         None

 

4.      Verdict

 

Accept the paper in its current form. 

Author Response

Thank you very much for reviewing this paper despite your busy schedule.

best regards,

Sangmin Song

Reviewer 3 Report

Authors present a high power conversion efficiency (PCE) on-chip switched-capacitor (SC) dc-dc step-up converter for a fully implantable neural interface operating with less than a few tens µW from energy harvesting. To improve the PCE in such light loads and wide variations of voltage conversion ratio (VCR), which is a typical scenario for ultra-low power fully implantable systems depending on energy harvesting, a phase-reduced soft-charging technique has been implemented in a step-up converter, thereby achieving very low VCR-sensitive PCE variation compared with other state-of-the-art works. The proposed dc-dc converter has been fabricated in a standard 180 nm CMOS 1P6M process. It exhibits high PCE (~80%) for wide input and output ranges from 0.5 V to 16 1.2 V and from 1.2 V to 1.8 V, respectively with switching frequencies of 0.3 – 2 MHz, achieving a peak efficiency of 82.6% at 54 µW loads.

The work is very interesting and the paper is well-written and organized. I have only some comment/suggestion reported in the following.

1) At the end of the introduction, the paper structure should be reported.

2) The target field of IMD powered by energy harvesters is an hot topic today and monolithic SC-based micro-power boost converters' topologies, also known as charge pumps, are continuously investigated and introduced in literature. Architectures of such circuits change sensibly basing on the used harvester because output signal forms and levels change. To give an example, pn-junction used as solar cell can provide relatively high DC voltages (up to 650 mV) that are deeply different by the few tens or hundreds of mV given by TEGs. For these last, DC-DC boost converters must be able to work with a very low input voltage or a kick-start auxiliary circuit is needed to start-up the main converter. A case totally different is that of ultrasound-based energy harvesting where piezoelectric devices are used as implantable electric generator. The voltage generated by such kind of device is an AC type, therefore an AC-DC converter must be used to adapt the signal form to the continuous current exploitable to feed the various circuits equipped in the IMD (sensors/acturators, communication systems, etc...).

I would suggest to the authors to better specify as the converter topology, in its generical conception, can change basing on the used internal power source. Moreover, I would suggest some paper (review and proposing papers which are focused on the field of study of this work and are related to different kind of energy harvesters) that could be included in the bibliography :

- A review of power management integrated circuits for ultrasound-based energy harvesting in implantable medical devices;

- A subthreshold cross-coupled hybrid charge pump for 50-mV cold-start

- A Bulk Current Regulation Technique for Dual-Branch Cross-Coupled Charge Pumps

3) It is not so clear, for me, PCE results in the last term of (5). What expressions are replaced to achieve the result PCE = n/(n+1). How the PCE is made independent by the parameter "m" ?

4) Are the gate voltage of the transistors used as switches bootstrapped by any mechanism or internal node voltages are reused to provide them ? It has been shown that start-up issues have determined the adoption of a start-up strategy (disconnect the output load until the output voltage reaches a reference voltage ), but during the earlier phase all the switches work or initial charge distribution among the various pumping capacitors happens by means other effects ?

5) It should be curious if the PCE vs. output current or PCE vs. output power is shown.

6) The proposed system outperforms very interesting performances, unfortunately the occupied silicon area is wide and effectively the widest as compared with the other work reported in table 1. An additional metric useful to compare different topologies implemented with different technology nodes is the power density defined as the ration between the maximum output power (or the nominal one) and the area.

For the rest, a good work.

 

Author Response

I'm very pleased for your reviewing this paper despite your busy schedule. Here is a reply to your comments.

1) The proposed structure was briefly described at the end of the introduction but mainly described in section 2 because graphically introducing it helps to understand clearly.

2) Thank you for the good point. We emphasized the possibility of combining with various energy sources in the introduction, but as you suggested, there was a lack of notice of the converter's characteristics that should be changed according to the type of energy source. We add the good examples you recommended to the reference to help the reader understand.

3) When equations (1) and (3) are substituted into equation (5), an independent result is obtained for m.

4) In the case of the gate voltage of the switch, the bottom side switch SB uses Vin, the top side switch ST uses Vout, and the bootstrap does not used.
In the case of the start-up issue, it was confirmed via simulation that Vout reached 300mV through sub-Vth region during the earlier phase when MVT transistor was used, and after that, normal operation is performed.

5) As a result of measuring while changing the load current or power of about three kinds due to complexity in measurement, a flat efficiency curve could be obtained, but only the result at a single power was described to show performance at a certain condition.

6) Since all flying caps were used as MIM caps for future combinations with on-chip photodiodes, the power density is certainly low. The low power density was designed in advance, so it was not added as a metric of the table.

A revised manuscript is attached.

Thank you again for your review.

Author Response File: Author Response.docx